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---- ----
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---- Ethernet Switch on Configurable Logic IP Core ----
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---- ----
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---- This file is part of the ESoCL project ----
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---- http://www.opencores.org/cores/esoc/ ----
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---- ----
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---- Description: see design description ESoCL_dd_71022001.pdf ----
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---- ----
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
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---- and/or release bulleting ESoCL_rb_71022001.pdf ----
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---- ----
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---- Author(s): L.Maarsen ----
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---- Bert Maarsen, lmaarsen@opencores.org ----
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---- ----
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-- Object : Entity work.esoc_reset
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-- Last modified : Mon Apr 14 12:49:49 2014.
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use work.package_esoc_configuration.all;
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entity esoc_reset is
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port(
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clk_control : in std_logic;
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esoc_areset : in std_logic;
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pll1_locked : in STD_LOGIC;
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pll2_locked : in STD_LOGIC;
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reset : out std_logic);
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end entity esoc_reset;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.esoc_reset.esoc_reset
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-- Last modified : Mon Apr 14 12:49:49 2014.
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--------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------------------
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-- architecture and declarations
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---------------------------------------------------------------------------------------------------------------
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architecture esoc_reset of esoc_reset is
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---------------------------------------------------------------------------------------------------------------
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-- signals
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---------------------------------------------------------------------------------------------------------------
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signal esoc_areset_sync : std_logic_vector(1 downto 0);
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begin
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--=============================================================================================================
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-- Process : synchronise asynchronous reset input plus filtering
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-- Description :
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--=============================================================================================================
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sync: process(clk_control,pll1_locked,pll2_locked)
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begin
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-- keep device in reset if pll's not locked
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if pll1_locked = '0' or pll2_locked = '0' then
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esoc_areset_sync <= (others => '1');
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-- synchronise external reset
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elsif clk_control'event and clk_control = '1' then
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esoc_areset_sync <= esoc_areset & esoc_areset_sync(esoc_areset_sync'high downto 1);
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end if;
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end process;
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reset <= esoc_areset_sync(0);
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end architecture esoc_reset ; -- of esoc_reset
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