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[/] [esoc/] [trunk/] [Sources/] [logixa/] [esoc_search_engine.vhd] - Blame information for rev 49

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1 42 lmaarsen
--------------------------------------------------------------------------------
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----                                                                        ----
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---- Ethernet Switch on Configurable Logic IP Core                          ----
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----                                                                        ----
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---- This file is part of the ESoCL project                                 ----
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---- http://www.opencores.org/cores/esoc/                                   ----
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----                                                                        ----
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---- Description: see design description ESoCL_dd_71022001.pdf              ----
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----                                                                        ----
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf                   ----
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----        and/or release bulleting ESoCL_rb_71022001.pdf                  ----
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----                                                                        ----
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---- Author(s): L.Maarsen                                                   ----
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---- Bert Maarsen, lmaarsen@opencores.org                                   ----
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----                                                                        ----
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--------------------------------------------------------------------------------
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----                                                                        ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG                           ----
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----                                                                        ----
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---- This source file may be used and distributed without                   ----
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---- restriction provided that this copyright statement is not              ----
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---- removed from the file and that any derivative work contains            ----
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---- the original copyright notice and the associated disclaimer.           ----
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----                                                                        ----
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---- This source file is free software; you can redistribute it             ----
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---- and/or modify it under the terms of the GNU Lesser General             ----
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---- Public License as published by the Free Software Foundation;           ----
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---- either version 2.1 of the License, or (at your option) any             ----
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---- later version.                                                         ----
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----                                                                        ----
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---- This source is distributed in the hope that it will be                 ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied             ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                ----
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---- PURPOSE. See the GNU Lesser General Public License for more            ----
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---- details.                                                               ----
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----                                                                        ----
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---- You should have received a copy of the GNU Lesser General              ----
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---- Public License along with this source; if not, download it             ----
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---- from http://www.opencores.org/lgpl.shtml                               ----
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----                                                                        ----
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--------------------------------------------------------------------------------
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-- Object        : Entity work.esoc_search_engine
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-- Last modified : Mon Apr 14 12:49:54 2014.
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--------------------------------------------------------------------------------
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use work.package_esoc_configuration.all;
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entity esoc_search_engine is
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  port(
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    clk_control         : in     std_logic;
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    clk_search          : in     std_logic;
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    ctrl_address        : in     std_logic_vector(15 downto 0);
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    ctrl_rd             : in     std_logic;
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    ctrl_rddata         : out    std_logic_vector(31 downto 0);
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    ctrl_wait           : out    std_logic;
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    ctrl_wr             : in     std_logic;
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    ctrl_wrdata         : in     std_logic_vector(31 downto 0);
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    reset               : in     std_logic;
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    search_eof          : in     std_logic;
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    search_key          : in     std_logic_vector(63 downto 0);
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    search_port_stalled : in     std_logic_vector(esoc_port_count-1 downto 0);
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    search_result       : out    std_logic_vector(esoc_port_count-1 downto 0);
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    search_result_av    : out    std_logic;
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    search_sof          : in     std_logic);
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end entity esoc_search_engine;
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--------------------------------------------------------------------------------
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-- Object        : Architecture work.esoc_search_engine.esoc_search
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-- Last modified : Mon Apr 14 12:49:54 2014.
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--------------------------------------------------------------------------------
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architecture esoc_search of esoc_search_engine is
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  signal q_b                       : STD_LOGIC_VECTOR(79 downto 0);
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  signal sa_wren                   : STD_LOGIC := '1';
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  signal data_b                    : STD_LOGIC_VECTOR(79 downto 0);
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  signal address_b                 : STD_LOGIC_VECTOR(12 downto 0);
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  signal wren_a                    : STD_LOGIC := '1';
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  signal address_a                 : STD_LOGIC_VECTOR(12 downto 0);
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  signal data_a                    : STD_LOGIC_VECTOR(79 downto 0);
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  signal q_a                       : STD_LOGIC_VECTOR(79 downto 0);
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  signal search_sa_drop_cnt        : std_logic;
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  signal search_entry_age_time     : std_logic_vector(11 downto 0);
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  signal wrreq                     : STD_LOGIC;
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  signal data                      : STD_LOGIC_VECTOR(79 downto 0);
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  signal wrfull                    : STD_LOGIC;
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  signal rdreq                     : std_logic;
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  signal q                         : STD_LOGIC_VECTOR(79 downto 0);
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  signal rdempty                   : STD_LOGIC;
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  signal search_sa_overload_cnt    : std_logic;
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  signal rdusedw                   : STD_LOGIC_VECTOR(6 downto 0);
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  signal search_entry_age_time_ena : std_logic;
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  signal clk_en                    : std_logic;
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  signal esoc_clk_en_gen_div       : integer;
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  signal Net_0                     : STD_LOGIC;
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  signal rden_b                    : STD_LOGIC := '1';
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  component esoc_search_engine_da
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    port(
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      clk_search           : in     std_logic;
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      reset                : in     std_logic;
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      search_eof           : in     std_logic;
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      search_key           : in     std_logic_vector(63 downto 0);
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      search_port_stalled  : in     std_logic_vector(esoc_port_count-1 downto 0);
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      search_result        : out    std_logic_vector(esoc_port_count-1 downto 0);
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      search_result_av     : out    std_logic;
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      search_sof           : in     std_logic;
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      search_table_address : out    STD_LOGIC_VECTOR(12 downto 0);
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      search_table_data    : out    STD_LOGIC_VECTOR(79 downto 0);
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      search_table_q       : in     STD_LOGIC_VECTOR(79 downto 0);
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      search_table_rden    : out    STD_LOGIC;
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      search_table_wren    : out    STD_LOGIC);
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  end component esoc_search_engine_da;
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121
  component esoc_search_engine_sa
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    port(
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      clk_search                : in     std_logic;
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      reset                     : in     std_logic;
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      search_aging_tick         : in     std_logic;
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      search_entry_age_time     : in     std_logic_vector(11 downto 0);
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      search_entry_age_time_ena : in     std_logic;
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      search_sa_drop_cnt        : out    std_logic;
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      search_sa_store_empty     : in     std_logic;
130
      search_sa_store_q         : in     std_logic_vector(79 downto 0);
131
      search_sa_store_rd        : out    std_logic;
132
      search_sa_store_words     : in     STD_LOGIC_VECTOR(6 downto 0);
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      search_table_address      : out    STD_LOGIC_VECTOR(12 downto 0);
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      search_table_data         : out    STD_LOGIC_VECTOR(79 downto 0);
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      search_table_q            : in     STD_LOGIC_VECTOR(79 downto 0);
136
      search_table_rden         : out    STD_LOGIC;
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      search_table_wren         : out    STD_LOGIC);
138
  end component esoc_search_engine_sa;
139
 
140
  component esoc_search_engine_control
141
    port(
142
      clk_control               : in     std_logic;
143
      clk_search                : in     std_logic;
144
      ctrl_address              : in     std_logic_vector(15 downto 0);
145
      ctrl_rd                   : in     std_logic;
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      ctrl_rddata               : out    std_logic_vector(31 downto 0);
147
      ctrl_wait                 : out    std_logic;
148
      ctrl_wr                   : in     std_logic;
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      ctrl_wrdata               : in     std_logic_vector(31 downto 0);
150
      reset                     : in     std_logic;
151
      search_entry_age_time     : out    std_logic_vector(11 downto 0);
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      search_entry_age_time_ena : out    std_logic;
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      search_sa_drop_cnt        : in     std_logic;
154
      search_sa_overload_cnt    : in     std_logic);
155
  end component esoc_search_engine_control;
156
 
157
  component esoc_ram_8kx80
158
    port(
159
      address_a : in     STD_LOGIC_VECTOR(12 downto 0);
160
      address_b : in     STD_LOGIC_VECTOR(12 downto 0);
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      data_a    : in     STD_LOGIC_VECTOR(79 downto 0);
162
      data_b    : in     STD_LOGIC_VECTOR(79 downto 0);
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      wren_a    : in     STD_LOGIC := '0';
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      wren_b    : in     STD_LOGIC := '0';
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      q_a       : out    STD_LOGIC_VECTOR(79 downto 0);
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      q_b       : out    STD_LOGIC_VECTOR(79 downto 0);
167
      clock     : in     STD_LOGIC := '1';
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      rden_a    : in     STD_LOGIC := '1';
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      rden_b    : in     STD_LOGIC := '1');
170
  end component esoc_ram_8kx80;
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172
  component esoc_search_engine_sa_store
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    port(
174
      clk_search             : in     std_logic;
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      reset                  : in     std_logic;
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      search_eof             : in     std_logic;
177
      search_key             : in     std_logic_vector(63 downto 0);
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      search_sa_overload_cnt : out    std_logic;
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      search_sa_store_d      : out    STD_LOGIC_VECTOR(79 downto 0);
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      search_sa_store_full   : in     STD_LOGIC;
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      search_sa_store_wr     : out    STD_LOGIC;
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      search_sof             : in     std_logic);
183
  end component esoc_search_engine_sa_store;
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  component esoc_fifo_128x80
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    port(
187
      aclr    : in     STD_LOGIC := '0';
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      data    : in     STD_LOGIC_VECTOR(79 downto 0);
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      rdclk   : in     STD_LOGIC;
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      rdreq   : in     STD_LOGIC;
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      wrclk   : in     STD_LOGIC;
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      wrreq   : in     STD_LOGIC;
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      q       : out    STD_LOGIC_VECTOR(79 downto 0);
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      rdempty : out    STD_LOGIC;
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      rdusedw : out    STD_LOGIC_VECTOR(6 downto 0);
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      wrfull  : out    STD_LOGIC;
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      wrusedw : out    STD_LOGIC_VECTOR(6 downto 0));
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  end component esoc_fifo_128x80;
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  component esoc_clk_en_gen
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    port(
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      clk     : in     std_logic;
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      clk_div : in     integer;
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      clk_en  : out    std_logic;
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      reset   : in     std_logic);
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  end component esoc_clk_en_gen;
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begin
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  --Destination MAC 
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  --Address Processing
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  --Source MAC Address 
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  --Processing and aging control
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  --MAC Address Table
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  --Search Engine Control
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  --SA, VID and 
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  --Source port buffer 
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  esoc_clk_en_gen_div <= clk_search_en_div_1s when esoc_mode = normal else clk_search_en_div_1s_sim;
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  u0: esoc_search_engine_da
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    port map(
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      clk_search           => clk_search,
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      reset                => reset,
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      search_eof           => search_eof,
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      search_key           => search_key,
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      search_port_stalled  => search_port_stalled,
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      search_result        => search_result,
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      search_result_av     => search_result_av,
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      search_sof           => search_sof,
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      search_table_address => address_a,
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      search_table_data    => data_a,
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      search_table_q       => q_a,
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      search_table_rden    => Net_0,
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      search_table_wren    => wren_a);
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  u1: esoc_search_engine_sa
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    port map(
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      clk_search                => clk_search,
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      reset                     => reset,
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      search_aging_tick         => clk_en,
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      search_entry_age_time     => search_entry_age_time,
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      search_entry_age_time_ena => search_entry_age_time_ena,
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      search_sa_drop_cnt        => search_sa_drop_cnt,
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      search_sa_store_empty     => rdempty,
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      search_sa_store_q         => q,
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      search_sa_store_rd        => rdreq,
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      search_sa_store_words     => rdusedw,
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      search_table_address      => address_b,
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      search_table_data         => data_b,
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      search_table_q            => q_b,
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      search_table_rden         => rden_b,
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      search_table_wren         => sa_wren);
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  u3: esoc_search_engine_control
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    port map(
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      clk_control               => clk_control,
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      clk_search                => clk_search,
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      ctrl_address              => ctrl_address,
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      ctrl_rd                   => ctrl_rd,
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      ctrl_rddata               => ctrl_rddata,
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      ctrl_wait                 => ctrl_wait,
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      ctrl_wr                   => ctrl_wr,
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      ctrl_wrdata               => ctrl_wrdata,
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      reset                     => reset,
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      search_entry_age_time     => search_entry_age_time,
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      search_entry_age_time_ena => search_entry_age_time_ena,
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      search_sa_drop_cnt        => search_sa_drop_cnt,
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      search_sa_overload_cnt    => search_sa_overload_cnt);
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  u2: esoc_ram_8kx80
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    port map(
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      address_a => address_a,
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      address_b => address_b,
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      data_a    => data_a,
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      data_b    => data_b,
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      wren_a    => wren_a,
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      wren_b    => sa_wren,
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      q_a       => q_a,
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      q_b       => q_b,
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      clock     => clk_search,
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      rden_a    => Net_0,
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      rden_b    => rden_b);
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283
  u5: esoc_search_engine_sa_store
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    port map(
285
      clk_search             => clk_search,
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      reset                  => reset,
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      search_eof             => search_eof,
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      search_key             => search_key,
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      search_sa_overload_cnt => search_sa_overload_cnt,
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      search_sa_store_d      => data,
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      search_sa_store_full   => wrfull,
292
      search_sa_store_wr     => wrreq,
293
      search_sof             => search_sof);
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295
  u6: esoc_fifo_128x80
296
    port map(
297
      aclr    => reset,
298
      data    => data,
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      rdclk   => clk_search,
300
      rdreq   => rdreq,
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      wrclk   => clk_search,
302
      wrreq   => wrreq,
303
      q       => q,
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      rdempty => rdempty,
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      rdusedw => rdusedw,
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      wrfull  => wrfull,
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      wrusedw => open);
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309
  u7: esoc_clk_en_gen
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    port map(
311
      clk     => clk_search,
312
      clk_div => esoc_clk_en_gen_div,
313
      clk_en  => clk_en,
314
      reset   => reset);
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316
end architecture esoc_search ; -- of esoc_search_engine
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