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---- ----
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---- Ethernet Switch on Configurable Logic IP Core ----
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---- ----
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---- This file is part of the ESoCL project ----
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---- http://www.opencores.org/cores/esoc/ ----
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---- ----
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---- Description: see design description ESoCL_dd_71022001.pdf ----
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---- ----
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
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---- and/or release bulleting ESoCL_rb_71022001.pdf ----
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---- ----
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---- Author(s): L.Maarsen ----
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---- Bert Maarsen, lmaarsen@opencores.org ----
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---- ----
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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--------------------------------------------------------------------------------
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-- Object : Entity work.esoc_search_engine_da
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-- Last modified : Mon Apr 14 12:50:04 2014.
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use work.package_hash10_24b.all;
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use work.package_esoc_configuration.all;
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entity esoc_search_engine_da is
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port(
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clk_search : in std_logic;
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reset : in std_logic;
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search_eof : in std_logic;
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search_key : in std_logic_vector(63 downto 0);
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search_port_stalled : in std_logic_vector(esoc_port_count-1 downto 0);
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search_result : out std_logic_vector(esoc_port_count-1 downto 0);
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search_result_av : out std_logic;
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search_sof : in std_logic;
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search_table_address : out STD_LOGIC_VECTOR(12 downto 0);
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search_table_data : out STD_LOGIC_VECTOR(79 downto 0);
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search_table_q : in STD_LOGIC_VECTOR(79 downto 0);
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search_table_rden : out STD_LOGIC;
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search_table_wren : out STD_LOGIC);
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end entity esoc_search_engine_da;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.esoc_search_engine_da.esoc_search_engine_da
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-- Last modified : Mon Apr 14 12:50:04 2014.
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--------------------------------------------------------------------------------
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architecture esoc_search_engine_da of esoc_search_engine_da is
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type search_states is (idle, wait_hash, compare);
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signal search_state: search_states;
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signal search_table_address_i: std_logic_vector(search_table_address'high downto 0);
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signal search_result_i: std_logic_vector(esoc_port_count-1 downto 0);
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signal search_port_stalled_sync : std_logic_vector(2*esoc_port_count-1 downto 0);
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signal search_table_coll_cnt: integer range esoc_search_engine_col_depth downto 0 ;
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signal search_hash_delay_cnt: integer range esoc_search_engine_hash_delay downto 0;
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signal search_key_i: std_logic_vector(59 downto 0);
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begin
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--=============================================================================================================
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-- Process : proces search requests for destination MAC address
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-- Description :
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--=============================================================================================================
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search_da: process(clk_search, reset)
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begin
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if reset = '1' then
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search_table_coll_cnt <= 0;
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search_hash_delay_cnt <= 0;
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search_key_i <= (others => '0');
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search_table_address_i <= (others => '0');
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search_table_rden <= '0';
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search_result_i <= (others => '0');
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search_result_av <= '0';
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search_port_stalled_sync <= (others => '0');
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elsif clk_search'event and clk_search = '1' then
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-- clear one-clock active signals
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search_result_av <= '0';
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search_table_rden <= '0';
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-- synchronise port stalled information with this clock
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search_port_stalled_sync(esoc_port_count-1 downto 0) <= search_port_stalled_sync(2*esoc_port_count-1 downto esoc_port_count);
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search_port_stalled_sync(2*esoc_port_count-1 downto esoc_port_count) <= search_port_stalled;
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-- process new search requests
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case search_state is
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when idle => -- wait for start of frame, first data is VID + DA, calculate hash pointer (additional delay may be required after synthesis, due to large XOR tree)
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if search_sof = '1' then
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-- send result (all ports) immediately if destination address is a BC or MC, if UC start search action.
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-- the BC/MC detection is part of the search engine and not part of port because you still need to learn the SA!
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if search_key(esoc_search_bus_mac+esoc_ethernet_uc_mc_bc) = '0'then
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search_key_i(esoc_search_entry_vlan+11 downto esoc_search_entry_vlan) <= search_key(esoc_search_bus_vlan+11 downto esoc_search_bus_vlan);
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search_key_i(esoc_search_entry_mac+47 downto esoc_search_entry_mac) <= search_key(esoc_search_bus_mac+47 downto esoc_search_bus_mac);
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search_table_address_i <= CALC_HASH10_24b(search_key(esoc_search_bus_mac+23 downto esoc_search_bus_mac)) & "000";
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search_table_rden <= '1';
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search_table_coll_cnt <= 0;
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-- use delay mechanism to give the hash function - large xor tree - time to provide stable result
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-- depends on target speed, use target timing analysis result to optimze this delay! At least one clock
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-- delay due to RAM latency
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search_hash_delay_cnt <= esoc_search_engine_hash_delay-1;
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search_state <= wait_hash;
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else
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search_result_av <= '1';
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search_result_i <= (others => '1');
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end if;
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end if;
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when wait_hash => -- hash result stable?
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if search_hash_delay_cnt = 0 then
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search_table_address_i <= std_logic_vector(to_unsigned(to_integer(unsigned(search_table_address_i))+1,search_table_address_i'length));
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search_state <= compare;
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else
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search_hash_delay_cnt <= search_hash_delay_cnt-1;
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end if;
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search_table_rden <= '1';
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when compare => -- there is a hit on DA and VID
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if search_table_q(esoc_search_entry_vlan+11 downto esoc_search_entry_vlan) = search_key_i(esoc_search_entry_vlan+11 downto esoc_search_entry_vlan) and
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search_table_q(esoc_search_entry_mac+47 downto esoc_search_entry_mac) = search_key_i(esoc_search_entry_mac+47 downto esoc_search_entry_mac) then
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-- entry valid, provide destination information else return broadcast as result
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if search_table_q(esoc_search_entry_valid) = '1' then
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search_result_av <= '1';
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search_result_i <= search_table_q(esoc_search_entry_destination+esoc_port_count-1 downto esoc_search_entry_destination);
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search_state <= idle;
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else
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search_result_av <= '1';
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search_result_i <= (others => '1');
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search_state <= idle;
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end if;
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-- there is no hit on DA and VID
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else
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-- End of collision buffer reached, no increment address for next entry else return result
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if search_table_coll_cnt < esoc_search_engine_col_depth then
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search_table_coll_cnt <= search_table_coll_cnt + 1;
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search_table_address_i <= std_logic_vector(to_unsigned(to_integer(unsigned(search_table_address_i))+1,search_table_address_i'length));
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search_table_rden <= '1';
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-- end of collission buffer, no hit, return broadcast as result
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else
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search_result_av <= '1';
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search_result_i <= (others => '1');
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search_state <= idle;
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end if;
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end if;
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when others => search_state <= idle;
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end case;
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end if;
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end process;
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search_table_wren <= '0';
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search_table_data <= (others => '0');
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search_table_address <= search_table_address_i;
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-- provide search result, but use port stall info to avoid use of data bus to stalled ports, waste of bus usage
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search_result <= search_result_i and not(search_port_stalled_sync(esoc_port_count-1 downto 0));
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end architecture esoc_search_engine_da ; -- of esoc_search_engine_da
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