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lmaarsen |
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---- ----
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---- Ethernet Switch on Configurable Logic IP Core ----
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---- ----
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---- This file is part of the ESoCL project ----
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---- http://www.opencores.org/cores/esoc/ ----
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---- ----
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---- Description: see design description ESoCL_dd_71022001.pdf ----
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---- ----
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---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
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---- and/or release bulleting ESoCL_rb_71022001.pdf ----
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---- ----
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---- Author(s): L.Maarsen ----
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---- Bert Maarsen, lmaarsen@opencores.org ----
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---- ----
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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-- Object : Entity work.esoc_search_engine_sa_store
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-- Last modified : Mon Apr 14 12:50:14 2014.
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library ieee, std, work;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use work.package_esoc_configuration.all;
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entity esoc_search_engine_sa_store is
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port(
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clk_search : in std_logic;
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reset : in std_logic;
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search_eof : in std_logic;
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search_key : in std_logic_vector(63 downto 0);
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search_sa_overload_cnt : out std_logic;
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search_sa_store_d : out STD_LOGIC_VECTOR(79 downto 0);
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search_sa_store_full : in STD_LOGIC;
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search_sa_store_wr : out STD_LOGIC;
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search_sof : in std_logic);
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end entity esoc_search_engine_sa_store;
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--------------------------------------------------------------------------------
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-- Object : Architecture work.esoc_search_engine_sa_store.esoc_search_engine_sa_store
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-- Last modified : Mon Apr 14 12:50:14 2014.
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--------------------------------------------------------------------------------
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architecture esoc_search_engine_sa_store of esoc_search_engine_sa_store is
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type store_sa_states is (idle, wait_sa, wait_full);
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signal store_sa_state: store_sa_states;
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begin
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--=============================================================================================================
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-- Process : proces store SA address for further processing
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-- Description :
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--=============================================================================================================
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store_sa: process(clk_search, reset)
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begin
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if reset = '1' then
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search_sa_store_wr <= '0';
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search_sa_store_d <= (others => '0');
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search_sa_overload_cnt <= '0';
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store_sa_state <= idle;
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elsif clk_search'event and clk_search = '1' then
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-- clear one-clock active signals
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search_sa_store_wr <= '0';
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search_sa_overload_cnt <= '0';
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-- define unused bits to avoid inferred latch warning during analysis & synthesis
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search_sa_store_d(esoc_search_entry_valid) <= '0';
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search_sa_store_d(esoc_search_entry_update) <= '0';
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search_sa_store_d(esoc_search_entry_unused2 downto esoc_search_entry_unused1) <= (others => '0');
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case store_sa_state is
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when idle => -- wait for start of frame, first data is VID + DA, skip DA, store VID, wait for SA and port number ... report when storage is full!
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if search_sof = '1' then
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if search_sa_store_full = '0' then
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search_sa_store_d(esoc_search_entry_vlan+11 downto esoc_search_entry_vlan) <= search_key(esoc_search_bus_vlan+11 downto esoc_search_bus_vlan);
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store_sa_state <= wait_sa;
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else
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search_sa_overload_cnt <= '1';
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store_sa_state <= wait_full;
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end if;
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end if;
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when wait_sa => -- get Source Port + SA and calculate hash pointer (additional delay may be required after synthesis, due to large XOR tree)
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search_sa_store_d(esoc_search_entry_destination+15 downto esoc_search_entry_destination) <= search_key(esoc_search_bus_sport+15 downto esoc_search_bus_sport);
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search_sa_store_d(esoc_search_entry_mac+47 downto esoc_search_entry_mac) <= search_key(esoc_search_bus_mac+47 downto esoc_search_bus_mac);
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search_sa_store_wr <= '1';
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store_sa_state <= idle;
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when wait_full => if search_sa_store_full = '0' then
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store_sa_state <= idle;
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end if;
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when others => store_sa_state <= idle;
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end case;
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end if;
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end process;
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end architecture esoc_search_engine_sa_store ; -- of esoc_search_engine_sa_store
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