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--

-- This VHDL file was generated by EASE/HDL 7.4 Revision 4 from HDL Works B.V.

--

-- Ease library  : work

-- HDL library   : work

-- Host name     : S212065

-- User name     : df768

-- Time stamp    : Tue Aug 19 08:05:18 2014

--

-- Designed by   : L.Maarsen

-- Company       : LogiXA

-- Project info  : eSoC

--

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-- Object        : Entity work.esoc_search_engine_sa_store

-- Last modified : Tue Aug 19 08:05:17 2014.

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library ieee, std, work;

use ieee.std_logic_1164.all;

use std.textio.all;

use ieee.numeric_std.all;

use work.package_esoc_configuration.all;

entity esoc_search_engine_sa_store is

  port(

    clk_search             : in     std_logic;

    reset                  : in     std_logic;

    search_eof             : in     std_logic;

    search_key             : in     std_logic_vector(63 downto 0);

    search_sa_overload_cnt : out    std_logic;

    search_sa_store_d      : out    STD_LOGIC_VECTOR(79 downto 0);

    search_sa_store_full   : in     STD_LOGIC;

    search_sa_store_wr     : out    STD_LOGIC;

    search_sof             : in     std_logic);

end entity esoc_search_engine_sa_store;

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-- Object        : Architecture work.esoc_search_engine_sa_store.esoc_search_engine_sa_store

-- Last modified : Tue Aug 19 08:05:17 2014.

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architecture esoc_search_engine_sa_store of esoc_search_engine_sa_store is

type   store_sa_states is (idle, wait_sa, wait_full);

signal store_sa_state: store_sa_states;

begin

--=============================================================================================================

-- Process                : proces store SA address for further processing

-- Description  : 

--=============================================================================================================    

store_sa:   process(clk_search, reset)

            begin

              if reset = '1' then

                search_sa_store_wr        <= '0';

                search_sa_store_d         <= (others => '0');

                search_sa_overload_cnt    <= '0';

                store_sa_state            <= idle;

              elsif clk_search'event and clk_search = '1' then

                -- clear one-clock active signals

                search_sa_store_wr <= '0';

                search_sa_overload_cnt <= '0';

                -- define unused bits to avoid inferred latch warning during analysis & synthesis

                search_sa_store_d(esoc_search_entry_valid) <= '0';

                search_sa_store_d(esoc_search_entry_aging) <= '0';

                search_sa_store_d(esoc_search_entry_unused2 downto esoc_search_entry_unused1) <= (others => '0');

                case store_sa_state is

                  when idle       =>  -- wait for start of frame, first data is VID + DA, skip DA, store VID, wait for SA and port number ... report when storage is full!

                                      if search_sof = '1' then

                                        if search_sa_store_full = '0' then

                                          search_sa_store_d(esoc_search_entry_vlan+11 downto esoc_search_entry_vlan) <= search_key(esoc_search_bus_vlan+11 downto esoc_search_bus_vlan);

                                          store_sa_state <= wait_sa;

                                        else

                                          search_sa_overload_cnt <= '1';

                                          store_sa_state <= wait_full;

                                        end if;

                                      end if;

                  when wait_sa    =>  -- get Source Port + SA and calculate hash pointer (additional delay may be required after synthesis, due to large XOR tree)  

                                      search_sa_store_d(esoc_search_entry_destination+15 downto esoc_search_entry_destination) <= search_key(esoc_search_bus_sport+15 downto esoc_search_bus_sport);

                                      search_sa_store_d(esoc_search_entry_mac+47 downto esoc_search_entry_mac)                 <= search_key(esoc_search_bus_mac+47 downto esoc_search_bus_mac);

                                      search_sa_store_wr <= '1';

                                      store_sa_state <= idle;

                  when wait_full  =>  if search_sa_store_full = '0' then

                                        store_sa_state <= idle;

                                      end if;

                  when others     =>  store_sa_state <= idle;

                end case;

              end if;

            end process;

end architecture esoc_search_engine_sa_store ; -- of esoc_search_engine_sa_store