OpenCores
URL https://opencores.org/ocsvn/etherlab/etherlab/trunk

Subversion Repositories etherlab

[/] [etherlab/] [trunk/] [vhdl/] [PCK_CRC32_D4.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 idiolatrie
--------------------------------------------------------------------------------
2
-- Copyright (C) 1999-2008 Easics NV.
3
-- This source file may be used and distributed without restriction
4
-- provided that this copyright statement is not removed from the file
5
-- and that any derivative work contains the original copyright notice
6
-- and the associated disclaimer.
7
--
8
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
9
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
10
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
11
--
12
-- Purpose : synthesizable CRC function
13
--   * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
14
--   * data width: 4
15
--
16
-- Info : tools@easics.be
17
--        http://www.easics.com
18
--------------------------------------------------------------------------------
19
library ieee;
20
use ieee.std_logic_1164.all;
21
 
22
package PCK_CRC32_D4 is
23
  -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
24
  -- data width: 4
25
  -- convention: the first serial bit is D[3]
26
  function nextCRC32_D4
27
    (Data: std_logic_vector(3 downto 0);
28
     crc:  std_logic_vector(31 downto 0))
29
    return std_logic_vector;
30
end PCK_CRC32_D4;
31
 
32
 
33
package body PCK_CRC32_D4 is
34
 
35
  -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
36
  -- data width: 4
37
  -- convention: the first serial bit is D[3]
38
  function nextCRC32_D4
39
    (Data: std_logic_vector(3 downto 0);
40
     crc:  std_logic_vector(31 downto 0))
41
    return std_logic_vector is
42
 
43
    variable d:      std_logic_vector(3 downto 0);
44
    variable c:      std_logic_vector(31 downto 0);
45
    variable newcrc: std_logic_vector(31 downto 0);
46
 
47
  begin
48
    d := Data;
49
    c := crc;
50
 
51
    newcrc(0) := d(0) xor c(28);
52
    newcrc(1) := d(1) xor d(0) xor c(28) xor c(29);
53
    newcrc(2) := d(2) xor d(1) xor d(0) xor c(28) xor c(29) xor c(30);
54
    newcrc(3) := d(3) xor d(2) xor d(1) xor c(29) xor c(30) xor c(31);
55
    newcrc(4) := d(3) xor d(2) xor d(0) xor c(0) xor c(28) xor c(30) xor c(31);
56
    newcrc(5) := d(3) xor d(1) xor d(0) xor c(1) xor c(28) xor c(29) xor c(31);
57
    newcrc(6) := d(2) xor d(1) xor c(2) xor c(29) xor c(30);
58
    newcrc(7) := d(3) xor d(2) xor d(0) xor c(3) xor c(28) xor c(30) xor c(31);
59
    newcrc(8) := d(3) xor d(1) xor d(0) xor c(4) xor c(28) xor c(29) xor c(31);
60
    newcrc(9) := d(2) xor d(1) xor c(5) xor c(29) xor c(30);
61
    newcrc(10) := d(3) xor d(2) xor d(0) xor c(6) xor c(28) xor c(30) xor c(31);
62
    newcrc(11) := d(3) xor d(1) xor d(0) xor c(7) xor c(28) xor c(29) xor c(31);
63
    newcrc(12) := d(2) xor d(1) xor d(0) xor c(8) xor c(28) xor c(29) xor c(30);
64
    newcrc(13) := d(3) xor d(2) xor d(1) xor c(9) xor c(29) xor c(30) xor c(31);
65
    newcrc(14) := d(3) xor d(2) xor c(10) xor c(30) xor c(31);
66
    newcrc(15) := d(3) xor c(11) xor c(31);
67
    newcrc(16) := d(0) xor c(12) xor c(28);
68
    newcrc(17) := d(1) xor c(13) xor c(29);
69
    newcrc(18) := d(2) xor c(14) xor c(30);
70
    newcrc(19) := d(3) xor c(15) xor c(31);
71
    newcrc(20) := c(16);
72
    newcrc(21) := c(17);
73
    newcrc(22) := d(0) xor c(18) xor c(28);
74
    newcrc(23) := d(1) xor d(0) xor c(19) xor c(28) xor c(29);
75
    newcrc(24) := d(2) xor d(1) xor c(20) xor c(29) xor c(30);
76
    newcrc(25) := d(3) xor d(2) xor c(21) xor c(30) xor c(31);
77
    newcrc(26) := d(3) xor d(0) xor c(22) xor c(28) xor c(31);
78
    newcrc(27) := d(1) xor c(23) xor c(29);
79
    newcrc(28) := d(2) xor c(24) xor c(30);
80
    newcrc(29) := d(3) xor c(25) xor c(31);
81
    newcrc(30) := c(26);
82
    newcrc(31) := c(27);
83
    return newcrc;
84
  end nextCRC32_D4;
85
 
86
end PCK_CRC32_D4;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.