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[/] [ethernet_tri_mode/] [tags/] [release-1-0/] [rtl/] [verilog/] [MAC_tx/] [MAC_tx_Ctrl.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_tx_ctrl.v                                               ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.3  2005/12/16 06:44:17  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2  2005/12/13 12:15:38  Administrator
// no message
//
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//                                           
 
module MAC_tx_ctrl (
Reset               ,
Clk                 ,
//CRC_gen Interface  
CRC_init            ,
Frame_data          ,
Data_en             ,
CRC_rd              ,
CRC_end             ,
CRC_out             ,
//Ramdon_gen interfac
Random_init         ,
RetryCnt            ,
Random_time_meet    ,
//flow control      
pause_apply         ,
pause_quanta_sub    ,
xoff_gen            ,
xoff_gen_complete   ,
xon_gen             ,
xon_gen_complete    ,
//MAC_tx_FF          
Fifo_data           ,
Fifo_rd             ,
Fifo_eop            ,
Fifo_da             ,
Fifo_rd_finish      ,
Fifo_rd_retry       ,
Fifo_ra             ,
Fifo_data_err_empty ,
Fifo_data_err_full  ,
//RMII               
TxD                 ,
TxEn                ,
CRS                 ,
//MAC_tx_addr_add   
MAC_tx_addr_rd      ,
MAC_tx_addr_data    ,
MAC_tx_addr_init    ,
//RMON               
Tx_pkt_type_rmon    ,
Tx_pkt_length_rmon  ,
Tx_apply_rmon       ,
Tx_pkt_err_type_rmon,
//CPU  
pause_frame_send_en ,
pause_quanta_set    ,
MAC_tx_add_en       ,
FullDuplex          ,
MaxRetry            ,
IFGset
);
 
input           Reset               ;
input           Clk                 ;
                //CRC_gen Interface 
output          CRC_init            ;
output  [7:0]   Frame_data          ;
output          Data_en             ;
output          CRC_rd              ;
input           CRC_end             ;
input   [7:0]   CRC_out             ;
                //Ramdon_gen interface
output          Random_init         ;
output  [3:0]   RetryCnt            ;
input           Random_time_meet    ;//levle hight indicate random time passed away
                //flow control
input           pause_apply         ;
output          pause_quanta_sub    ;
input           xoff_gen            ;
output          xoff_gen_complete   ;
input           xon_gen             ;
output          xon_gen_complete    ;
                //MAC_rx_FF
input   [7:0]   Fifo_data           ;
output          Fifo_rd             ;
input           Fifo_eop            ;
input           Fifo_da             ;
output          Fifo_rd_finish      ;
output          Fifo_rd_retry       ;
input           Fifo_ra             ;
input           Fifo_data_err_empty ;
input           Fifo_data_err_full  ;
                //RMII
output  [7:0]   TxD                 ;
output          TxEn                ;
input           CRS                 ;
                //MAC_tx_addr_add
output          MAC_tx_addr_init    ;
output          MAC_tx_addr_rd      ;
input   [7:0]   MAC_tx_addr_data    ;
                //RMON
output  [2:0]   Tx_pkt_type_rmon    ;
output  [15:0]  Tx_pkt_length_rmon  ;
output          Tx_apply_rmon       ;
output  [2:0]   Tx_pkt_err_type_rmon;
                //CPU
input           pause_frame_send_en ;
input   [15:0]  pause_quanta_set    ;
input           MAC_tx_add_en       ;
input           FullDuplex          ;
input   [3:0]   MaxRetry            ;
input   [5:0]   IFGset              ;
//******************************************************************************        
//internal signals                                                              
//******************************************************************************   
parameter       StateIdle           =4'd00;
parameter       StatePreamble       =4'd01;
parameter       StateSFD            =4'd02;
parameter       StateData           =4'd03;
parameter       StatePause          =4'd04;
parameter       StatePAD            =4'd05;
parameter       StateFCS            =4'd06;
parameter       StateIFG            =4'd07;
parameter       StateJam            =4'd08;
parameter       StateBackOff        =4'd09;
parameter       StateJamDrop        =4'd10;
parameter       StateFFEmptyDrop    =4'd11;
parameter       StateSwitchNext     =4'd12;
parameter       StateDefer          =4'd13;
parameter       StateSendPauseFrame =4'd14;
 
reg [3:0]       Current_state   /*synthesis syn_keep=1 */;
reg [3:0]       Next_state;
reg [5:0]       IFG_counter;
reg [4:0]       Preamble_counter;//
reg [7:0]       TxD_tmp             ;
reg             TxEn_tmp            ;
reg [15:0]      Tx_pkt_length_rmon  ;
reg             Tx_apply_rmon       ;
reg [2:0]       Tx_pkt_err_type_rmon;
reg [3:0]       RetryCnt            ;
reg             Random_init         ;
reg             Fifo_rd_finish      ;
reg             Fifo_rd_retry       ;
reg [7:0]       TxD                 ;
reg             TxEn                ;
reg             CRC_init            ;
reg             Data_en             ;
reg             CRC_rd              ;
reg             Fifo_rd             ;
reg             MAC_tx_addr_rd      ;
reg             MAC_header_slot     ;
reg             MAC_header_slot_tmp ;
reg [2:0]       Tx_pkt_type_rmon    ;
wire            Collision           ;
reg             MAC_tx_addr_init    ;
reg             Src_MAC_ptr         ;
reg [7:0]       IPLengthCounter     ;//for pad append
reg [1:0]       PADCounter          ;
reg [7:0]       JamCounter          ;
reg             PktDrpEvenPtr       ;
reg [7:0]       pause_counter       ;
reg             pause_quanta_sub    ;
reg             pause_frame_send_en_dl1 ;
reg [15:0]      pause_quanta_set_dl1    ;
reg [4:0]       send_pause_frame_counter    ;
reg             xoff_gen_complete   ;
reg             xon_gen_complete    ;
//******************************************************************************    
//boundery signal processing                                                             
//****************************************************************************** 
always @(posedge Clk or posedge Reset)
    if (Reset)
        begin
        pause_frame_send_en_dl1         <=0;
        pause_quanta_set_dl1            <=0;
        end
    else
        begin
        pause_frame_send_en_dl1         <=pause_frame_send_en   ;
        pause_quanta_set_dl1            <=pause_quanta_set      ;
        end
//******************************************************************************    
//state machine                                                             
//****************************************************************************** 
assign Collision=TxEn&CRS;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        send_pause_frame_counter    <=0;
    else if(Current_state!=StateSendPauseFrame)
        send_pause_frame_counter    <=0;
    else
        send_pause_frame_counter    <=send_pause_frame_counter +1;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        pause_counter   <=0;
    else if (Current_state!=StatePause)
        pause_counter   <=0;
    else
        pause_counter   <=pause_counter+1;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        IPLengthCounter     <=0;
    else if (Current_state==StateSwitchNext)
        IPLengthCounter     <=0;
    else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StatePAD))
        IPLengthCounter     <=IPLengthCounter+1;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        PADCounter      <=0;
    else if (Current_state!=StatePAD)
        PADCounter      <=0;
    else
        PADCounter      <=PADCounter+1;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        Current_state       <=StateDefer;
    else
        Current_state       <=Next_state;
 
always @ (*)
        case (Current_state)
            StateDefer:
                if ((FullDuplex)||(!FullDuplex&&!CRS))
                    Next_state=StateIFG;
                else
                    Next_state=Current_state;
            StateIFG:
                if (!FullDuplex&&CRS)
                    Next_state=StateDefer;
                else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//ȥ��һЩ�����ʱ��
                    Next_state=StateIdle;
                else
                    Next_state=Current_state;
            StateIdle:
                if (!FullDuplex&&CRS)
                    Next_state=StateDefer;
                else if (pause_apply)
                    Next_state=StatePause;
                else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)))
                    Next_state=StatePreamble;
                else
                    Next_state=Current_state;
            StatePause:
                if (pause_counter==512/8)
                    Next_state=StateDefer;
                else
                    Next_state=Current_state;
            StatePreamble:
                if (!FullDuplex&&Collision)
                    Next_state=StateJam;
                else if ((FullDuplex&&Preamble_counter==7)||(!FullDuplex&&!Collision&&Preamble_counter==7))
                    Next_state=StateSFD;
                else
                    Next_state=Current_state;
            StateSFD:
                if (!FullDuplex&&Collision)
                    Next_state=StateJam;
                else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
                    Next_state=StateSendPauseFrame;
                else
                    Next_state=StateData;
            StateSendPauseFrame:
                if (send_pause_frame_counter==19)
                    Next_state=StatePAD;
                else
                    Next_state=Current_state;
            StateData:
                if (!FullDuplex&&Collision)
                    Next_state=StateJam;
                else if (Fifo_data_err_empty)
                    Next_state=StateFFEmptyDrop;
                else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0
                    Next_state=StateFCS;
                else if (Fifo_eop)
                    Next_state=StatePAD;
                else
                    Next_state=StateData;
            StatePAD:
                if (!FullDuplex&&Collision)
                    Next_state=StateJam;
                else if (IPLengthCounter>=59)
                    Next_state=StateFCS;
                else
                    Next_state=Current_state;
            StateJam:
                if (RetryCnt<=MaxRetry&&JamCounter==16)
                    Next_state=StateBackOff;
                else if (RetryCnt>MaxRetry)
                    Next_state=StateJamDrop;
                else
                    Next_state=Current_state;
            StateBackOff:
                if (Random_time_meet)
                    Next_state  =StateDefer;
                else
                    Next_state  =Current_state;
            StateFCS:
                if (!FullDuplex&&Collision)
                    Next_state  =StateJam;
                else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
                    Next_state  =StateDefer;
                else if (CRC_end)
                    Next_state  =StateSwitchNext;
                else
                    Next_state  =Current_state;
            StateFFEmptyDrop:
                if (Fifo_eop)
                    Next_state  =StateSwitchNext;
                else
                    Next_state  =Current_state;
            StateJamDrop:
                if (Fifo_eop)
                    Next_state  =StateSwitchNext;
                else
                    Next_state  =Current_state;
            StateSwitchNext:
                    Next_state  =StateDefer;
            default:
                Next_state  =StateDefer;
        endcase
 
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        JamCounter      <=0;
    else if (Current_state!=StateJam)
        JamCounter      <=0;
    else if (Current_state==StateJam)
        JamCounter      <=JamCounter+1;
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        RetryCnt        <=0;
    else if (Current_state==StateSwitchNext)
        RetryCnt        <=0;
    else if (Current_state==StateJam&&Next_state==StateBackOff)
        RetryCnt        <=RetryCnt + 1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        IFG_counter     <=0;
    else if (Current_state!=StateIFG)
        IFG_counter     <=0;
    else
        IFG_counter     <=IFG_counter + 1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Preamble_counter    <=0;
    else if (Current_state!=StatePreamble)
        Preamble_counter    <=0;
    else
        Preamble_counter    <=Preamble_counter+ 1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        PktDrpEvenPtr       <=0;
    else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop)
        PktDrpEvenPtr       <=~PktDrpEvenPtr;
//******************************************************************************    
//generate output signals                                                           
//****************************************************************************** 
//CRC related
always @(Current_state)
    if (Current_state==StateSFD)
        CRC_init    =1;
    else
        CRC_init    =0;
 
assign Frame_data=TxD_tmp;
 
always @(Current_state)
    if (Current_state==StateData||Current_state==StatePAD)
        Data_en     =1;
    else
        Data_en     =0;
 
always @(Current_state)
    if (Current_state==StateFCS)
        CRC_rd      =1;
    else
        CRC_rd      =0;
 
//Ramdon_gen interface
always @(Current_state or Next_state)
    if (Current_state==StateJam&&Next_state==StateBackOff)
        Random_init =1;
    else
        Random_init =0;
 
//MAC_rx_FF
//data have one cycle delay after fifo read signals  
always @ (*)
    if (Current_state==StateData ||
        Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen))  ||
        Current_state==StateJamDrop&&PktDrpEvenPtr||
        Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
        Fifo_rd     =1;
    else
        Fifo_rd     =0;
 
always @ (Current_state)
    if (Current_state==StateSwitchNext)
        Fifo_rd_finish  =1;
    else
        Fifo_rd_finish  =0;
 
always @ (Current_state)
    if (Current_state==StateJam)
        Fifo_rd_retry   =1;
    else
        Fifo_rd_retry   =0;
//RMII
always @(Current_state)
    if (Current_state==StatePreamble||Current_state==StateSFD||
        Current_state==StateData||Current_state==StateSendPauseFrame||
        Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam)
        TxEn_tmp    =1;
    else
        TxEn_tmp    =0;
 
//gen txd data      
always @(*)
    case (Current_state)
        StatePreamble:
            TxD_tmp =8'h55;
        StateSFD:
            TxD_tmp =8'hd5;
        StateData:
            if (Src_MAC_ptr&&MAC_tx_add_en)
                TxD_tmp =MAC_tx_addr_data;
            else
                TxD_tmp =Fifo_data;
        StateSendPauseFrame:
            if (Src_MAC_ptr)
                TxD_tmp =MAC_tx_addr_data;
            else
                case (send_pause_frame_counter)
                    5'd0:   TxD_tmp =8'h01;
                    5'd1:   TxD_tmp =8'h80;
                    5'd2:   TxD_tmp =8'hc2;
                    5'd3:   TxD_tmp =8'h00;
                    5'd4:   TxD_tmp =8'h00;
                    5'd5:   TxD_tmp =8'h01;
                    5'd12:  TxD_tmp =8'h88;//type
                    5'd13:  TxD_tmp =8'h08;//
                    5'd14:  TxD_tmp =8'h00;//opcode
                    5'd15:  TxD_tmp =8'h01;
                    5'd16:  TxD_tmp =pause_quanta_set_dl1[15:8];
                    5'd17:  TxD_tmp =pause_quanta_set_dl1[7:0];
                    default:TxD_tmp =0;
                endcase
 
        StatePAD:
                TxD_tmp =8'h00;
        StateJam:
                TxD_tmp =8'h01; //jam sequence
        StateFCS:
            TxD_tmp =CRC_out;
        default:
            TxD_tmp =2'b0;
    endcase
always @ (posedge Clk or posedge Reset)
    if (Reset)
        begin
        TxD     <=0;
        TxEn    <=0;
        end
    else
        begin
        TxD     <=TxD_tmp;
        TxEn    <=TxEn_tmp;
        end
//RMON
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_pkt_length_rmon      <=0;
    else if (Current_state==StateSFD)
        Tx_pkt_length_rmon      <=0;
    else if (Current_state==StateData)
        Tx_pkt_length_rmon      <=Tx_pkt_length_rmon+1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_apply_rmon       <=0;
    else if ((Fifo_eop&&Current_state==StateJamDrop)||
             (Fifo_eop&&Current_state==StateFFEmptyDrop)||
             CRC_end)
        Tx_apply_rmon       <=1;
    else
        Tx_apply_rmon       <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_pkt_err_type_rmon    <=0;
    else if(Fifo_eop&&Current_state==StateJamDrop)
        Tx_pkt_err_type_rmon    <=3'b001;//
    else if(Fifo_eop&&Current_state==StateFFEmptyDrop)
        Tx_pkt_err_type_rmon    <=3'b010;//underflow
    else if(Fifo_eop&&Fifo_data_err_full)
        Tx_pkt_err_type_rmon    <=3'b011;//overflow
    else if(CRC_end)
        Tx_pkt_err_type_rmon    <=3'b100;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        MAC_header_slot_tmp <=0;
    else if(Current_state==StateSFD&&Next_state==StateData)
        MAC_header_slot_tmp <=0;
    else
        MAC_header_slot_tmp <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        MAC_header_slot     <=0;
    else
        MAC_header_slot     <=MAC_header_slot_tmp;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Tx_pkt_type_rmon    <=0;
    else if (Current_state==StateSendPauseFrame)
        Tx_pkt_type_rmon    <=3'b100;
    else if(MAC_header_slot)
        Tx_pkt_type_rmon    <={1'b0,TxD_tmp};
 
 
always @(Tx_pkt_length_rmon)
    if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11)
        Src_MAC_ptr         =1;
    else
        Src_MAC_ptr         =0;
 
//MAC_tx_addr_add  
always @ (posedge Clk or posedge Reset)
    if (Reset)
        MAC_tx_addr_rd  <=0;
    else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame))
        MAC_tx_addr_rd  <=1;
    else
        MAC_tx_addr_rd  <=0;
 
always @ (Tx_pkt_length_rmon or Fifo_rd)
    if ((Tx_pkt_length_rmon==3)&&Fifo_rd)
        MAC_tx_addr_init=1;
    else
        MAC_tx_addr_init=0;
 
//flow control
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_sub    <=0;
    else if(pause_counter==512/8)
        pause_quanta_sub    <=1;
    else
        pause_quanta_sub    <=0;
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        xoff_gen_complete   <=0;
    else if(Current_state==StateDefer&&xoff_gen)
        xoff_gen_complete   <=1;
    else
        xoff_gen_complete   <=0;
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        xon_gen_complete    <=0;
    else if(Current_state==StateDefer&&xon_gen)
        xon_gen_complete    <=1;
    else
        xon_gen_complete    <=0;
 
endmodule

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_tx_ctrl.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9	7	maverickis	`//// - Jon Gao (gaojon@yahoo.com) ////`
10	5	maverickis	`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41	6	maverickis	`// $Log: not supported by cvs2svn $`
42	7	maverickis	`// Revision 1.3 2005/12/16 06:44:17 Administrator`
43			`// replaced tab with space.`
44			`// passed 9.6k length frame test.`
45	6	maverickis	`//`
46	7	maverickis	`// Revision 1.2 2005/12/13 12:15:38 Administrator`
47			`// no message`
48			`//`
49	6	maverickis	`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
50			`// no message`
51			`//`
52	5	maverickis
53			`module MAC_tx_ctrl (`
54	7	maverickis	`Reset ,`
55			`Clk ,`
56	5	maverickis	`//CRC_gen Interface`
57	7	maverickis	`CRC_init ,`
58			`Frame_data ,`
59			`Data_en ,`
60			`CRC_rd ,`
61			`CRC_end ,`
62			`CRC_out ,`
63	5	maverickis	`//Ramdon_gen interfac`
64	7	maverickis	`Random_init ,`
65			`RetryCnt ,`
66			`Random_time_meet ,`
67	5	maverickis	`//flow control`
68	7	maverickis	`pause_apply ,`
69			`pause_quanta_sub ,`
70			`xoff_gen ,`
71			`xoff_gen_complete ,`
72			`xon_gen ,`
73			`xon_gen_complete ,`
74	5	maverickis	`//MAC_tx_FF`
75	7	maverickis	`Fifo_data ,`
76			`Fifo_rd ,`
77			`Fifo_eop ,`
78			`Fifo_da ,`
79			`Fifo_rd_finish ,`
80			`Fifo_rd_retry ,`
81			`Fifo_ra ,`
82			`Fifo_data_err_empty ,`
83			`Fifo_data_err_full ,`
84	5	maverickis	`//RMII`
85	7	maverickis	`TxD ,`
86			`TxEn ,`
87			`CRS ,`
88	5	maverickis	`//MAC_tx_addr_add`
89	7	maverickis	`MAC_tx_addr_rd ,`
90			`MAC_tx_addr_data ,`
91	5	maverickis	`MAC_tx_addr_init ,`
92			`//RMON`
93	7	maverickis	`Tx_pkt_type_rmon ,`
94			`Tx_pkt_length_rmon ,`
95			`Tx_apply_rmon ,`
96	5	maverickis	`Tx_pkt_err_type_rmon,`
97			`//CPU`
98	7	maverickis	`pause_frame_send_en ,`
99			`pause_quanta_set ,`
100			`MAC_tx_add_en ,`
101			`FullDuplex ,`
102			`MaxRetry ,`
103			`IFGset`
104	5	maverickis	`);`
105
106	7	maverickis	`input Reset ;`
107			`input Clk ;`
108			`//CRC_gen Interface`
109			`output CRC_init ;`
110			`output [7:0] Frame_data ;`
111			`output Data_en ;`
112			`output CRC_rd ;`
113			`input CRC_end ;`
114			`input [7:0] CRC_out ;`
115			`//Ramdon_gen interface`
116			`output Random_init ;`
117			`output [3:0] RetryCnt ;`
118			`input Random_time_meet ;//levle hight indicate random time passed away`
119			`//flow control`
120			`input pause_apply ;`
121			`output pause_quanta_sub ;`
122			`input xoff_gen ;`
123			`output xoff_gen_complete ;`
124			`input xon_gen ;`
125			`output xon_gen_complete ;`
126			`//MAC_rx_FF`
127			`input [7:0] Fifo_data ;`
128			`output Fifo_rd ;`
129			`input Fifo_eop ;`
130			`input Fifo_da ;`
131			`output Fifo_rd_finish ;`
132			`output Fifo_rd_retry ;`
133			`input Fifo_ra ;`
134			`input Fifo_data_err_empty ;`
135			`input Fifo_data_err_full ;`
136			`//RMII`
137			`output [7:0] TxD ;`
138			`output TxEn ;`
139			`input CRS ;`
140			`//MAC_tx_addr_add`
141			`output MAC_tx_addr_init ;`
142			`output MAC_tx_addr_rd ;`
143			`input [7:0] MAC_tx_addr_data ;`
144			`//RMON`
145			`output [2:0] Tx_pkt_type_rmon ;`
146			`output [15:0] Tx_pkt_length_rmon ;`
147			`output Tx_apply_rmon ;`
148			`output [2:0] Tx_pkt_err_type_rmon;`
149			`//CPU`
150			`input pause_frame_send_en ;`
151			`input [15:0] pause_quanta_set ;`
152			`input MAC_tx_add_en ;`
153			`input FullDuplex ;`
154			`input [3:0] MaxRetry ;`
155			`input [5:0] IFGset ;`
156			`//******************************************************************************`
157	5	maverickis	`//internal signals`
158			`//******************************************************************************`
159	7	maverickis	`parameter StateIdle =4'd00;`
160			`parameter StatePreamble =4'd01;`
161			`parameter StateSFD =4'd02;`
162			`parameter StateData =4'd03;`
163			`parameter StatePause =4'd04;`
164			`parameter StatePAD =4'd05;`
165			`parameter StateFCS =4'd06;`
166			`parameter StateIFG =4'd07;`
167			`parameter StateJam =4'd08;`
168			`parameter StateBackOff =4'd09;`
169			`parameter StateJamDrop =4'd10;`
170			`parameter StateFFEmptyDrop =4'd11;`
171			`parameter StateSwitchNext =4'd12;`
172			`parameter StateDefer =4'd13;`
173			`parameter StateSendPauseFrame =4'd14;`
174	5	maverickis
175	7	maverickis	`reg [3:0] Current_state /synthesis syn_keep=1 /;`
176			`reg [3:0] Next_state;`
177			`reg [5:0] IFG_counter;`
178			`reg [4:0] Preamble_counter;//`
179			`reg [7:0] TxD_tmp ;`
180			`reg TxEn_tmp ;`
181			`reg [15:0] Tx_pkt_length_rmon ;`
182			`reg Tx_apply_rmon ;`
183			`reg [2:0] Tx_pkt_err_type_rmon;`
184			`reg [3:0] RetryCnt ;`
185			`reg Random_init ;`
186			`reg Fifo_rd_finish ;`
187			`reg Fifo_rd_retry ;`
188			`reg [7:0] TxD ;`
189			`reg TxEn ;`
190			`reg CRC_init ;`
191			`reg Data_en ;`
192			`reg CRC_rd ;`
193			`reg Fifo_rd ;`
194			`reg MAC_tx_addr_rd ;`
195			`reg MAC_header_slot ;`
196			`reg MAC_header_slot_tmp ;`
197			`reg [2:0] Tx_pkt_type_rmon ;`
198			`wire Collision ;`
199			`reg MAC_tx_addr_init ;`
200			`reg Src_MAC_ptr ;`
201			`reg [7:0] IPLengthCounter ;//for pad append`
202			`reg [1:0] PADCounter ;`
203			`reg [7:0] JamCounter ;`
204			`reg PktDrpEvenPtr ;`
205			`reg [7:0] pause_counter ;`
206			`reg pause_quanta_sub ;`
207			`reg pause_frame_send_en_dl1 ;`
208			`reg [15:0] pause_quanta_set_dl1 ;`
209			`reg [4:0] send_pause_frame_counter ;`
210			`reg xoff_gen_complete ;`
211			`reg xon_gen_complete ;`
212	5	maverickis	`//******************************************************************************`
213			`//boundery signal processing`
214			`//******************************************************************************`
215			`always @(posedge Clk or posedge Reset)`
216	7	maverickis	`if (Reset)`
217			`begin`
218			`pause_frame_send_en_dl1 <=0;`
219			`pause_quanta_set_dl1 <=0;`
220			`end`
221			`else`
222			`begin`
223			`pause_frame_send_en_dl1 <=pause_frame_send_en ;`
224			`pause_quanta_set_dl1 <=pause_quanta_set ;`
225			`end`
226	5	maverickis	`//******************************************************************************`
227			`//state machine`
228			`//******************************************************************************`
229			`assign Collision=TxEn&CRS;`
230
231			`always @(posedge Clk or posedge Reset)`
232	7	maverickis	`if (Reset)`
233			`send_pause_frame_counter <=0;`
234			`else if(Current_state!=StateSendPauseFrame)`
235			`send_pause_frame_counter <=0;`
236			`else`
237			`send_pause_frame_counter <=send_pause_frame_counter +1;`
238	5	maverickis
239			`always @(posedge Clk or posedge Reset)`
240	7	maverickis	`if (Reset)`
241			`pause_counter <=0;`
242			`else if (Current_state!=StatePause)`
243			`pause_counter <=0;`
244			`else`
245			`pause_counter <=pause_counter+1;`
246
247	5	maverickis	`always @(posedge Clk or posedge Reset)`
248	7	maverickis	`if (Reset)`
249			`IPLengthCounter <=0;`
250			`else if (Current_state==StateSwitchNext)`
251			`IPLengthCounter <=0;`
252			`else if (IPLengthCounter!=8'hff&&(Current_state==StateData\|\|Current_state==StatePAD))`
253			`IPLengthCounter <=IPLengthCounter+1;`
254	5	maverickis
255			`always @(posedge Clk or posedge Reset)`
256	7	maverickis	`if (Reset)`
257			`PADCounter <=0;`
258			`else if (Current_state!=StatePAD)`
259			`PADCounter <=0;`
260			`else`
261			`PADCounter <=PADCounter+1;`
262	5	maverickis
263			`always @(posedge Clk or posedge Reset)`
264	7	maverickis	`if (Reset)`
265			`Current_state <=StateDefer;`
266			`else`
267			`Current_state <=Next_state;`
268
269	5	maverickis	`always @ (*)`
270	7	maverickis	`case (Current_state)`
271			`StateDefer:`
272			`if ((FullDuplex)\|\|(!FullDuplex&&!CRS))`
273			`Next_state=StateIFG;`
274			`else`
275			`Next_state=Current_state;`
276			`StateIFG:`
277			`if (!FullDuplex&&CRS)`
278			`Next_state=StateDefer;`
279			`else if ((FullDuplex&&IFG_counter==IFGset-4)\|\|(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//ȥ��һЩ��ʱ��`
280			`Next_state=StateIdle;`
281			`else`
282			`Next_state=Current_state;`
283			`StateIdle:`
284			`if (!FullDuplex&&CRS)`
285			`Next_state=StateDefer;`
286			`else if (pause_apply)`
287			`Next_state=StatePause;`
288			`else if ((FullDuplex&&Fifo_ra)\|\|(!FullDuplex&&!CRS&&Fifo_ra)\|\|(pause_frame_send_en_dl1&&(xoff_gen\|\|xon_gen)))`
289			`Next_state=StatePreamble;`
290			`else`
291			`Next_state=Current_state;`
292			`StatePause:`
293			`if (pause_counter==512/8)`
294			`Next_state=StateDefer;`
295			`else`
296			`Next_state=Current_state;`
297			`StatePreamble:`
298			`if (!FullDuplex&&Collision)`
299			`Next_state=StateJam;`
300			`else if ((FullDuplex&&Preamble_counter==7)\|\|(!FullDuplex&&!Collision&&Preamble_counter==7))`
301			`Next_state=StateSFD;`
302			`else`
303			`Next_state=Current_state;`
304			`StateSFD:`
305			`if (!FullDuplex&&Collision)`
306			`Next_state=StateJam;`
307			`else if (pause_frame_send_en_dl1&&(xoff_gen\|\|xon_gen))`
308			`Next_state=StateSendPauseFrame;`
309			`else`
310			`Next_state=StateData;`
311			`StateSendPauseFrame:`
312			`if (send_pause_frame_counter==19)`
313			`Next_state=StatePAD;`
314			`else`
315			`Next_state=Current_state;`
316			`StateData:`
317			`if (!FullDuplex&&Collision)`
318			`Next_state=StateJam;`
319			`else if (Fifo_data_err_empty)`
320			`Next_state=StateFFEmptyDrop;`
321			`else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0`
322			`Next_state=StateFCS;`
323			`else if (Fifo_eop)`
324			`Next_state=StatePAD;`
325			`else`
326			`Next_state=StateData;`
327			`StatePAD:`
328			`if (!FullDuplex&&Collision)`
329			`Next_state=StateJam;`
330			`else if (IPLengthCounter>=59)`
331			`Next_state=StateFCS;`
332			`else`
333			`Next_state=Current_state;`
334			`StateJam:`
335			`if (RetryCnt<=MaxRetry&&JamCounter==16)`
336			`Next_state=StateBackOff;`
337			`else if (RetryCnt>MaxRetry)`
338			`Next_state=StateJamDrop;`
339			`else`
340			`Next_state=Current_state;`
341			`StateBackOff:`
342			`if (Random_time_meet)`
343			`Next_state =StateDefer;`
344			`else`
345			`Next_state =Current_state;`
346			`StateFCS:`
347			`if (!FullDuplex&&Collision)`
348			`Next_state =StateJam;`
349			`else if (pause_frame_send_en_dl1&&(xoff_gen\|\|xon_gen))`
350			`Next_state =StateDefer;`
351			`else if (CRC_end)`
352			`Next_state =StateSwitchNext;`
353			`else`
354			`Next_state =Current_state;`
355			`StateFFEmptyDrop:`
356			`if (Fifo_eop)`
357			`Next_state =StateSwitchNext;`
358			`else`
359			`Next_state =Current_state;`
360			`StateJamDrop:`
361			`if (Fifo_eop)`
362			`Next_state =StateSwitchNext;`
363			`else`
364			`Next_state =Current_state;`
365			`StateSwitchNext:`
366			`Next_state =StateDefer;`
367			`default:`
368			`Next_state =StateDefer;`
369			`endcase`
370	5	maverickis
371
372	7	maverickis
373	5	maverickis	`always @ (posedge Clk or posedge Reset)`
374	7	maverickis	`if (Reset)`
375			`JamCounter <=0;`
376			`else if (Current_state!=StateJam)`
377			`JamCounter <=0;`
378			`else if (Current_state==StateJam)`
379			`JamCounter <=JamCounter+1;`
380
381
382	5	maverickis	`always @ (posedge Clk or posedge Reset)`
383	7	maverickis	`if (Reset)`
384			`RetryCnt <=0;`
385			`else if (Current_state==StateSwitchNext)`
386			`RetryCnt <=0;`
387			`else if (Current_state==StateJam&&Next_state==StateBackOff)`
388			`RetryCnt <=RetryCnt + 1;`
389
390	5	maverickis	`always @ (posedge Clk or posedge Reset)`
391	7	maverickis	`if (Reset)`
392			`IFG_counter <=0;`
393			`else if (Current_state!=StateIFG)`
394			`IFG_counter <=0;`
395			`else`
396			`IFG_counter <=IFG_counter + 1;`
397	5	maverickis
398			`always @ (posedge Clk or posedge Reset)`
399	7	maverickis	`if (Reset)`
400			`Preamble_counter <=0;`
401			`else if (Current_state!=StatePreamble)`
402			`Preamble_counter <=0;`
403			`else`
404			`Preamble_counter <=Preamble_counter+ 1;`
405
406	5	maverickis	`always @ (posedge Clk or posedge Reset)`
407	7	maverickis	`if (Reset)`
408			`PktDrpEvenPtr <=0;`
409			`else if(Current_state==StateJamDrop\|\|Current_state==StateFFEmptyDrop)`
410			`PktDrpEvenPtr <=~PktDrpEvenPtr;`
411	5	maverickis	`//******************************************************************************`
412			`//generate output signals`
413			`//******************************************************************************`
414			`//CRC related`
415			`always @(Current_state)`
416	7	maverickis	`if (Current_state==StateSFD)`
417			`CRC_init =1;`
418			`else`
419			`CRC_init =0;`
420
421	5	maverickis	`assign Frame_data=TxD_tmp;`
422
423			`always @(Current_state)`
424	7	maverickis	`if (Current_state==StateData\|\|Current_state==StatePAD)`
425			`Data_en =1;`
426			`else`
427			`Data_en =0;`
428
429	5	maverickis	`always @(Current_state)`
430	7	maverickis	`if (Current_state==StateFCS)`
431			`CRC_rd =1;`
432			`else`
433			`CRC_rd =0;`
434
435	5	maverickis	`//Ramdon_gen interface`
436			`always @(Current_state or Next_state)`
437	7	maverickis	`if (Current_state==StateJam&&Next_state==StateBackOff)`
438			`Random_init =1;`
439			`else`
440			`Random_init =0;`
441	5	maverickis
442			`//MAC_rx_FF`
443			`//data have one cycle delay after fifo read signals`
444			`always @ (*)`
445	7	maverickis	`if (Current_state==StateData \|\|`
446			`Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen\|\|xon_gen)) \|\|`
447			`Current_state==StateJamDrop&&PktDrpEvenPtr\|\|`
448			`Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )`
449			`Fifo_rd =1;`
450			`else`
451			`Fifo_rd =0;`
452
453	5	maverickis	`always @ (Current_state)`
454	7	maverickis	`if (Current_state==StateSwitchNext)`
455			`Fifo_rd_finish =1;`
456			`else`
457			`Fifo_rd_finish =0;`
458
459	5	maverickis	`always @ (Current_state)`
460	7	maverickis	`if (Current_state==StateJam)`
461			`Fifo_rd_retry =1;`
462			`else`
463			`Fifo_rd_retry =0;`
464	5	maverickis	`//RMII`
465			`always @(Current_state)`
466	7	maverickis	`if (Current_state==StatePreamble\|\|Current_state==StateSFD\|\|`
467			`Current_state==StateData\|\|Current_state==StateSendPauseFrame\|\|`
468			`Current_state==StateFCS\|\|Current_state==StatePAD\|\|Current_state==StateJam)`
469			`TxEn_tmp =1;`
470			`else`
471			`TxEn_tmp =0;`
472	5	maverickis
473	7	maverickis	`//gen txd data`
474	5	maverickis	`always @(*)`
475	7	maverickis	`case (Current_state)`
476			`StatePreamble:`
477			`TxD_tmp =8'h55;`
478			`StateSFD:`
479			`TxD_tmp =8'hd5;`
480			`StateData:`
481			`if (Src_MAC_ptr&&MAC_tx_add_en)`
482			`TxD_tmp =MAC_tx_addr_data;`
483			`else`
484			`TxD_tmp =Fifo_data;`
485			`StateSendPauseFrame:`
486			`if (Src_MAC_ptr)`
487			`TxD_tmp =MAC_tx_addr_data;`
488			`else`
489			`case (send_pause_frame_counter)`
490			`5'd0: TxD_tmp =8'h01;`
491			`5'd1: TxD_tmp =8'h80;`
492			`5'd2: TxD_tmp =8'hc2;`
493			`5'd3: TxD_tmp =8'h00;`
494			`5'd4: TxD_tmp =8'h00;`
495			`5'd5: TxD_tmp =8'h01;`
496			`5'd12: TxD_tmp =8'h88;//type`
497			`5'd13: TxD_tmp =8'h08;//`
498			`5'd14: TxD_tmp =8'h00;//opcode`
499			`5'd15: TxD_tmp =8'h01;`
500			`5'd16: TxD_tmp =pause_quanta_set_dl1[15:8];`

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[/] [ethernet_tri_mode/] [tags/] [release-1-0/] [rtl/] [verilog/] [MAC_tx/] [MAC_tx_Ctrl.v] - Blame information for rev 15