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[/] [ethernet_tri_mode/] [tags/] [release-1-0/] [rtl/] [verilog/] [RMON/] [RMON_addr_gen.v] - Blame information for rev 33

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  RMON_addr_gen.v                                             ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.2  2005/12/16 06:44:19  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//         
module RMON_addr_gen(
Clk                 ,
Reset               ,
//RMON                                             
Pkt_type_rmon       ,
Pkt_length_rmon     ,
Apply_rmon          ,//pluse signal looks like eop 
Pkt_err_type_rmon   ,
//                                                 
Reg_apply           ,
Reg_addr            ,
Reg_data            ,
Reg_next            ,
//CPU                                              
Reg_drop_apply
);
input           Clk                 ;
input           Reset               ;
                //RMON
input   [2:0]   Pkt_type_rmon       ;
input   [15:0]  Pkt_length_rmon     ;
input           Apply_rmon          ;//pluse signal looks like eop
input   [2:0]   Pkt_err_type_rmon   ;
                //RMON_ctrl
output          Reg_apply           ;
output  [4:0]   Reg_addr            ;
output  [15:0]  Reg_data            ;
input           Reg_next            ;
                //CPU
output          Reg_drop_apply      ;
 
//******************************************************************************
//internal signals                                                              
//******************************************************************************
parameter       StateIdle       =5'b00001;
parameter       StatePktLength  =5'b00010;
parameter       StatePktNumber  =5'b00100;
parameter       StatePktType    =5'b01000;
parameter       StatePktRange   =5'b10000;
 
reg [4:0]       CurrentState;
reg [4:0]       NextState;
 
reg [2:0]       PktTypeReg      ;
reg [15:0]      PktLengthReg    ;
reg [2:0]       PktErrTypeReg   ;
 
reg             Reg_apply       ;
reg [4:0]       Reg_addr            ;
reg [15:0]      Reg_data            ;
reg             Reg_drop_apply  ;
//******************************************************************************
//register boundery signals    
 
//******************************************************************************
reg             Apply_rmon_dl1;
reg             Apply_rmon_dl2;
reg             Apply_rmon_pulse;
reg [2:0]       Pkt_type_rmon_dl1       ;
reg [15:0]      Pkt_length_rmon_dl1     ;
reg [2:0]       Pkt_err_type_rmon_dl1   ;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        begin
        Pkt_type_rmon_dl1       <=0;
        Pkt_length_rmon_dl1     <=0;
        Pkt_err_type_rmon_dl1   <=0;
        end
    else
        begin
        Pkt_type_rmon_dl1       <=Pkt_type_rmon     ;
        Pkt_length_rmon_dl1     <=Pkt_length_rmon   ;
        Pkt_err_type_rmon_dl1   <=Pkt_err_type_rmon ;
        end
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        begin
        Apply_rmon_dl1  <=0;
        Apply_rmon_dl2  <=0;
        end
    else
        begin
        Apply_rmon_dl1  <=Apply_rmon;
        Apply_rmon_dl2  <=Apply_rmon_dl1;
        end
 
always @(Apply_rmon_dl1 or Apply_rmon_dl2)
    if (Apply_rmon_dl1&!Apply_rmon_dl2)
        Apply_rmon_pulse    =1;
    else
        Apply_rmon_pulse    =0;
 
 
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        begin
        PktTypeReg          <=0;
        PktLengthReg        <=0;
        PktErrTypeReg       <=0;
        end
    else if (Apply_rmon_pulse&&CurrentState==StateIdle)
        begin
        PktTypeReg          <=Pkt_type_rmon_dl1     ;
        PktLengthReg        <=Pkt_length_rmon_dl1   ;
        PktErrTypeReg       <=Pkt_err_type_rmon_dl1 ;
        end
 
 
//******************************************************************************
//State Machine                                                             
//******************************************************************************
always @(posedge Clk or posedge Reset)
    if (Reset)
        CurrentState    <=StateIdle;
    else
        CurrentState    <=NextState;
 
always @(CurrentState or Apply_rmon_pulse or Reg_next)
    case (CurrentState)
        StateIdle:
            if (Apply_rmon_pulse)
                NextState   =StatePktLength;
            else
                NextState   =StateIdle;
        StatePktLength:
            if (Reg_next)
                NextState   =StatePktNumber;
            else
                NextState   =CurrentState;
        StatePktNumber:
            if (Reg_next)
                NextState   =StatePktType;
            else
                NextState   =CurrentState;
        StatePktType:
            if (Reg_next)
                NextState   =StatePktRange;
            else
                NextState   =CurrentState;
        StatePktRange:
            if (Reg_next)
                NextState   =StateIdle;
            else
                NextState   =CurrentState;
        default:
                NextState   =StateIdle;
    endcase
 
//******************************************************************************
//gen output signals                                                            
//******************************************************************************
//Reg_apply
always @ (CurrentState)
    if (CurrentState==StatePktLength||CurrentState==StatePktNumber||
        CurrentState==StatePktType||CurrentState==StatePktRange)
        Reg_apply   =1;
    else
        Reg_apply   =0;
 
//Reg_addr
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Reg_addr    <=0;
    else case (CurrentState)
            StatePktLength:
                Reg_addr    <=5'd00;
            StatePktNumber:
                Reg_addr    <=5'd01;
            StatePktType:
                case(PktTypeReg)
                    3'b011:
                        Reg_addr    <=5'd02;    //broadcast
                    3'b001:
                        Reg_addr    <=5'd03;    //multicast 
                    3'b100:
                        Reg_addr    <=5'd16;    //pause frame   
                    default:
                        Reg_addr    <=5'd04;    //unicast
                endcase
            StatePktRange:
                case(PktErrTypeReg)
                    3'b001:
                        Reg_addr    <=5'd05;
                    3'b010:
                        Reg_addr    <=5'd06;
                    3'b011:
                        Reg_addr    <=5'd07;
                    3'b100:
                        if (PktLengthReg<64)
                            Reg_addr    <=5'd08;
                        else if (PktLengthReg==64)
                            Reg_addr    <=5'd09;
                        else if (PktLengthReg<128)
                            Reg_addr    <=5'd10;
                        else if (PktLengthReg<256)
                            Reg_addr    <=5'd11;
                        else if (PktLengthReg<512)
                            Reg_addr    <=5'd12;
                        else if (PktLengthReg<1024)
                            Reg_addr    <=5'd13;
                        else if (PktLengthReg<1519)
                            Reg_addr    <=5'd14;
                        else
                            Reg_addr    <=5'd15;
                    default:
                        Reg_addr    <=5'd05;
                endcase
            default:
                    Reg_addr    <=5'd05;
        endcase
 
//Reg_data
always @ (CurrentState or PktLengthReg)
    case (CurrentState)
        StatePktLength:
            Reg_data    =PktLengthReg;
        StatePktNumber:
            Reg_data    =1;
        StatePktType:
            Reg_data =1;
        StatePktRange:
            Reg_data =1;
        default:
            Reg_data =0;
    endcase
 
//Reg_drop_apply
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Reg_drop_apply  <=0;
    else if (CurrentState!=StateIdle&&Apply_rmon_pulse)
        Reg_drop_apply  <=1;
    else
        Reg_drop_apply  <=0;
 
 
endmodule
 

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// RMON_addr_gen.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9	7	maverickis	`//// - Jon Gao (gaojon@yahoo.com) ////`
10	5	maverickis	`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41	6	maverickis	`// $Log: not supported by cvs2svn $`
42	7	maverickis	`// Revision 1.2 2005/12/16 06:44:19 Administrator`
43			`// replaced tab with space.`
44			`// passed 9.6k length frame test.`
45			`//`
46	6	maverickis	`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
47			`// no message`
48			`//`
49	5	maverickis	`module RMON_addr_gen(`
50	7	maverickis	`Clk ,`
51			`Reset ,`
52	5	maverickis	`//RMON`
53	7	maverickis	`Pkt_type_rmon ,`
54			`Pkt_length_rmon ,`
55			`Apply_rmon ,//pluse signal looks like eop`
56			`Pkt_err_type_rmon ,`
57	5	maverickis	`//`
58	7	maverickis	`Reg_apply ,`
59			`Reg_addr ,`
60			`Reg_data ,`
61			`Reg_next ,`
62	5	maverickis	`//CPU`
63	7	maverickis	`Reg_drop_apply`
64	5	maverickis	`);`
65	7	maverickis	`input Clk ;`
66			`input Reset ;`
67			`//RMON`
68			`input [2:0] Pkt_type_rmon ;`
69			`input [15:0] Pkt_length_rmon ;`
70			`input Apply_rmon ;//pluse signal looks like eop`
71			`input [2:0] Pkt_err_type_rmon ;`
72			`//RMON_ctrl`
73			`output Reg_apply ;`
74			`output [4:0] Reg_addr ;`
75			`output [15:0] Reg_data ;`
76			`input Reg_next ;`
77			`//CPU`
78			`output Reg_drop_apply ;`
79	5	maverickis
80			`//******************************************************************************`
81			`//internal signals`
82			`//******************************************************************************`
83	7	maverickis	`parameter StateIdle =5'b00001;`
84			`parameter StatePktLength =5'b00010;`
85			`parameter StatePktNumber =5'b00100;`
86			`parameter StatePktType =5'b01000;`
87			`parameter StatePktRange =5'b10000;`
88	5	maverickis
89	7	maverickis	`reg [4:0] CurrentState;`
90			`reg [4:0] NextState;`
91
92			`reg [2:0] PktTypeReg ;`
93			`reg [15:0] PktLengthReg ;`
94			`reg [2:0] PktErrTypeReg ;`
95
96			`reg Reg_apply ;`
97			`reg [4:0] Reg_addr ;`
98			`reg [15:0] Reg_data ;`
99			`reg Reg_drop_apply ;`
100	5	maverickis	`//******************************************************************************`
101			`//register boundery signals`
102
103			`//******************************************************************************`
104	7	maverickis	`reg Apply_rmon_dl1;`
105			`reg Apply_rmon_dl2;`
106			`reg Apply_rmon_pulse;`
107			`reg [2:0] Pkt_type_rmon_dl1 ;`
108			`reg [15:0] Pkt_length_rmon_dl1 ;`
109			`reg [2:0] Pkt_err_type_rmon_dl1 ;`
110	5	maverickis
111			`always @(posedge Clk or posedge Reset)`
112	7	maverickis	`if (Reset)`
113			`begin`
114			`Pkt_type_rmon_dl1 <=0;`
115			`Pkt_length_rmon_dl1 <=0;`
116			`Pkt_err_type_rmon_dl1 <=0;`
117			`end`
118			`else`
119			`begin`
120			`Pkt_type_rmon_dl1 <=Pkt_type_rmon ;`
121			`Pkt_length_rmon_dl1 <=Pkt_length_rmon ;`
122			`Pkt_err_type_rmon_dl1 <=Pkt_err_type_rmon ;`
123			`end`
124	5	maverickis
125			`always @(posedge Clk or posedge Reset)`
126	7	maverickis	`if (Reset)`
127			`begin`
128			`Apply_rmon_dl1 <=0;`
129			`Apply_rmon_dl2 <=0;`
130			`end`
131			`else`
132			`begin`
133			`Apply_rmon_dl1 <=Apply_rmon;`
134			`Apply_rmon_dl2 <=Apply_rmon_dl1;`
135			`end`
136
137	5	maverickis	`always @(Apply_rmon_dl1 or Apply_rmon_dl2)`
138	7	maverickis	`if (Apply_rmon_dl1&!Apply_rmon_dl2)`
139			`Apply_rmon_pulse =1;`
140			`else`
141			`Apply_rmon_pulse =0;`
142	5	maverickis
143
144	7	maverickis
145	5	maverickis	`always @(posedge Clk or posedge Reset)`
146	7	maverickis	`if (Reset)`
147			`begin`
148			`PktTypeReg <=0;`
149			`PktLengthReg <=0;`
150			`PktErrTypeReg <=0;`
151			`end`
152			`else if (Apply_rmon_pulse&&CurrentState==StateIdle)`
153			`begin`
154			`PktTypeReg <=Pkt_type_rmon_dl1 ;`
155			`PktLengthReg <=Pkt_length_rmon_dl1 ;`
156			`PktErrTypeReg <=Pkt_err_type_rmon_dl1 ;`
157			`end`
158
159	5	maverickis
160			`//******************************************************************************`
161			`//State Machine`
162			`//******************************************************************************`
163			`always @(posedge Clk or posedge Reset)`
164	7	maverickis	`if (Reset)`
165			`CurrentState <=StateIdle;`
166			`else`
167			`CurrentState <=NextState;`
168
169	5	maverickis	`always @(CurrentState or Apply_rmon_pulse or Reg_next)`
170	7	maverickis	`case (CurrentState)`
171			`StateIdle:`
172			`if (Apply_rmon_pulse)`
173			`NextState =StatePktLength;`
174			`else`
175			`NextState =StateIdle;`
176			`StatePktLength:`
177			`if (Reg_next)`
178			`NextState =StatePktNumber;`
179			`else`
180			`NextState =CurrentState;`
181			`StatePktNumber:`
182			`if (Reg_next)`
183			`NextState =StatePktType;`
184			`else`
185			`NextState =CurrentState;`
186			`StatePktType:`
187			`if (Reg_next)`
188			`NextState =StatePktRange;`
189			`else`
190			`NextState =CurrentState;`
191			`StatePktRange:`
192			`if (Reg_next)`
193			`NextState =StateIdle;`
194			`else`
195			`NextState =CurrentState;`
196			`default:`
197			`NextState =StateIdle;`
198			`endcase`
199
200	5	maverickis	`//******************************************************************************`
201			`//gen output signals`
202			`//******************************************************************************`
203			`//Reg_apply`
204			`always @ (CurrentState)`
205	7	maverickis	`if (CurrentState==StatePktLength\|\|CurrentState==StatePktNumber\|\|`
206			`CurrentState==StatePktType\|\|CurrentState==StatePktRange)`
207			`Reg_apply =1;`
208			`else`
209			`Reg_apply =0;`
210
211	5	maverickis	`//Reg_addr`
212			`always @ (posedge Clk or posedge Reset)`
213	7	maverickis	`if (Reset)`
214			`Reg_addr <=0;`
215			`else case (CurrentState)`
216			`StatePktLength:`
217			`Reg_addr <=5'd00;`
218			`StatePktNumber:`
219			`Reg_addr <=5'd01;`
220			`StatePktType:`
221			`case(PktTypeReg)`
222			`3'b011:`
223			`Reg_addr <=5'd02; //broadcast`
224			`3'b001:`
225			`Reg_addr <=5'd03; //multicast`
226			`3'b100:`
227			`Reg_addr <=5'd16; //pause frame`
228			`default:`
229			`Reg_addr <=5'd04; //unicast`
230			`endcase`
231			`StatePktRange:`
232			`case(PktErrTypeReg)`
233			`3'b001:`
234			`Reg_addr <=5'd05;`
235			`3'b010:`
236			`Reg_addr <=5'd06;`
237			`3'b011:`
238			`Reg_addr <=5'd07;`
239			`3'b100:`
240			`if (PktLengthReg<64)`
241			`Reg_addr <=5'd08;`
242			`else if (PktLengthReg==64)`
243			`Reg_addr <=5'd09;`
244			`else if (PktLengthReg<128)`
245			`Reg_addr <=5'd10;`
246			`else if (PktLengthReg<256)`
247			`Reg_addr <=5'd11;`
248			`else if (PktLengthReg<512)`
249			`Reg_addr <=5'd12;`
250			`else if (PktLengthReg<1024)`
251			`Reg_addr <=5'd13;`
252			`else if (PktLengthReg<1519)`
253			`Reg_addr <=5'd14;`
254			`else`
255			`Reg_addr <=5'd15;`
256			`default:`
257			`Reg_addr <=5'd05;`
258			`endcase`
259			`default:`
260			`Reg_addr <=5'd05;`
261			`endcase`
262
263	5	maverickis	`//Reg_data`
264			`always @ (CurrentState or PktLengthReg)`
265	7	maverickis	`case (CurrentState)`
266			`StatePktLength:`
267			`Reg_data =PktLengthReg;`
268			`StatePktNumber:`
269			`Reg_data =1;`
270			`StatePktType:`
271			`Reg_data =1;`
272			`StatePktRange:`
273			`Reg_data =1;`
274			`default:`
275			`Reg_data =0;`
276			`endcase`
277
278	5	maverickis	`//Reg_drop_apply`
279			`always @ (posedge Clk or posedge Reset)`
280	7	maverickis	`if (Reset)`
281			`Reg_drop_apply <=0;`
282			`else if (CurrentState!=StateIdle&&Apply_rmon_pulse)`
283			`Reg_drop_apply <=1;`
284			`else`
285			`Reg_drop_apply <=0;`
286
287	5	maverickis
288	7	maverickis	`endmodule`
289

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[/] [ethernet_tri_mode/] [tags/] [release-1-0/] [rtl/] [verilog/] [RMON/] [RMON_addr_gen.v] - Blame information for rev 33