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[/] [ethernet_tri_mode/] [tags/] [release-1-0/] [rtl/] [verilog/] [RMON/] [RMON_ctrl.v] - Blame information for rev 6

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  RMON_CTRL.v                                             ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//  
module RMON_CTRL (
Clk                             ,
Reset                   ,
//RMON_CTRL        
Reg_apply_0             ,
Reg_addr_0              ,
Reg_data_0              ,
Reg_next_0              ,
Reg_apply_1             ,
Reg_addr_1              ,
Reg_data_1              ,
Reg_next_1              ,
//dual-port ram
Addra                           ,
Dina                            ,
Douta                           ,
Wea                                     ,
//CPU                  
CPU_rd_addr             ,
CPU_rd_apply            ,
CPU_rd_grant            ,
CPU_rd_dout
 
);
input                   Clk                             ;
input                   Reset                   ;
                                //RMON_CTRL
input                   Reg_apply_0             ;
input[4:0]               Reg_addr_0              ;
input[15:0]              Reg_data_0              ;
output                  Reg_next_0              ;
 
input                   Reg_apply_1             ;
input[4:0]               Reg_addr_1              ;
input[15:0]              Reg_data_1              ;
output                  Reg_next_1              ;
 
 
                                //dual-port ram 
                                //port-a for Rmon  
output[5:0]      Addra                           ;
output[31:0]     Dina                            ;
input[31:0]      Douta                           ;
output                  Wea                                     ;
                                //CPU
input[5:0]               CPU_rd_addr                     ;
input                   CPU_rd_apply            ;
output                  CPU_rd_grant            ;
output[31:0]     CPU_rd_dout                     ;
 
 
 
 
//******************************************************************************
//internal signals                                                              
//******************************************************************************
 
parameter               StateCPU                =5'd00;
parameter               StateMAC0               =5'd01;
parameter               StateMAC1               =5'd02;
 
 
reg[4:0]         CurrentState;
reg[4:0]         NextState;
reg[4:0]         CurrentState_reg;
 
reg[4:0]         StepCounter;
reg[31:0]                DoutaReg;
reg[5:0]                 Addra                           ;
reg[31:0]                Dina;
reg                             Reg_next_0              ;
reg                             Reg_next_1              ;
reg                             Write;
reg                             Read;
reg                             Pipeline;
reg[31:0]                CPU_rd_dout                     ;
reg                             CPU_rd_apply_reg        ;
//******************************************************************************
//State Machine                                                            
//******************************************************************************
 
always @(posedge Clk or posedge Reset)
        if (Reset)
                CurrentState    <=StateMAC0;
        else
                CurrentState    <=NextState;
 
always @(posedge Clk or posedge Reset)
        if (Reset)
                CurrentState_reg        <=StateMAC0;
        else if(CurrentState!=StateCPU)
                CurrentState_reg        <=CurrentState;
 
always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg
                                                                           or Reg_apply_1
                                                                           or StepCounter
                                                                           )
        case(CurrentState)
                StateMAC0:
                        if(!Reg_apply_0&&CPU_rd_apply_reg)
                                NextState       =StateCPU;
                        else if(!Reg_apply_0)
                                NextState       =StateMAC1;
                        else
                                NextState       =CurrentState;
                StateMAC1:
                        if(!Reg_apply_1&&CPU_rd_apply_reg)
                                NextState       =StateCPU;
                        else if(!Reg_apply_1)
                                NextState       =StateMAC0;
                        else
                                NextState       =CurrentState;
                StateCPU:
                        if (StepCounter==3)
                                case (CurrentState_reg)
                                        StateMAC0       :NextState      =StateMAC0 ;
                                        StateMAC1       :NextState      =StateMAC1 ;
                                        default         :NextState      =StateMAC0;
                                endcase
                        else
                                NextState       =CurrentState;
 
                default:
                                NextState       =StateMAC0;
        endcase
 
 
 
always @(posedge Clk or posedge Reset)
        if (Reset)
                StepCounter             <=0;
        else if(NextState!=CurrentState)
                StepCounter             <=0;
        else if (StepCounter!=4'hf)
                StepCounter             <=StepCounter + 1;
 
//******************************************************************************
//temp signals                                                            
//******************************************************************************
always @(StepCounter)
        if(     StepCounter==1||StepCounter==4||
                StepCounter==7||StepCounter==10)
                Read    =1;
        else
                Read    =0;
 
always @(StepCounter or CurrentState)
        if(     StepCounter==2||StepCounter==5||
                StepCounter==8||StepCounter==11)
                Pipeline        =1;
        else
                Pipeline        =0;
 
always @(StepCounter or CurrentState)
        if(     StepCounter==3||StepCounter==6||
                StepCounter==9||StepCounter==12)
                Write   =1;
        else
                Write   =0;
 
always @(posedge Clk or posedge Reset)
        if (Reset)
                DoutaReg                <=0;
        else if (Read)
                DoutaReg                <=Douta;
 
 
//******************************************************************************
//gen output signals                                                        
//******************************************************************************        
//Addra 
always @(*)
        case(CurrentState)
                StateMAC0 :             Addra={1'd0 ,Reg_addr_0 };
                StateMAC1 :             Addra={1'd1 ,Reg_addr_1 };
                StateCPU:               Addra=CPU_rd_addr;
                default:                Addra=0;
                endcase
 
//Dina
always @(posedge Clk or posedge Reset)
        if (Reset)
                Dina    <=0;
        else
                case(CurrentState)
                        StateMAC0 :             Dina<=Douta+Reg_data_0 ;
                        StateMAC1 :             Dina<=Douta+Reg_data_1 ;
                        StateCPU:               Dina<=0;
                        default:                Dina<=0;
                endcase
 
assign  Wea             =Write;
//Reg_next
always @(CurrentState or Pipeline)
        if(CurrentState==StateMAC0)
                Reg_next_0      =Pipeline;
        else
                Reg_next_0      =0;
 
always @(CurrentState or Pipeline)
        if(CurrentState==StateMAC1)
                Reg_next_1      =Pipeline;
        else
                Reg_next_1      =0;
 
 
//CPU_rd_grant   
reg             CPU_rd_apply_dl1;
reg             CPU_rd_apply_dl2;
//rising edge
always @ (posedge Clk or posedge Reset)
        if (Reset)
                begin
                CPU_rd_apply_dl1                <=0;
        CPU_rd_apply_dl2        <=0;
                end
        else
                begin
                CPU_rd_apply_dl1                <=CPU_rd_apply;
        CPU_rd_apply_dl2        <=CPU_rd_apply_dl1;
                end
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                CPU_rd_apply_reg        <=0;
        else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)
                CPU_rd_apply_reg        <=1;
        else if (CurrentState==StateCPU&&Write)
                CPU_rd_apply_reg        <=0;
 
assign CPU_rd_grant     =!CPU_rd_apply_reg;
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                CPU_rd_dout             <=0;
        else if (Pipeline&&CurrentState==StateCPU)
                CPU_rd_dout             <=Douta;
 
endmodule

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Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [tags/] [release-1-0/] [rtl/] [verilog/] [RMON/] [RMON_ctrl.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// RMON_CTRL.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41	6	maverickis	`// $Log: not supported by cvs2svn $`
42			`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
43			`// no message`
44			`//`
45	5	maverickis	`module RMON_CTRL (`
46			`Clk ,`
47			`Reset ,`
48			`//RMON_CTRL`
49			`Reg_apply_0 ,`
50			`Reg_addr_0 ,`
51			`Reg_data_0 ,`
52			`Reg_next_0 ,`
53			`Reg_apply_1 ,`
54			`Reg_addr_1 ,`
55			`Reg_data_1 ,`
56			`Reg_next_1 ,`
57			`//dual-port ram`
58			`Addra ,`
59			`Dina ,`
60			`Douta ,`
61			`Wea ,`
62			`//CPU`
63			`CPU_rd_addr ,`
64			`CPU_rd_apply ,`
65			`CPU_rd_grant ,`
66			`CPU_rd_dout`
67
68			`);`
69			`input Clk ;`
70			`input Reset ;`
71			`//RMON_CTRL`
72			`input Reg_apply_0 ;`
73			`input[4:0] Reg_addr_0 ;`
74			`input[15:0] Reg_data_0 ;`
75			`output Reg_next_0 ;`
76
77			`input Reg_apply_1 ;`
78			`input[4:0] Reg_addr_1 ;`
79			`input[15:0] Reg_data_1 ;`
80			`output Reg_next_1 ;`
81
82
83			`//dual-port ram`
84			`//port-a for Rmon`
85			`output[5:0] Addra ;`
86			`output[31:0] Dina ;`
87			`input[31:0] Douta ;`
88			`output Wea ;`
89			`//CPU`
90			`input[5:0] CPU_rd_addr ;`
91			`input CPU_rd_apply ;`
92			`output CPU_rd_grant ;`
93			`output[31:0] CPU_rd_dout ;`
94
95
96
97
98			`//******************************************************************************`
99			`//internal signals`
100			`//******************************************************************************`
101
102			`parameter StateCPU =5'd00;`
103			`parameter StateMAC0 =5'd01;`
104			`parameter StateMAC1 =5'd02;`
105
106
107			`reg[4:0] CurrentState;`
108			`reg[4:0] NextState;`
109			`reg[4:0] CurrentState_reg;`
110
111			`reg[4:0] StepCounter;`
112			`reg[31:0] DoutaReg;`
113			`reg[5:0] Addra ;`
114			`reg[31:0] Dina;`
115			`reg Reg_next_0 ;`
116			`reg Reg_next_1 ;`
117			`reg Write;`
118			`reg Read;`
119			`reg Pipeline;`
120			`reg[31:0] CPU_rd_dout ;`
121			`reg CPU_rd_apply_reg ;`
122			`//******************************************************************************`
123			`//State Machine`
124			`//******************************************************************************`
125
126			`always @(posedge Clk or posedge Reset)`
127			`if (Reset)`
128			`CurrentState <=StateMAC0;`
129			`else`
130			`CurrentState <=NextState;`
131
132			`always @(posedge Clk or posedge Reset)`
133			`if (Reset)`
134			`CurrentState_reg <=StateMAC0;`
135			`else if(CurrentState!=StateCPU)`
136			`CurrentState_reg <=CurrentState;`
137
138			`always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg`
139			`or Reg_apply_1`
140			`or StepCounter`
141			`)`
142			`case(CurrentState)`
143			`StateMAC0:`
144			`if(!Reg_apply_0&&CPU_rd_apply_reg)`
145			`NextState =StateCPU;`
146			`else if(!Reg_apply_0)`
147			`NextState =StateMAC1;`
148			`else`
149			`NextState =CurrentState;`
150			`StateMAC1:`
151			`if(!Reg_apply_1&&CPU_rd_apply_reg)`
152			`NextState =StateCPU;`
153			`else if(!Reg_apply_1)`
154			`NextState =StateMAC0;`
155			`else`
156			`NextState =CurrentState;`
157			`StateCPU:`
158			`if (StepCounter==3)`
159			`case (CurrentState_reg)`
160			`StateMAC0 :NextState =StateMAC0 ;`
161			`StateMAC1 :NextState =StateMAC1 ;`
162			`default :NextState =StateMAC0;`
163			`endcase`
164			`else`
165			`NextState =CurrentState;`
166
167			`default:`
168			`NextState =StateMAC0;`
169			`endcase`
170
171
172
173			`always @(posedge Clk or posedge Reset)`
174			`if (Reset)`
175			`StepCounter <=0;`
176			`else if(NextState!=CurrentState)`
177			`StepCounter <=0;`
178			`else if (StepCounter!=4'hf)`
179			`StepCounter <=StepCounter + 1;`
180
181			`//******************************************************************************`
182			`//temp signals`
183			`//******************************************************************************`
184			`always @(StepCounter)`
185			`if( StepCounter==1\|\|StepCounter==4\|\|`
186			`StepCounter==7\|\|StepCounter==10)`
187			`Read =1;`
188			`else`
189			`Read =0;`
190
191			`always @(StepCounter or CurrentState)`
192			`if( StepCounter==2\|\|StepCounter==5\|\|`
193			`StepCounter==8\|\|StepCounter==11)`
194			`Pipeline =1;`
195			`else`
196			`Pipeline =0;`
197
198			`always @(StepCounter or CurrentState)`
199			`if( StepCounter==3\|\|StepCounter==6\|\|`
200			`StepCounter==9\|\|StepCounter==12)`
201			`Write =1;`
202			`else`
203			`Write =0;`
204
205			`always @(posedge Clk or posedge Reset)`
206			`if (Reset)`
207			`DoutaReg <=0;`
208			`else if (Read)`
209			`DoutaReg <=Douta;`
210
211
212			`//******************************************************************************`
213			`//gen output signals`
214			`//******************************************************************************`
215			`//Addra`
216			`always @(*)`
217			`case(CurrentState)`
218			`StateMAC0 : Addra={1'd0 ,Reg_addr_0 };`
219			`StateMAC1 : Addra={1'd1 ,Reg_addr_1 };`
220			`StateCPU: Addra=CPU_rd_addr;`
221			`default: Addra=0;`
222			`endcase`
223
224			`//Dina`
225			`always @(posedge Clk or posedge Reset)`
226			`if (Reset)`
227			`Dina <=0;`
228			`else`
229			`case(CurrentState)`
230			`StateMAC0 : Dina<=Douta+Reg_data_0 ;`
231			`StateMAC1 : Dina<=Douta+Reg_data_1 ;`
232			`StateCPU: Dina<=0;`
233			`default: Dina<=0;`
234			`endcase`
235
236			`assign Wea =Write;`
237			`//Reg_next`
238			`always @(CurrentState or Pipeline)`
239			`if(CurrentState==StateMAC0)`
240			`Reg_next_0 =Pipeline;`
241			`else`
242			`Reg_next_0 =0;`
243
244			`always @(CurrentState or Pipeline)`
245			`if(CurrentState==StateMAC1)`
246			`Reg_next_1 =Pipeline;`
247			`else`
248			`Reg_next_1 =0;`
249
250
251			`//CPU_rd_grant`
252			`reg CPU_rd_apply_dl1;`
253			`reg CPU_rd_apply_dl2;`
254			`//rising edge`
255			`always @ (posedge Clk or posedge Reset)`
256			`if (Reset)`
257			`begin`
258			`CPU_rd_apply_dl1 <=0;`
259			`CPU_rd_apply_dl2 <=0;`
260			`end`
261			`else`
262			`begin`
263			`CPU_rd_apply_dl1 <=CPU_rd_apply;`
264			`CPU_rd_apply_dl2 <=CPU_rd_apply_dl1;`
265			`end`
266
267			`always @ (posedge Clk or posedge Reset)`
268			`if (Reset)`
269			`CPU_rd_apply_reg <=0;`
270			`else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)`
271			`CPU_rd_apply_reg <=1;`
272			`else if (CurrentState==StateCPU&&Write)`
273			`CPU_rd_apply_reg <=0;`
274
275			`assign CPU_rd_grant =!CPU_rd_apply_reg;`
276
277			`always @ (posedge Clk or posedge Reset)`
278			`if (Reset)`
279			`CPU_rd_dout <=0;`
280			`else if (Pipeline&&CurrentState==StateCPU)`
281			`CPU_rd_dout <=Douta;`
282
283			`endmodule`