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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  afifo.v                                                     ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
module afifo(
din,
wr_en,
wr_clk,
rd_en,
rd_clk,
ainit,
dout,
full,
almost_full,
empty,
wr_count,
rd_count,
rd_ack,
wr_ack);
 
//////////////////////////////////////////////////////
parameter               DATA_WIDTH                      =32;
parameter               ADDR_WIDTH                      =5;
parameter               COUNT_DATA_WIDTH        =5;
parameter               ALMOST_FULL_DEPTH       =8;
parameter               BLK_RAM_TYPE            ="M4K";
parameter               DUAL_PORT_TYPE          ="DUAL_PORT";// DUAL_PORT=simple dual port or BIDIR_DUAL_PORT=true dual_port 
//////////////////////////////////////////////////////
input   [DATA_WIDTH-1:0]                         din;
input                                                           wr_en;
input                                                           wr_clk;
input                                                           rd_en;
input                                                           rd_clk;
input                                                           ainit;
output  [DATA_WIDTH-1:0]                         dout;
output                                                          full;
output                                                          almost_full;
output                                                          empty;
output  [COUNT_DATA_WIDTH-1:0]           wr_count /* synthesis syn_keep=1 */;
output  [COUNT_DATA_WIDTH-1:0]           rd_count /* synthesis syn_keep=1 */;
output                                                          rd_ack;
output                                                          wr_ack;
//////////////////////////////////////////////////////  
//local signals
////////////////////////////////////////////////////// 
reg             [ADDR_WIDTH-1:0]                         Add_wr;
reg             [ADDR_WIDTH-1:0]                         Add_wr_ungray;
reg             [ADDR_WIDTH-1:0]                         Add_wr_gray;
reg             [ADDR_WIDTH-1:0]                         Add_wr_gray_dl1;
 
reg             [ADDR_WIDTH-1:0]                         Add_rd;
wire    [ADDR_WIDTH-1:0]                         Add_rd_pluse;
reg             [ADDR_WIDTH-1:0]                         Add_rd_gray;
reg             [ADDR_WIDTH-1:0]                         Add_rd_gray_dl1;
reg             [ADDR_WIDTH-1:0]                         Add_rd_ungray;
wire    [ADDR_WIDTH-1:0]                 Add_wr_pluse;
integer                                                         i;
reg                                                             full /* synthesis syn_keep=1 */;
reg                                                             empty;
wire    [ADDR_WIDTH-1:0]                         ff_used_wr;
wire    [ADDR_WIDTH-1:0]                         ff_used_rd;
reg                                                             rd_ack;
reg                                                             rd_ack_tmp;
reg                                                                     almost_full;
wire    [DATA_WIDTH-1:0]                         dout_tmp;
 
//////////////////////////////////////////////////////  
//Write clock domain
//////////////////////////////////////////////////////
assign wr_ack      =0;
assign ff_used_wr  =Add_wr-Add_rd_ungray;
 
assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
 
 
 
 
always @ (posedge ainit or posedge wr_clk)
        if (ainit)
                Add_wr_gray                     <=0;
        else
                begin
                Add_wr_gray[ADDR_WIDTH-1]       <=Add_wr[ADDR_WIDTH-1];
                for (i=ADDR_WIDTH-2;i>=0;i=i-1)
                Add_wr_gray[i]                  <=Add_wr[i+1]^Add_wr[i];
                end
 
//����ַ���з�gray����.
 
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                Add_rd_gray_dl1                 <=0;
        else
                Add_rd_gray_dl1                 <=Add_rd_gray;
 
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                Add_rd_ungray                   =0;
        else
                begin
                Add_rd_ungray[ADDR_WIDTH-1]     =Add_rd_gray_dl1[ADDR_WIDTH-1];
                for (i=ADDR_WIDTH-2;i>=0;i=i-1)
                        Add_rd_ungray[i]        =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
                end
 
assign                  Add_wr_pluse=Add_wr+1;
 
 
/*
always @ (Add_wr_pluse or Add_rd_ungray)
        if (Add_wr_pluse==Add_rd_ungray)
                full    =1;
        else
                full    =0;
 
*/
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                full    <=0;
        else if(Add_wr_pluse==Add_rd_ungray&&wr_en)
                full    <=1;
        else if(Add_wr!=Add_rd_ungray)
                full    <=0;
 
 
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                almost_full             <=0;
        else if (wr_count>=ALMOST_FULL_DEPTH)
                almost_full             <=1;
        else
                almost_full             <=0;
 
always @ (posedge wr_clk or posedge ainit)
        if (ainit)
                Add_wr  <=0;
        else if (wr_en&&!full)
                Add_wr  <=Add_wr +1;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//read clock domain
//******************************************************************************
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                rd_ack          <=0;
        else if (rd_en&&!empty)
                rd_ack          <=1;
        else
                rd_ack          <=0;
 
 
 
assign ff_used_rd       =Add_wr_ungray-Add_rd;
assign rd_count         =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
assign Add_rd_pluse     =Add_rd+1;
 
 
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                Add_rd          <=0;
        else if (rd_en&&!empty)  //��EOP��Ͳ����ˡ�
                Add_rd          <=Add_rd + 1;
 
//����ַ����gray��任.
always @ (posedge ainit or posedge rd_clk)
        if (ainit)
                Add_rd_gray                     <=0;
        else
                begin
                Add_rd_gray[ADDR_WIDTH-1]       <=Add_rd[ADDR_WIDTH-1];
                for (i=ADDR_WIDTH-2;i>=0;i=i-1)
                Add_rd_gray[i]                  <=Add_rd[i+1]^Add_rd[i];
                end
/*              Add_rd_gray                     <={     Add_rd[8],
                                                                Add_rd[8]^Add_rd[7],
                                                                Add_rd[7]^Add_rd[6],
                                                                Add_rd[6]^Add_rd[5],
                                                                Add_rd[5]^Add_rd[4],
                                                                Add_rd[4]^Add_rd[3],
                                                                Add_rd[3]^Add_rd[2],
                                                                Add_rd[2]^Add_rd[1],
                                                                Add_rd[1]^Add_rd[0]};
*/
//д��ַ���з�gray����.
 
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                Add_wr_gray_dl1         <=0;
        else
                Add_wr_gray_dl1         <=Add_wr_gray;
 
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                Add_wr_ungray           =0;
        else
                begin
                Add_wr_ungray[ADDR_WIDTH-1]     =Add_wr_gray_dl1[ADDR_WIDTH-1];
                for (i=ADDR_WIDTH-2;i>=0;i=i-1)
                        Add_wr_ungray[i]        =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
                end
 
/*              Add_wr_ungray   <={
                Add_wr_gray_dl1[8],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
*/
//empty�źŲ��� 
/*
always @ (Add_rd or Add_wr_ungray)
        if (Add_rd==Add_wr_ungray)
                empty   =1;
        else
                empty   =0;
*/
always @ (posedge rd_clk or posedge ainit)
        if (ainit)
                empty   <=1;
        else if (Add_rd_pluse==Add_wr_ungray&&rd_en)
                empty   <=1;
        else if (Add_rd!=Add_wr_ungray)
                empty   <=0;
 
 
 
//////////////////////////////////////////////////////  
//instant need change for your own dpram
////////////////////////////////////////////////////// 
duram #(
DATA_WIDTH,
ADDR_WIDTH,
BLK_RAM_TYPE,
DUAL_PORT_TYPE)
U_duram                 (
.data_a     (din                ),
.wren_a     (wr_en          ),
.address_a  (Add_wr         ),
.address_b  (Add_rd         ),
.clock_a    (wr_clk         ),
.clock_b    (rd_clk         ),
.q_b        (dout              ));
 
endmodule

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Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [tags/] [release-1-0/] [rtl/] [verilog/] [TECH/] [afifo.v] - Blame information for rev 33

Line No.	Rev	Author	Line
1	6	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// afifo.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42			`module afifo(`
43			`din,`
44			`wr_en,`
45			`wr_clk,`
46			`rd_en,`
47			`rd_clk,`
48			`ainit,`
49			`dout,`
50			`full,`
51			`almost_full,`
52			`empty,`
53			`wr_count,`
54			`rd_count,`
55			`rd_ack,`
56			`wr_ack);`
57
58			`//////////////////////////////////////////////////////`
59			`parameter DATA_WIDTH =32;`
60			`parameter ADDR_WIDTH =5;`
61			`parameter COUNT_DATA_WIDTH =5;`
62			`parameter ALMOST_FULL_DEPTH =8;`
63			`parameter BLK_RAM_TYPE ="M4K";`
64			`parameter DUAL_PORT_TYPE ="DUAL_PORT";// DUAL_PORT=simple dual port or BIDIR_DUAL_PORT=true dual_port`
65			`//////////////////////////////////////////////////////`
66			`input [DATA_WIDTH-1:0] din;`
67			`input wr_en;`
68			`input wr_clk;`
69			`input rd_en;`
70			`input rd_clk;`
71			`input ainit;`
72			`output [DATA_WIDTH-1:0] dout;`
73			`output full;`
74			`output almost_full;`
75			`output empty;`
76			`output [COUNT_DATA_WIDTH-1:0] wr_count /* synthesis syn_keep=1 */;`
77			`output [COUNT_DATA_WIDTH-1:0] rd_count /* synthesis syn_keep=1 */;`
78			`output rd_ack;`
79			`output wr_ack;`
80			`//////////////////////////////////////////////////////`
81			`//local signals`
82			`//////////////////////////////////////////////////////`
83			`reg [ADDR_WIDTH-1:0] Add_wr;`
84			`reg [ADDR_WIDTH-1:0] Add_wr_ungray;`
85			`reg [ADDR_WIDTH-1:0] Add_wr_gray;`
86			`reg [ADDR_WIDTH-1:0] Add_wr_gray_dl1;`
87
88			`reg [ADDR_WIDTH-1:0] Add_rd;`
89			`wire [ADDR_WIDTH-1:0] Add_rd_pluse;`
90			`reg [ADDR_WIDTH-1:0] Add_rd_gray;`
91			`reg [ADDR_WIDTH-1:0] Add_rd_gray_dl1;`
92			`reg [ADDR_WIDTH-1:0] Add_rd_ungray;`
93			`wire [ADDR_WIDTH-1:0] Add_wr_pluse;`
94			`integer i;`
95			`reg full /* synthesis syn_keep=1 */;`
96			`reg empty;`
97			`wire [ADDR_WIDTH-1:0] ff_used_wr;`
98			`wire [ADDR_WIDTH-1:0] ff_used_rd;`
99			`reg rd_ack;`
100			`reg rd_ack_tmp;`
101			`reg almost_full;`
102			`wire [DATA_WIDTH-1:0] dout_tmp;`
103
104			`//////////////////////////////////////////////////////`
105			`//Write clock domain`
106			`//////////////////////////////////////////////////////`
107			`assign wr_ack =0;`
108			`assign ff_used_wr =Add_wr-Add_rd_ungray;`
109
110			`assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];`
111
112
113
114
115			`always @ (posedge ainit or posedge wr_clk)`
116			`if (ainit)`
117			`Add_wr_gray <=0;`
118			`else`
119			`begin`
120			`Add_wr_gray[ADDR_WIDTH-1] <=Add_wr[ADDR_WIDTH-1];`
121			`for (i=ADDR_WIDTH-2;i>=0;i=i-1)`
122			`Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];`
123			`end`
124
125			`//��ַ��з�gray��.`
126
127			`always @ (posedge wr_clk or posedge ainit)`
128			`if (ainit)`
129			`Add_rd_gray_dl1 <=0;`
130			`else`
131			`Add_rd_gray_dl1 <=Add_rd_gray;`
132
133			`always @ (posedge wr_clk or posedge ainit)`
134			`if (ainit)`
135			`Add_rd_ungray =0;`
136			`else`
137			`begin`
138			`Add_rd_ungray[ADDR_WIDTH-1] =Add_rd_gray_dl1[ADDR_WIDTH-1];`
139			`for (i=ADDR_WIDTH-2;i>=0;i=i-1)`
140			`Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];`
141			`end`
142
143			`assign Add_wr_pluse=Add_wr+1;`
144
145
146			`/*`
147			`always @ (Add_wr_pluse or Add_rd_ungray)`
148			`if (Add_wr_pluse==Add_rd_ungray)`
149			`full =1;`
150			`else`
151			`full =0;`
152
153			`*/`
154			`always @ (posedge wr_clk or posedge ainit)`
155			`if (ainit)`
156			`full <=0;`
157			`else if(Add_wr_pluse==Add_rd_ungray&&wr_en)`
158			`full <=1;`
159			`else if(Add_wr!=Add_rd_ungray)`
160			`full <=0;`
161
162
163			`always @ (posedge wr_clk or posedge ainit)`
164			`if (ainit)`
165			`almost_full <=0;`
166			`else if (wr_count>=ALMOST_FULL_DEPTH)`
167			`almost_full <=1;`
168			`else`
169			`almost_full <=0;`
170
171			`always @ (posedge wr_clk or posedge ainit)`
172			`if (ainit)`
173			`Add_wr <=0;`
174			`else if (wr_en&&!full)`
175			`Add_wr <=Add_wr +1;`
176
177
178
179
180
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220
221			`//******************************************************************************`
222			`//read clock domain`
223			`//******************************************************************************`
224			`always @ (posedge rd_clk or posedge ainit)`
225			`if (ainit)`
226			`rd_ack <=0;`
227			`else if (rd_en&&!empty)`
228			`rd_ack <=1;`
229			`else`
230			`rd_ack <=0;`
231
232
233
234			`assign ff_used_rd =Add_wr_ungray-Add_rd;`
235			`assign rd_count =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];`
236			`assign Add_rd_pluse =Add_rd+1;`
237
238
239			`always @ (posedge rd_clk or posedge ainit)`
240			`if (ainit)`
241			`Add_rd <=0;`
242			`else if (rd_en&&!empty) //��EOP��Ͳ��ˡ�`
243			`Add_rd <=Add_rd + 1;`
244
245			`//��ַ��gray��任.`
246			`always @ (posedge ainit or posedge rd_clk)`
247			`if (ainit)`
248			`Add_rd_gray <=0;`
249			`else`
250			`begin`
251			`Add_rd_gray[ADDR_WIDTH-1] <=Add_rd[ADDR_WIDTH-1];`
252			`for (i=ADDR_WIDTH-2;i>=0;i=i-1)`
253			`Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];`
254			`end`
255			`/* Add_rd_gray <={ Add_rd[8],`
256			`Add_rd[8]^Add_rd[7],`
257			`Add_rd[7]^Add_rd[6],`
258			`Add_rd[6]^Add_rd[5],`
259			`Add_rd[5]^Add_rd[4],`
260			`Add_rd[4]^Add_rd[3],`
261			`Add_rd[3]^Add_rd[2],`
262			`Add_rd[2]^Add_rd[1],`
263			`Add_rd[1]^Add_rd[0]};`
264			`*/`
265			`//д��ַ��з�gray��.`
266
267			`always @ (posedge rd_clk or posedge ainit)`
268			`if (ainit)`
269			`Add_wr_gray_dl1 <=0;`
270			`else`
271			`Add_wr_gray_dl1 <=Add_wr_gray;`
272
273			`always @ (posedge rd_clk or posedge ainit)`
274			`if (ainit)`
275			`Add_wr_ungray =0;`
276			`else`
277			`begin`
278			`Add_wr_ungray[ADDR_WIDTH-1] =Add_wr_gray_dl1[ADDR_WIDTH-1];`
279			`for (i=ADDR_WIDTH-2;i>=0;i=i-1)`
280			`Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];`
281			`end`
282
283			`/* Add_wr_ungray <={`
284			`Add_wr_gray_dl1[8],`
285			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],`
286			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],`
287			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],`
288			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],`
289			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],`
290			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],`
291			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],`
292			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };`
293			`*/`
294			`//empty�źŲ��`
295			`/*`
296			`always @ (Add_rd or Add_wr_ungray)`
297			`if (Add_rd==Add_wr_ungray)`
298			`empty =1;`
299			`else`
300			`empty =0;`
301			`*/`
302			`always @ (posedge rd_clk or posedge ainit)`
303			`if (ainit)`
304			`empty <=1;`
305			`else if (Add_rd_pluse==Add_wr_ungray&&rd_en)`
306			`empty <=1;`
307			`else if (Add_rd!=Add_wr_ungray)`
308			`empty <=0;`
309
310
311
312			`//////////////////////////////////////////////////////`
313			`//instant need change for your own dpram`
314			`//////////////////////////////////////////////////////`
315			`duram #(`
316			`DATA_WIDTH,`
317			`ADDR_WIDTH,`
318			`BLK_RAM_TYPE,`
319			`DUAL_PORT_TYPE)`
320			`U_duram (`
321			`.data_a (din ),`
322			`.wren_a (wr_en ),`
323			`.address_a (Add_wr ),`
324			`.address_b (Add_rd ),`
325			`.clock_a (wr_clk ),`
326			`.clock_b (rd_clk ),`
327			`.q_b (dout ));`
328
329			`endmodule`