OpenCores
URL https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk

Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [trunk/] [bench/] [verilog/] [Phy_sim.v] - Blame information for rev 33

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 maverickis
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Phy_sim.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Jon Gao (gaojon@yahoo.com)                            ////
10
////                                                              ////
11
////                                                              ////
12
//////////////////////////////////////////////////////////////////////
13
////                                                              ////
14
//// Copyright (C) 2001 Authors                                   ////
15
////                                                              ////
16
//// This source file may be used and distributed without         ////
17
//// restriction provided that this copyright statement is not    ////
18
//// removed from the file and that any derivative work contains  ////
19
//// the original copyright notice and the associated disclaimer. ////
20
////                                                              ////
21
//// This source file is free software; you can redistribute it   ////
22
//// and/or modify it under the terms of the GNU Lesser General   ////
23
//// Public License as published by the Free Software Foundation; ////
24
//// either version 2.1 of the License, or (at your option) any   ////
25
//// later version.                                               ////
26
////                                                              ////
27
//// This source is distributed in the hope that it will be       ////
28
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
29
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
30
//// PURPOSE.  See the GNU Lesser General Public License for more ////
31
//// details.                                                     ////
32
////                                                              ////
33
//// You should have received a copy of the GNU Lesser General    ////
34
//// Public License along with this source; if not, download it   ////
35
//// from http://www.opencores.org/lgpl.shtml                     ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
//                                                                    
39
// CVS Revision History                                               
40
//                                                                    
41
// $Log: not supported by cvs2svn $
42 23 maverickis
// Revision 1.2  2006/01/19 14:07:50  maverickist
43
// verification is complete.
44
//
45 6 maverickis
// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
46
// no message
47
// 
48
 
49
`timescale 1ns/100ps
50
 
51
module Phy_sim (
52
input                   Gtx_clk                                 ,//used only in GMII mode
53
output                  Rx_clk                                  ,
54
output                  Tx_clk                                  ,//used only in MII mode
55
input                   Tx_er                                   ,
56
input                   Tx_en                                   ,
57
input   [7:0]    Txd                                             ,
58
output                  Rx_er                                   ,
59
output                  Rx_dv                                   ,
60
output  [7:0]    Rxd                                             ,
61
output                  Crs                                             ,
62
output                  Col                                             ,
63
input   [2:0]    Speed
64
);
65
//////////////////////////////////////////////////////////////////////
66
// this file used to simulate Phy.
67
// generate clk and loop the Tx data to Rx data
68
// full duplex mode can be verified on loop mode.
69
//////////////////////////////////////////////////////////////////////
70
//////////////////////////////////////////////////////////////////////
71
// internal signals
72
//////////////////////////////////////////////////////////////////////
73
reg                             Clk_25m                 ;//used for 100 Mbps mode
74
reg                             Clk_2_5m                ;//used for 10 Mbps mode
75 23 maverickis
//wire                  Rx_clk                  ;
76
//wire                  Tx_clk                  ;//used only in MII mode
77 6 maverickis
//////////////////////////////////////////////////////////////////////
78
always
79
        begin
80
        #20             Clk_25m=0;
81
        #20             Clk_25m=1;
82
        end
83
 
84
always
85
        begin
86
        #200    Clk_2_5m=0;
87
        #200    Clk_2_5m=1;
88
        end
89
 
90
assign  Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
91
assign  Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0;
92
 
93
assign  Rx_dv   =Tx_en  ;
94
assign  Rxd             =Txd    ;
95
assign  Rx_er   =0               ;
96
assign  Crs     =Tx_en  ;
97
assign  Col             =0               ;
98
 
99
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.