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maverickis |
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//// ////
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//// tb_top.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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module tb_top (
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);
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//******************************************************************************
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//internal signals
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//******************************************************************************
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//system signals
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input Reset ,
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input Clk_125M ,
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input Clk_user ,
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input Clk_reg ,
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//user interface
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output Rx_mac_ra ,
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input Rx_mac_rd ,
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output [31:0] Rx_mac_data ,
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output [1:0] Rx_mac_BE ,
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output Rx_mac_pa ,
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output Rx_mac_sop ,
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output Rx_mac_eop ,
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//user interface
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output Tx_mac_wa ,
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input Tx_mac_wr ,
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input [31:0] Tx_mac_data ,
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input [1:0] Tx_mac_BE ,//big endian
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input Tx_mac_sop ,
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input Tx_mac_eop ,
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//Phy interface
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//Phy interface
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output Gtx_clk ,//used only in GMII mode
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input Rx_clk ,
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input Tx_clk ,//used only in MII mode
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output Tx_er ,
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output Tx_en ,
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output [7:0] Txd ,
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input Rx_er ,
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input Rx_dv ,
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input [7:0] Rxd ,
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input Crs ,
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input Col ,
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//Tx host interface
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input [4:0] Tx_Hwmark ,
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input [4:0] Tx_Lwmark ,
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input pause_frame_send_en ,
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input [15:0] pause_quanta_set ,
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input MAC_tx_add_en ,
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input FullDuplex ,
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input [3:0] MaxRetry ,
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input [5:0] IFGset ,
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input [7:0] MAC_tx_add_prom_data ,
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input [2:0] MAC_tx_add_prom_add ,
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input MAC_tx_add_prom_wr ,
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input tx_pause_en ,
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input xoff_cpu ,
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input xon_cpu ,
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//Rx host interface
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input MAC_rx_add_chk_en ,
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input [7:0] MAC_rx_add_prom_data ,
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input [2:0] MAC_rx_add_prom_add ,
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input MAC_rx_add_prom_wr ,
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input broadcast_filter_en ,
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input [15:0] broadcast_MAX ,
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input RX_APPEND_CRC ,
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input CRC_chk_en ,
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input [5:0] RX_IFG_SET ,
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input [15:0] RX_MAX_LENGTH ,// 1518
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input [6:0] RX_MIN_LENGTH ,// 64
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//RMON host interface
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input [5:0] CPU_rd_addr ,
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input CPU_rd_apply ,
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output CPU_rd_grant ,
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output [31:0] CPU_rd_dout ,
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//Phy int host interface
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input Line_loop_en ,
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input [2:0] Speed ,
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//MII to CPU
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input [7:0] Divider ,// Divider for the host clock
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input [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
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input [4:0] Rgad ,// Register Address (within the PHY)
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input [4:0] Fiad ,// PHY Address
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input NoPre ,// No Preamble (no 32-bit preamble)
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input WCtrlData ,// Write Control Data operation
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input RStat ,// Read Status operation
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input ScanStat ,// Scan Status operation
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output Busy ,// Busy Signal
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output LinkFail ,// Link Integrity Signal
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output Nvalid ,// Invalid Status (qualifier for the valid scan result)
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output [15:0] Prsd ,// Read Status Data (data read from the PHY)
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output WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
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output RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
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output UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data
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//MII interface signals
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inout Mdio ,// MII Management Data In
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output Mdc ,// MII Management Data Clock
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//******************************************************************************
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//internal signals
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//******************************************************************************
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MAC_top U_MAC_top(
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.//system signals (//system signals ),
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.Reset (Reset ),
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.Clk_125M (Clk_125M ),
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.Clk_user (Clk_user ),
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.Clk_reg (Clk_reg ),
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.//user interface (//user interface ),
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.Rx_mac_ra (Rx_mac_ra ),
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.Rx_mac_rd (Rx_mac_rd ),
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.Rx_mac_data (Rx_mac_data ),
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.Rx_mac_BE (Rx_mac_BE ),
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.Rx_mac_pa (Rx_mac_pa ),
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.Rx_mac_sop (Rx_mac_sop ),
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.Rx_mac_eop (Rx_mac_eop ),
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.//user interface (//user interface ),
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.Tx_mac_wa (Tx_mac_wa ),
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.Tx_mac_wr (Tx_mac_wr ),
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.Tx_mac_data (Tx_mac_data ),
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.Tx_mac_BE (Tx_mac_BE ),
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.Tx_mac_sop (Tx_mac_sop ),
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.Tx_mac_eop (Tx_mac_eop ),
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.//Phy interface (//Phy interface ),
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.//Phy interface (//Phy interface ),
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.Gtx_clk (Gtx_clk ),
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.Rx_clk (Rx_clk ),
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.Tx_clk (Tx_clk ),
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.Tx_er (Tx_er ),
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.Tx_en (Tx_en ),
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.Txd (Txd ),
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.Rx_er (Rx_er ),
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.Rx_dv (Rx_dv ),
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.Rxd (Rxd ),
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.Crs (Crs ),
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.Col (Col ),
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.//Tx host interface (//Tx host interface ),
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.Tx_Hwmark (Tx_Hwmark ),
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.Tx_Lwmark (Tx_Lwmark ),
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.pause_frame_send_en (pause_frame_send_en ),
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.pause_quanta_set (pause_quanta_set ),
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.MAC_tx_add_en (MAC_tx_add_en ),
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.FullDuplex (FullDuplex ),
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.MaxRetry (MaxRetry ),
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.IFGset (IFGset ),
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.MAC_tx_add_prom_data (MAC_tx_add_prom_data ),
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.MAC_tx_add_prom_add (MAC_tx_add_prom_add ),
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.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ),
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.tx_pause_en (tx_pause_en ),
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.xoff_cpu (xoff_cpu ),
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.xon_cpu (xon_cpu ),
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.//Rx host interface (//Rx host interface ),
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.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),
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.MAC_rx_add_prom_data (MAC_rx_add_prom_data ),
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.MAC_rx_add_prom_add (MAC_rx_add_prom_add ),
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.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ),
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.broadcast_filter_en (broadcast_filter_en ),
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.broadcast_MAX (broadcast_MAX ),
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.RX_APPEND_CRC (RX_APPEND_CRC ),
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.CRC_chk_en (CRC_chk_en ),
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.RX_IFG_SET (RX_IFG_SET ),
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.RX_MAX_LENGTH (RX_MAX_LENGTH ),
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.RX_MIN_LENGTH (RX_MIN_LENGTH ),
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.//RMON host interface (//RMON host interface ),
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.CPU_rd_addr (CPU_rd_addr ),
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.CPU_rd_apply (CPU_rd_apply ),
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.CPU_rd_grant (CPU_rd_grant ),
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.CPU_rd_dout (CPU_rd_dout ),
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.//Phy int host interface (//Phy int host interface ),
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.Line_loop_en (Line_loop_en ),
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.Speed (Speed ),
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.//MII to CPU (//MII to CPU ),
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.Divider (Divider ),
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.CtrlData (CtrlData ),
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.Rgad (Rgad ),
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.Fiad (Fiad ),
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.NoPre (NoPre ),
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.WCtrlData (WCtrlData ),
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.RStat (RStat ),
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.ScanStat (ScanStat ),
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.Busy (Busy ),
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.LinkFail (LinkFail ),
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.Nvalid (Nvalid ),
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.Prsd (Prsd ),
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.WCtrlDataStart (WCtrlDataStart ),
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.RStatStart (RStatStart ),
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.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ),
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.//MII interface signals (//MII interface signals ),
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.Mdio (Mdio ),
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.Mdc (Mdc )
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);
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endmodule
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