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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [Clk_ctrl.v] - Blame information for rev 35

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Clk_ctrl.v                                                  ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Jon Gao (gaojon@yahoo.com)                            ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//                                                                    
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// CVS Revision History                                               
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//                                                                    
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// $Log: not supported by cvs2svn $
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// Revision 1.2  2005/12/16 06:44:13  Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
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// no message
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// 
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module Clk_ctrl(
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Reset           ,
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Clk_125M        ,
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//host interface,
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Speed           ,
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//Phy interface ,
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Gtx_clk         ,
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Rx_clk          ,
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Tx_clk          ,
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//interface clk ,
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MAC_tx_clk      ,
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MAC_rx_clk      ,
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MAC_tx_clk_div  ,
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MAC_rx_clk_div
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);
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input           Reset           ;
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input           Clk_125M        ;
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                //host interface
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input   [2:0]   Speed           ;
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                //Phy interface         
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output          Gtx_clk         ;//used only in GMII mode
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input           Rx_clk          ;
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input           Tx_clk          ;//used only in MII mode
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                //interface clk signals
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output          MAC_tx_clk      ;
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output          MAC_rx_clk      ;
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output          MAC_tx_clk_div  ;
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output          MAC_rx_clk_div  ;
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//******************************************************************************
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//internal signals                                                              
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//******************************************************************************
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wire            Rx_clk_div2 ;
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wire            Tx_clk_div2 ;
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//******************************************************************************
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//                                                              
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//******************************************************************************
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assign Gtx_clk      =Clk_125M                   ;
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assign MAC_rx_clk   =Rx_clk                     ;
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CLK_DIV2 U_0_CLK_DIV2(
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.Reset          (Reset          ),
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.IN             (Rx_clk         ),
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.OUT            (Rx_clk_div2    )
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);
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CLK_DIV2 U_1_CLK_DIV2(
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.Reset          (Reset          ),
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.IN             (Tx_clk         ),
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.OUT            (Tx_clk_div2    )
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);
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CLK_SWITCH U_0_CLK_SWITCH(
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.IN_0           (Rx_clk_div2    ),
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.IN_1           (Rx_clk         ),
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.SW             (Speed[2]       ),
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.OUT            (MAC_rx_clk_div )
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);
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CLK_SWITCH U_1_CLK_SWITCH(
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.IN_0           (Tx_clk         ),
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.IN_1           (Clk_125M       ),
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.SW             (Speed[2]       ),
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.OUT            (MAC_tx_clk     )
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);
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CLK_SWITCH U_2_CLK_SWITCH(
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.IN_0           (Tx_clk_div2    ),
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.IN_1           (Clk_125M       ),
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.SW             (Speed[2]       ),
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.OUT            (MAC_tx_clk_div )
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);
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endmodule

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