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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_rx/] [CRC_chk.v] - Blame information for rev 33

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  CRC_chk.v                                                   ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Jon Gao (gaojon@yahoo.com)                            ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.2  2005/12/16 06:44:16  Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
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// no message
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//
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module CRC_chk(
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Reset       ,
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Clk         ,
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CRC_data    ,
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CRC_init    ,
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CRC_en      ,
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//From CPU
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CRC_chk_en  ,
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CRC_err
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);
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input       Reset       ;
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input       Clk         ;
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input[7:0]  CRC_data    ;
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input       CRC_init    ;
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input       CRC_en      ;
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            //From CPU
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input       CRC_chk_en  ;
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output      CRC_err     ;
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//******************************************************************************
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//internal signals
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//******************************************************************************
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reg [31:0]  CRC_reg;
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wire[31:0]  Next_CRC;
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//******************************************************************************
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//input data width is 8bit, and the first bit is bit[0]
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function[31:0]  NextCRC;
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    input[7:0]      D;
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    input[31:0]     C;
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    reg[31:0]       NewCRC;
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    begin
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    NewCRC[0]=C[24]^C[30]^D[1]^D[7];
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    NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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    NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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    NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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    NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
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    NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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    NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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    NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
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    NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
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    NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
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    NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
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    NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
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    NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
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    NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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    NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
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    NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
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    NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
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    NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
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    NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
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    NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
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    NewCRC[20]=C[12]^C[28]^D[3];
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    NewCRC[21]=C[13]^C[29]^D[2];
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    NewCRC[22]=C[14]^C[24]^D[7];
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    NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
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    NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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    NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
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    NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
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    NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
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    NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
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    NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
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    NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
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    NewCRC[31]=C[23]^C[29]^D[2];
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    NextCRC=NewCRC;
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    end
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        endfunction
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always @ (posedge Clk or posedge Reset)
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    if (Reset)
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        CRC_reg     <=32'hffffffff;
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    else if (CRC_init)
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        CRC_reg     <=32'hffffffff;
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    else if (CRC_en)
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        CRC_reg     <=NextCRC(CRC_data,CRC_reg);
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assign  CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b);
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endmodule

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