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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_rx_FF.v                                                 ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.4  2006/05/28 05:09:20  maverickist
// no message
//
// Revision 1.3  2006/01/19 14:07:54  maverickist
// verification is complete.
//
// Revision 1.3  2005/12/16 06:44:16  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
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// Revision 1.2  2005/12/13 12:15:37  Administrator
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//
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//                                           
 
module MAC_rx_FF (
Reset       ,
Clk_MAC     ,
Clk_SYS     ,
//MAC_rx_ctrl interface                                                                                                                                          
Fifo_data       ,
Fifo_data_en    ,
Fifo_full       ,
Fifo_data_err   ,
Fifo_data_end   ,
//CPU
Rx_Hwmark,
Rx_Lwmark,
RX_APPEND_CRC,
//user interface                                                                                                                                               
Rx_mac_ra   ,
Rx_mac_rd   ,
Rx_mac_data ,
Rx_mac_BE   ,
Rx_mac_sop  ,
Rx_mac_pa,
Rx_mac_eop
);
input           Reset       ;
input           Clk_MAC     ;
input           Clk_SYS     ;
                //MAC_rx_ctrl interface 
input   [7:0]   Fifo_data       ;
input           Fifo_data_en    ;
output          Fifo_full       ;
input           Fifo_data_err   ;
input           Fifo_data_end   ;
                //CPU
input           RX_APPEND_CRC       ;
input   [4:0]   Rx_Hwmark           ;
input   [4:0]   Rx_Lwmark           ;
                //user interface 
output          Rx_mac_ra   ;//
input           Rx_mac_rd   ;
output  [31:0]  Rx_mac_data ;
output  [1:0]   Rx_mac_BE   ;
output          Rx_mac_pa   ;
output          Rx_mac_sop  ;
output          Rx_mac_eop  ;
 
//******************************************************************************
//internal signals                                                              
//******************************************************************************
parameter       State_byte3     =4'd0;
parameter       State_byte2     =4'd1;
parameter       State_byte1     =4'd2;
parameter       State_byte0     =4'd3;
parameter       State_be0       =4'd4;
parameter       State_be3       =4'd5;
parameter       State_be2       =4'd6;
parameter       State_be1       =4'd7;
parameter       State_err_end   =4'd8;
parameter       State_idle      =4'd9;
 
parameter       SYS_read        =3'd0;
parameter       SYS_pause       =3'd1;
parameter       SYS_wait_end    =3'd2;
parameter       SYS_idle        =3'd3;
parameter       FF_emtpy_err    =3'd4;
 
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr_ungray;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr_gray;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr_gray_dl1;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr_reg;
 
reg [`MAC_TX_FF_DEPTH-1:0]       Add_rd;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_rd_gray;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_rd_gray_dl1;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_rd_ungray;
reg [35:0]      Din;
reg [35:0]      Din_tmp;
reg [35:0]      Din_tmp_reg;
wire[35:0]      Dout;
reg             Wr_en;
reg             Wr_en_tmp;
reg             Wr_en_ptr;
wire[`MAC_TX_FF_DEPTH-1:0]       Add_wr_pluse;
wire[`MAC_TX_FF_DEPTH-1:0]       Add_wr_pluse4;
wire[`MAC_TX_FF_DEPTH-1:0]       Add_wr_pluse3;
wire[`MAC_TX_FF_DEPTH-1:0]       Add_wr_pluse2;
reg             Full;
reg             Almost_full;
reg             Empty /* synthesis syn_keep=1 */;
reg [3:0]       Current_state /* synthesis syn_keep=1 */;
reg [3:0]       Next_state;
reg [7:0]       Fifo_data_byte0;
reg [7:0]       Fifo_data_byte1;
reg [7:0]       Fifo_data_byte2;
reg [7:0]       Fifo_data_byte3;
reg             Fifo_data_en_dl1;
reg [7:0]       Fifo_data_dl1;
reg             Rx_mac_sop_tmp  ;
reg             Rx_mac_sop  ;
reg             Rx_mac_ra   ;
reg             Rx_mac_pa   ;
 
 
 
reg [2:0]       Current_state_SYS /* synthesis syn_keep=1 */;
reg [2:0]       Next_state_SYS ;
reg [5:0]       Packet_number_inFF /* synthesis syn_keep=1 */;
reg             Packet_number_sub ;
wire            Packet_number_add_edge;
reg             Packet_number_add_dl1;
reg             Packet_number_add_dl2;
reg             Packet_number_add ;
reg             Packet_number_add_tmp    ;
reg             Packet_number_add_tmp_dl1;
reg             Packet_number_add_tmp_dl2;
 
reg             Rx_mac_sop_tmp_dl1;
reg [35:0]      Dout_dl1;
reg [4:0]       Fifo_data_count;
reg             Rx_mac_pa_tmp       ;
reg             Add_wr_jump_tmp     ;
reg             Add_wr_jump_tmp_pl1 ;
reg             Add_wr_jump         ;
reg             Add_wr_jump_rd_pl1  ;
reg [4:0]       Rx_Hwmark_pl        ;
reg [4:0]       Rx_Lwmark_pl        ;
integer         i                   ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************    
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Current_state   <=State_idle;
    else
        Current_state   <=Next_state;
 
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
    case (Current_state)
        State_idle:
                if (Fifo_data_en)
                    Next_state  =State_byte3;
                else
                    Next_state  =Current_state;
        State_byte3:
                if (Fifo_data_en)
                    Next_state  =State_byte2;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be1;
                else
                    Next_state  =Current_state;
        State_byte2:
                if (Fifo_data_en)
                    Next_state  =State_byte1;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be2;
                else
                    Next_state  =Current_state;
        State_byte1:
                if (Fifo_data_en)
                    Next_state  =State_byte0;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be3;
                else
                    Next_state  =Current_state;
        State_byte0:
                if (Fifo_data_en)
                    Next_state  =State_byte3;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be0;
                else
                    Next_state  =Current_state;
        State_be1:
                Next_state      =State_idle;
        State_be2:
                Next_state      =State_idle;
        State_be3:
                Next_state      =State_idle;
        State_be0:
                Next_state      =State_idle;
        State_err_end:
                Next_state      =State_idle;
        default:
                Next_state      =State_idle;
    endcase
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_wr_reg      <=0;
    else if (Current_state==State_idle)
        Add_wr_reg      <=Add_wr;
 
//
 
 
always @ (posedge Reset or posedge Clk_MAC)
    if (Reset)
        Add_wr_gray         <=0;
    else
                begin
                Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                Add_wr_gray[i]                  <=Add_wr[i+1]^Add_wr[i];
                end
 
//
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_rd_gray_dl1         <=0;
    else
        Add_rd_gray_dl1         <=Add_rd_gray;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_rd_ungray       =0;
    else
                begin
                Add_rd_ungray[`MAC_RX_FF_DEPTH-1]       =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                        Add_rd_ungray[i]        =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
                end
assign          Add_wr_pluse=Add_wr+1;
assign          Add_wr_pluse4=Add_wr+4;
assign          Add_wr_pluse3=Add_wr+3;
assign          Add_wr_pluse2=Add_wr+2;
 
 
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Full    <=0;
    else if (Add_wr_pluse==Add_rd_ungray)
        Full    <=1;
    else
        Full    <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Almost_full     <=0;
        else if (Add_wr_pluse4==Add_rd_ungray||
                 Add_wr_pluse3==Add_rd_ungray||
                 Add_wr_pluse2==Add_rd_ungray||
                 Add_wr_pluse==Add_rd_ungray
                 )
                Almost_full     <=1;
        else
                Almost_full     <=0;
 
assign          Fifo_full =Almost_full;
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_wr  <=0;
    else if (Current_state==State_err_end)
        Add_wr  <=Add_wr_reg;
    else if (Wr_en&&!Full)
        Add_wr  <=Add_wr +1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump_tmp <=0;
        else if (Current_state==State_err_end)
            Add_wr_jump_tmp <=1;
        else
            Add_wr_jump_tmp <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump_tmp_pl1 <=0;
        else
            Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump <=0;
        else if (Current_state==State_err_end)
            Add_wr_jump <=1;
        else if (Add_wr_jump_tmp_pl1)
            Add_wr_jump <=0;
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_en_dl1    <=0;
    else
        Fifo_data_en_dl1    <=Fifo_data_en;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_dl1   <=0;
    else
        Fifo_data_dl1   <=Fifo_data;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte3     <=0;
    else if (Current_state==State_byte3&&Fifo_data_en_dl1)
        Fifo_data_byte3     <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte2     <=0;
    else if (Current_state==State_byte2&&Fifo_data_en_dl1)
        Fifo_data_byte2     <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte1     <=0;
    else if (Current_state==State_byte1&&Fifo_data_en_dl1)
        Fifo_data_byte1     <=Fifo_data_dl1;
 
always @ (* )
    case (Current_state)
        State_be0:
            Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
        State_be1:
            Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
        State_be2:
            Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
        State_be3:
            Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
        default:
            Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
    endcase
 
always @ (*)
    if (Current_state==State_be0||Current_state==State_be1||
       Current_state==State_be2||Current_state==State_be3||
      (Current_state==State_byte0&&Fifo_data_en))
        Wr_en_tmp   =1;
    else
        Wr_en_tmp   =0;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Din_tmp_reg <=0;
    else if(Wr_en_tmp)
        Din_tmp_reg <=Din_tmp;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Wr_en_ptr   <=0;
    else if(Current_state==State_idle)
        Wr_en_ptr   <=0;
    else if(Wr_en_tmp)
        Wr_en_ptr   <=1;
 
//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Wr_en           <=0;
        Din             <=0;
        end
    else if(RX_APPEND_CRC)
        begin
        Wr_en           <=Wr_en_tmp;
        Din             <=Din_tmp;
        end
    else
        begin
        Wr_en           <=Wr_en_tmp&&Wr_en_ptr;
        Din             <={Din_tmp[35:32],Din_tmp_reg[31:0]};
        end
 
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add_tmp   <=0;
    else if (Current_state==State_be0||Current_state==State_be1||
             Current_state==State_be2||Current_state==State_be3)
        Packet_number_add_tmp   <=1;
    else
        Packet_number_add_tmp   <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_tmp_dl1   <=0;
        Packet_number_add_tmp_dl2   <=0;
        end
    else
        begin
        Packet_number_add_tmp_dl1   <=Packet_number_add_tmp;
        Packet_number_add_tmp_dl2   <=Packet_number_add_tmp_dl1;
        end
 
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.       
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles       
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add   <=0;
    else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
        Packet_number_add   <=1;
    else
        Packet_number_add   <=0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Current_state_SYS   <=SYS_idle;
    else
        Current_state_SYS   <=Next_state_SYS;
 
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
    case (Current_state_SYS)
        SYS_idle:
                        if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
                Next_state_SYS  =SYS_read;
                    else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
                        Next_state_SYS  =FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_read:
            if (!Rx_mac_rd)
                Next_state_SYS  =SYS_pause;
            else if (Dout[35])
                Next_state_SYS  =SYS_wait_end;
            else if (Empty)
                Next_state_SYS  =FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_pause:
            if (Rx_mac_rd)
                Next_state_SYS  =SYS_read;
            else
                Next_state_SYS  =Current_state_SYS;
        FF_emtpy_err:
            if (!Empty)
                Next_state_SYS  =SYS_read;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_wait_end:
            if (!Rx_mac_rd)
                Next_state_SYS  =SYS_idle;
            else
                Next_state_SYS  =Current_state_SYS;
        default:
                Next_state_SYS  =SYS_idle;
    endcase
 
 
//gen Rx_mac_ra 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_dl1   <=0;
        Packet_number_add_dl2   <=0;
        end
    else
        begin
        Packet_number_add_dl1   <=Packet_number_add;
        Packet_number_add_dl2   <=Packet_number_add_dl1;
        end
assign  Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
 
always @ (Current_state_SYS or Next_state_SYS)
    if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
        Packet_number_sub       =1;
    else
        Packet_number_sub       =0;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Packet_number_inFF      <=0;
    else if (Packet_number_add_edge&&!Packet_number_sub)
        Packet_number_inFF      <=Packet_number_inFF + 1;
        else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
        Packet_number_inFF      <=Packet_number_inFF - 1;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Fifo_data_count     <=0;
    else
        Fifo_data_count     <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Rx_Hwmark_pl        <=0;
        Rx_Lwmark_pl        <=0;
        end
    else
        begin
        Rx_Hwmark_pl        <=Rx_Hwmark;
        Rx_Lwmark_pl        <=Rx_Lwmark;
        end
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
        Rx_mac_ra   <=1;
 
 
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_rd      <=0;
    else if (Current_state_SYS==SYS_read&&!Dout[35])
        Add_rd      <=Add_rd + 1;
 
//
always @ (posedge Reset or posedge Clk_SYS)
    if (Reset)
        Add_rd_gray         <=0;
    else
                begin
                Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                Add_rd_gray[i]                  <=Add_rd[i+1]^Add_rd[i];
                end
//
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_gray_dl1     <=0;
    else
        Add_wr_gray_dl1     <=Add_wr_gray;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_jump_rd_pl1  <=0;
    else
        Add_wr_jump_rd_pl1  <=Add_wr_jump;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_ungray       =0;
    else if (!Add_wr_jump_rd_pl1)
                begin
                Add_wr_ungray[`MAC_RX_FF_DEPTH-1]       =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                        Add_wr_ungray[i]        =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
                end
//empty signal gen  
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Empty   <=1;
    else if (Add_rd==Add_wr_ungray)
        Empty   <=1;
    else
        Empty   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Dout_dl1    <=0;
    else
        Dout_dl1    <=Dout;
 
assign  Rx_mac_data     =Dout_dl1[31:0];
assign  Rx_mac_BE       =Dout_dl1[33:32];
assign  Rx_mac_eop      =Dout_dl1[35];
 
//aligned to Addr_rd 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_pa_tmp   <=0;
    else if (Current_state_SYS==SYS_read&&!Dout[35])
        Rx_mac_pa_tmp   <=1;
    else
        Rx_mac_pa_tmp   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_pa   <=0;
    else
        Rx_mac_pa   <=Rx_mac_pa_tmp;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_sop_tmp      <=0;
    else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
        Rx_mac_sop_tmp      <=1;
    else
        Rx_mac_sop_tmp      <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Rx_mac_sop_tmp_dl1  <=0;
        Rx_mac_sop          <=0;
        end
    else
        begin
        Rx_mac_sop_tmp_dl1  <=Rx_mac_sop_tmp;
        Rx_mac_sop          <=Rx_mac_sop_tmp_dl1;
        end
 
 
 
//******************************************************************************
 
duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
.data_a         (Din        ),
.wren_a         (Wr_en      ),
.address_a      (Add_wr     ),
.address_b      (Add_rd     ),
.clock_a        (Clk_MAC    ),
.clock_b        (Clk_SYS    ),
.q_b            (Dout       ));
 
endmodule
 
 
 
 
 

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_rx_FF.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9	7	maverickis	`//// - Jon Gao (gaojon@yahoo.com) ////`
10	5	maverickis	`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41	6	maverickis	`// $Log: not supported by cvs2svn $`
42	19	maverickis	`// Revision 1.4 2006/05/28 05:09:20 maverickist`
43			`// no message`
44			`//`
45	18	maverickis	`// Revision 1.3 2006/01/19 14:07:54 maverickist`
46			`// verification is complete.`
47			`//`
48	7	maverickis	`// Revision 1.3 2005/12/16 06:44:16 Administrator`
49			`// replaced tab with space.`
50			`// passed 9.6k length frame test.`
51	6	maverickis	`//`
52	7	maverickis	`// Revision 1.2 2005/12/13 12:15:37 Administrator`
53			`// no message`
54			`//`
55	6	maverickis	`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
56			`// no message`
57			`//`
58	5	maverickis
59			`module MAC_rx_FF (`
60	7	maverickis	`Reset ,`
61			`Clk_MAC ,`
62			`Clk_SYS ,`
63	5	maverickis	`//MAC_rx_ctrl interface`
64	7	maverickis	`Fifo_data ,`
65			`Fifo_data_en ,`
66			`Fifo_full ,`
67			`Fifo_data_err ,`
68			`Fifo_data_end ,`
69	5	maverickis	`//CPU`
70	7	maverickis	`Rx_Hwmark,`
71			`Rx_Lwmark,`
72	5	maverickis	`RX_APPEND_CRC,`
73			`//user interface`
74	7	maverickis	`Rx_mac_ra ,`
75			`Rx_mac_rd ,`
76			`Rx_mac_data ,`
77			`Rx_mac_BE ,`
78			`Rx_mac_sop ,`
79	5	maverickis	`Rx_mac_pa,`
80	7	maverickis	`Rx_mac_eop`
81	5	maverickis	`);`
82	7	maverickis	`input Reset ;`
83			`input Clk_MAC ;`
84			`input Clk_SYS ;`
85			`//MAC_rx_ctrl interface`
86			`input [7:0] Fifo_data ;`
87			`input Fifo_data_en ;`
88			`output Fifo_full ;`
89			`input Fifo_data_err ;`
90			`input Fifo_data_end ;`
91			`//CPU`
92			`input RX_APPEND_CRC ;`
93			`input [4:0] Rx_Hwmark ;`
94			`input [4:0] Rx_Lwmark ;`
95			`//user interface`
96			`output Rx_mac_ra ;//`
97			`input Rx_mac_rd ;`
98			`output [31:0] Rx_mac_data ;`
99			`output [1:0] Rx_mac_BE ;`
100			`output Rx_mac_pa ;`
101			`output Rx_mac_sop ;`
102			`output Rx_mac_eop ;`
103	5	maverickis
104			`//******************************************************************************`
105			`//internal signals`
106			`//******************************************************************************`
107	7	maverickis	`parameter State_byte3 =4'd0;`
108			`parameter State_byte2 =4'd1;`
109			`parameter State_byte1 =4'd2;`
110			`parameter State_byte0 =4'd3;`
111			`parameter State_be0 =4'd4;`
112			`parameter State_be3 =4'd5;`
113			`parameter State_be2 =4'd6;`
114			`parameter State_be1 =4'd7;`
115			`parameter State_err_end =4'd8;`
116			`parameter State_idle =4'd9;`
117	5	maverickis
118	7	maverickis	`parameter SYS_read =3'd0;`
119			`parameter SYS_pause =3'd1;`
120			`parameter SYS_wait_end =3'd2;`
121			`parameter SYS_idle =3'd3;`
122			`parameter FF_emtpy_err =3'd4;`
123	5	maverickis
124	7	maverickis	reg [`MAC_TX_FF_DEPTH-1:0] Add_wr;
125			reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_ungray;
126			reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_gray;
127			reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_gray_dl1;
128			reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_reg;
129	5	maverickis
130	7	maverickis	reg [`MAC_TX_FF_DEPTH-1:0] Add_rd;
131			reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_gray;
132			reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_gray_dl1;
133			reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_ungray;
134			`reg [35:0] Din;`
135			`reg [35:0] Din_tmp;`
136			`reg [35:0] Din_tmp_reg;`
137			`wire[35:0] Dout;`
138			`reg Wr_en;`
139			`reg Wr_en_tmp;`
140			`reg Wr_en_ptr;`
141			wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse;
142	19	maverickis	wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse4;
143			wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse3;
144			wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse2;
145	7	maverickis	`reg Full;`
146	19	maverickis	`reg Almost_full;`
147	7	maverickis	`reg Empty /* synthesis syn_keep=1 */;`
148			`reg [3:0] Current_state /* synthesis syn_keep=1 */;`
149			`reg [3:0] Next_state;`
150			`reg [7:0] Fifo_data_byte0;`
151			`reg [7:0] Fifo_data_byte1;`
152			`reg [7:0] Fifo_data_byte2;`
153			`reg [7:0] Fifo_data_byte3;`
154			`reg Fifo_data_en_dl1;`
155			`reg [7:0] Fifo_data_dl1;`
156			`reg Rx_mac_sop_tmp ;`
157			`reg Rx_mac_sop ;`
158			`reg Rx_mac_ra ;`
159			`reg Rx_mac_pa ;`
160	5	maverickis
161
162
163	7	maverickis	`reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;`
164			`reg [2:0] Next_state_SYS ;`
165			`reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;`
166			`reg Packet_number_sub ;`
167			`wire Packet_number_add_edge;`
168			`reg Packet_number_add_dl1;`
169			`reg Packet_number_add_dl2;`
170			`reg Packet_number_add ;`
171			`reg Packet_number_add_tmp ;`
172			`reg Packet_number_add_tmp_dl1;`
173			`reg Packet_number_add_tmp_dl2;`
174	5	maverickis
175	7	maverickis	`reg Rx_mac_sop_tmp_dl1;`
176			`reg [35:0] Dout_dl1;`
177			`reg [4:0] Fifo_data_count;`
178			`reg Rx_mac_pa_tmp ;`
179	19	maverickis	`reg Add_wr_jump_tmp ;`
180			`reg Add_wr_jump_tmp_pl1 ;`
181			`reg Add_wr_jump ;`
182			`reg Add_wr_jump_rd_pl1 ;`
183	18	maverickis	`reg [4:0] Rx_Hwmark_pl ;`
184			`reg [4:0] Rx_Lwmark_pl ;`
185	7	maverickis	`integer i ;`
186	5	maverickis	`//******************************************************************************`
187			`//domain Clk_MAC,write data to dprom.a-port for write`
188	7	maverickis	`//******************************************************************************`
189	5	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
190	7	maverickis	`if (Reset)`
191			`Current_state <=State_idle;`
192			`else`
193			`Current_state <=Next_state;`
194
195	5	maverickis	`always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)`
196	7	maverickis	`case (Current_state)`
197			`State_idle:`
198			`if (Fifo_data_en)`
199			`Next_state =State_byte3;`
200			`else`
201			`Next_state =Current_state;`
202			`State_byte3:`
203			`if (Fifo_data_en)`
204			`Next_state =State_byte2;`
205			`else if (Fifo_data_err)`
206			`Next_state =State_err_end;`
207			`else if (Fifo_data_end)`
208			`Next_state =State_be1;`
209			`else`
210			`Next_state =Current_state;`
211			`State_byte2:`
212			`if (Fifo_data_en)`
213			`Next_state =State_byte1;`
214			`else if (Fifo_data_err)`
215			`Next_state =State_err_end;`
216			`else if (Fifo_data_end)`
217			`Next_state =State_be2;`
218			`else`
219			`Next_state =Current_state;`
220			`State_byte1:`
221			`if (Fifo_data_en)`
222			`Next_state =State_byte0;`
223			`else if (Fifo_data_err)`
224			`Next_state =State_err_end;`
225			`else if (Fifo_data_end)`
226			`Next_state =State_be3;`
227			`else`
228			`Next_state =Current_state;`
229			`State_byte0:`
230			`if (Fifo_data_en)`
231			`Next_state =State_byte3;`
232			`else if (Fifo_data_err)`
233			`Next_state =State_err_end;`
234			`else if (Fifo_data_end)`
235			`Next_state =State_be0;`
236			`else`
237			`Next_state =Current_state;`
238			`State_be1:`
239			`Next_state =State_idle;`
240			`State_be2:`
241			`Next_state =State_idle;`
242			`State_be3:`
243			`Next_state =State_idle;`
244			`State_be0:`
245			`Next_state =State_idle;`
246			`State_err_end:`
247			`Next_state =State_idle;`
248			`default:`
249			`Next_state =State_idle;`
250			`endcase`
251	5	maverickis
252			`//`
253			`always @ (posedge Clk_MAC or posedge Reset)`
254	7	maverickis	`if (Reset)`
255			`Add_wr_reg <=0;`
256			`else if (Current_state==State_idle)`
257			`Add_wr_reg <=Add_wr;`
258
259	5	maverickis	`//`
260
261	7	maverickis
262	5	maverickis	`always @ (posedge Reset or posedge Clk_MAC)`
263	7	maverickis	`if (Reset)`
264			`Add_wr_gray <=0;`
265			`else`
266			`begin`
267			Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
268			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
269			`Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];`
270			`end`
271	5	maverickis
272			`//`
273
274			`always @ (posedge Clk_MAC or posedge Reset)`
275	7	maverickis	`if (Reset)`
276			`Add_rd_gray_dl1 <=0;`
277			`else`
278			`Add_rd_gray_dl1 <=Add_rd_gray;`
279
280	5	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
281	7	maverickis	`if (Reset)`
282			`Add_rd_ungray =0;`
283			`else`
284			`begin`
285			Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
286			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
287			`Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];`
288			`end`
289			`assign Add_wr_pluse=Add_wr+1;`
290	19	maverickis	`assign Add_wr_pluse4=Add_wr+4;`
291			`assign Add_wr_pluse3=Add_wr+3;`
292			`assign Add_wr_pluse2=Add_wr+2;`
293	5	maverickis
294	19	maverickis
295
296	5	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
297	7	maverickis	`if (Reset)`
298			`Full <=0;`
299			`else if (Add_wr_pluse==Add_rd_ungray)`
300			`Full <=1;`
301			`else`
302			`Full <=0;`
303	5	maverickis
304	19	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
305			`if (Reset)`
306			`Almost_full <=0;`
307			`else if (Add_wr_pluse4==Add_rd_ungray\|\|`
308			`Add_wr_pluse3==Add_rd_ungray\|\|`
309			`Add_wr_pluse2==Add_rd_ungray\|\|`
310			`Add_wr_pluse==Add_rd_ungray`
311			`)`
312			`Almost_full <=1;`
313			`else`
314			`Almost_full <=0;`
315	5	maverickis
316	19	maverickis	`assign Fifo_full =Almost_full;`
317
318	5	maverickis	`//`
319			`always @ (posedge Clk_MAC or posedge Reset)`
320	7	maverickis	`if (Reset)`
321			`Add_wr <=0;`
322			`else if (Current_state==State_err_end)`
323			`Add_wr <=Add_wr_reg;`
324			`else if (Wr_en&&!Full)`
325			`Add_wr <=Add_wr +1;`
326
327	19	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
328			`if (Reset)`
329			`Add_wr_jump_tmp <=0;`
330			`else if (Current_state==State_err_end)`
331			`Add_wr_jump_tmp <=1;`
332			`else`
333			`Add_wr_jump_tmp <=0;`
334
335			`always @ (posedge Clk_MAC or posedge Reset)`
336			`if (Reset)`
337			`Add_wr_jump_tmp_pl1 <=0;`
338			`else`
339			`Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;`
340
341			`always @ (posedge Clk_MAC or posedge Reset)`
342			`if (Reset)`
343			`Add_wr_jump <=0;`
344			`else if (Current_state==State_err_end)`
345			`Add_wr_jump <=1;`
346			`else if (Add_wr_jump_tmp_pl1)`
347			`Add_wr_jump <=0;`
348
349	5	maverickis	`//`
350			`always @ (posedge Clk_MAC or posedge Reset)`
351	7	maverickis	`if (Reset)`
352			`Fifo_data_en_dl1 <=0;`
353			`else`
354			`Fifo_data_en_dl1 <=Fifo_data_en;`
355
356	5	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
357	7	maverickis	`if (Reset)`
358			`Fifo_data_dl1 <=0;`
359			`else`
360			`Fifo_data_dl1 <=Fifo_data;`
361
362	5	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
363	7	maverickis	`if (Reset)`
364			`Fifo_data_byte3 <=0;`
365			`else if (Current_state==State_byte3&&Fifo_data_en_dl1)`
366			`Fifo_data_byte3 <=Fifo_data_dl1;`
367	5	maverickis
368			`always @ (posedge Clk_MAC or posedge Reset)`
369	7	maverickis	`if (Reset)`
370			`Fifo_data_byte2 <=0;`
371			`else if (Current_state==State_byte2&&Fifo_data_en_dl1)`
372			`Fifo_data_byte2 <=Fifo_data_dl1;`
373
374	5	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
375	7	maverickis	`if (Reset)`
376			`Fifo_data_byte1 <=0;`
377			`else if (Current_state==State_byte1&&Fifo_data_en_dl1)`
378			`Fifo_data_byte1 <=Fifo_data_dl1;`
379	5	maverickis
380	7	maverickis	`always @ (* )`
381			`case (Current_state)`
382			`State_be0:`
383			`Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
384			`State_be1:`
385			`Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};`
386			`State_be2:`
387			`Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};`
388			`State_be3:`
389			`Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};`
390			`default:`
391			`Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
392			`endcase`
393
394			`always @ (*)`
395			`if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
396			`Current_state==State_be2\|\|Current_state==State_be3\|\|`
397			`(Current_state==State_byte0&&Fifo_data_en))`
398			`Wr_en_tmp =1;`
399			`else`
400			`Wr_en_tmp =0;`
401
402			`always @ (posedge Clk_MAC or posedge Reset)`
403			`if (Reset)`
404			`Din_tmp_reg <=0;`
405			`else if(Wr_en_tmp)`
406			`Din_tmp_reg <=Din_tmp;`
407
408			`always @ (posedge Clk_MAC or posedge Reset)`
409			`if (Reset)`
410			`Wr_en_ptr <=0;`
411			`else if(Current_state==State_idle)`
412			`Wr_en_ptr <=0;`
413			`else if(Wr_en_tmp)`
414			`Wr_en_ptr <=1;`
415
416			`//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS`
417			`always @ (posedge Clk_MAC or posedge Reset)`
418			`if (Reset)`
419			`begin`
420			`Wr_en <=0;`
421			`Din <=0;`
422			`end`
423			`else if(RX_APPEND_CRC)`
424			`begin`
425			`Wr_en <=Wr_en_tmp;`
426			`Din <=Din_tmp;`
427			`end`
428			`else`
429			`begin`
430			`Wr_en <=Wr_en_tmp&&Wr_en_ptr;`
431			`Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};`
432			`end`
433
434	5	maverickis	`//this signal for read side to handle the packet number in fifo`
435			`always @ (posedge Clk_MAC or posedge Reset)`
436	7	maverickis	`if (Reset)`
437			`Packet_number_add_tmp <=0;`
438			`else if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
439			`Current_state==State_be2\|\|Current_state==State_be3)`
440			`Packet_number_add_tmp <=1;`
441			`else`
442			`Packet_number_add_tmp <=0;`
443
444	6	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
445	7	maverickis	`if (Reset)`
446			`begin`
447			`Packet_number_add_tmp_dl1 <=0;`
448			`Packet_number_add_tmp_dl2 <=0;`
449			`end`
450			`else`
451			`begin`
452			`Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;`
453			`Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;`
454			`end`
455
456			`//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.`
457	6	maverickis	`//expand to two cycles long almost=16 ns`
458	7	maverickis	`//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles`
459	6	maverickis	`always @ (posedge Clk_MAC or posedge Reset)`
460	7	maverickis	`if (Reset)`
461			`Packet_number_add <=0;`
462			`else if (Packet_number_add_tmp_dl1\|\|Packet_number_add_tmp_dl2)`
463			`Packet_number_add <=1;`
464			`else`
465			`Packet_number_add <=0;`
466	5	maverickis
467
468
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471
472
473
474
475
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477
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489
490			`//******************************************************************************`
491			`//domain Clk_SYS,read data from dprom.b-port for read`
492			`//******************************************************************************`
493
494
495			`always @ (posedge Clk_SYS or posedge Reset)`
496	7	maverickis	`if (Reset)`
497			`Current_state_SYS <=SYS_idle;`
498			`else`
499			`Current_state_SYS <=Next_state_SYS;`
500

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