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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_rx/] [MAC_rx_FF.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_rx_FF.v                                                 ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $                                           
 
module MAC_rx_FF (
Reset           ,
Clk_MAC     ,
Clk_SYS     ,
//MAC_rx_ctrl interface                                                                                                                                          
Fifo_data               ,
Fifo_data_en    ,
Fifo_full           ,
Fifo_data_err   ,
Fifo_data_end   ,
//CPU
RX_APPEND_CRC,
//user interface                                                                                                                                               
Rx_mac_ra       ,
Rx_mac_rd       ,
Rx_mac_data     ,
Rx_mac_BE       ,
Rx_mac_sop      ,
Rx_mac_pa,
Rx_mac_eop
);
input                   Reset           ;
input                   Clk_MAC     ;
input                   Clk_SYS     ;
                                //MAC_rx_ctrl interface 
input[7:0]               Fifo_data               ;
input                   Fifo_data_en    ;
output                  Fifo_full           ;
input                   Fifo_data_err   ;
input                   Fifo_data_end   ;
                                //CPU
input                   RX_APPEND_CRC;
                                //user interface 
output                  Rx_mac_ra       ;//
input                   Rx_mac_rd       ;
output[31:0]     Rx_mac_data     ;
output[1:0]              Rx_mac_BE       ;
output                  Rx_mac_pa       ;
output                  Rx_mac_sop      ;
output                  Rx_mac_eop      ;
 
//******************************************************************************
//internal signals                                                              
//******************************************************************************
parameter               State_byte3             =4'd0;
parameter               State_byte2             =4'd1;
parameter               State_byte1             =4'd2;
parameter               State_byte0             =4'd3;
parameter               State_be0               =4'd4;
parameter               State_be3               =4'd5;
parameter               State_be2               =4'd6;
parameter               State_be1               =4'd7;
parameter               State_err_end   =4'd8;
parameter               State_idle              =4'd9;
 
parameter               SYS_read                =3'd0;
parameter               SYS_wait_end    =3'd1;
parameter               SYS_idle                =3'd2;
parameter               FF_emtpy_err    =3'd3;
 
reg     [8:0]            Add_wr;
reg     [8:0]            Add_wr_ungray;
reg     [8:0]            Add_wr_gray;
reg     [8:0]            Add_wr_gray_dl1;
reg     [8:0]            Add_wr_reg;
 
reg     [8:0]            Add_rd;
reg     [8:0]            Add_rd_gray;
reg     [8:0]            Add_rd_gray_dl1;
reg     [8:0]            Add_rd_ungray;
reg     [35:0]           Din;
wire[35:0]               Dout;
reg                     Wr_en;
wire[8:0]                Add_wr_pluse;
reg                             Full;
reg                             Empty /* synthesis syn_keep=1 */;
reg     [3:0]            Current_state /* synthesis syn_keep=1 */;
reg     [3:0]            Next_state;
reg     [7:0]            Fifo_data_byte0;
reg     [7:0]            Fifo_data_byte1;
reg     [7:0]            Fifo_data_byte2;
reg     [7:0]            Fifo_data_byte3;
reg                             Fifo_data_en_dl1;
reg     [7:0]            Fifo_data_dl1;
reg                             Rx_mac_sop_tmp  ;
reg                             Rx_mac_sop      ;
reg                             Rx_mac_eop      ;
reg                             Rx_mac_ra       ;
reg                             Rx_mac_pa       ;
 
 
 
reg     [2:0]            Current_state_SYS /* synthesis syn_keep=1 */;
reg     [2:0]            Next_state_SYS ;
reg     [5:0]            Packet_number_inFF /* synthesis syn_keep=1 */;
reg                             Packet_number_sub ;
wire                    Packet_number_add_edge;
reg                             Packet_number_add_dl1;
reg                             Packet_number_add_dl2;
reg                             Packet_number_add ;
 
reg                     Rx_mac_sop_tmp_dl1;
reg[35:0]                Dout_dl1;
reg[1:0]         Rx_mac_BE       ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************        
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Current_state   <=State_idle;
        else
                Current_state   <=Next_state;
 
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
        case (Current_state)
                State_idle:
                                if (Fifo_data_en)
                                        Next_state      =State_byte3;
                                else
                                        Next_state      =Current_state;
                State_byte3:
                                if (Fifo_data_en)
                                        Next_state      =State_byte2;
                                else if (Fifo_data_err)
                                        Next_state      =State_err_end;
                                else if (Fifo_data_end)
                                        Next_state      =State_be1;
                                else
                                        Next_state      =Current_state;
                State_byte2:
                                if (Fifo_data_en)
                                        Next_state      =State_byte1;
                                else if (Fifo_data_err)
                                        Next_state      =State_err_end;
                                else if (Fifo_data_end)
                                        Next_state      =State_be2;
                                else
                                        Next_state      =Current_state;
                State_byte1:
                                if (Fifo_data_en)
                                        Next_state      =State_byte0;
                                else if (Fifo_data_err)
                                        Next_state      =State_err_end;
                                else if (Fifo_data_end)
                                        Next_state      =State_be3;
                                else
                                        Next_state      =Current_state;
                State_byte0:
                                if (Fifo_data_en)
                                        Next_state      =State_byte3;
                                else if (Fifo_data_err)
                                        Next_state      =State_err_end;
                                else if (Fifo_data_end)
                                        Next_state      =State_be0;
                                else
                                        Next_state      =Current_state;
                State_be1:
                                Next_state              =State_idle;
                State_be2:
                                Next_state              =State_idle;
                State_be3:
                                Next_state              =State_idle;
                State_be0:
                                Next_state              =State_idle;
                State_err_end:
                                Next_state              =State_idle;
                default:
                                Next_state              =State_idle;
        endcase
 
//
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Add_wr_reg              <=0;
        else if (Current_state==State_idle)
                Add_wr_reg              <=Add_wr;
 
//
 
 
always @ (posedge Reset or posedge Clk_MAC)
        if (Reset)
                Add_wr_gray                     <=0;
        else
                Add_wr_gray                     <={     Add_wr[8],
                                                                Add_wr[8]^Add_wr[7],
                                                                Add_wr[7]^Add_wr[6],
                                                                Add_wr[6]^Add_wr[5],
                                                                Add_wr[5]^Add_wr[4],
                                                                Add_wr[4]^Add_wr[3],
                                                                Add_wr[3]^Add_wr[2],
                                                                Add_wr[2]^Add_wr[1],
                                                                Add_wr[1]^Add_wr[0]};
 
//
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Add_rd_gray_dl1                 <=0;
        else
                Add_rd_gray_dl1                 <=Add_rd_gray;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Add_rd_ungray           <=0;
        else
                Add_rd_ungray   <={
                Add_rd_gray_dl1[8],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1]^Add_rd_gray_dl1[0] };
 
assign                  Add_wr_pluse=Add_wr+1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Full    <=0;
        else if (Add_wr_pluse==Add_rd_ungray)
                Full    <=1;
        else
                Full    <=0;
 
assign          Fifo_full =Full;
 
//
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Add_wr  <=0;
        else if (Current_state==State_err_end)
                Add_wr  <=Add_wr_reg;
        else if (Wr_en&&!Full)
                Add_wr  <=Add_wr +1;
 
//
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_en_dl1        <=0;
        else
                Fifo_data_en_dl1        <=Fifo_data_en;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_dl1   <=0;
        else
                Fifo_data_dl1   <=Fifo_data;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_byte3         <=0;
        else if (Current_state==State_byte3&&Fifo_data_en_dl1)
                Fifo_data_byte3         <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_byte2         <=0;
        else if (Current_state==State_byte2&&Fifo_data_en_dl1)
                Fifo_data_byte2         <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_byte1         <=0;
        else if (Current_state==State_byte1&&Fifo_data_en_dl1)
                Fifo_data_byte1         <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_byte0         <=0;
        else if (Current_state==State_byte0&&Fifo_data_en_dl1)
                Fifo_data_byte0         <=Fifo_data_dl1;
 
always @ (Current_state or Fifo_data_byte3 or Fifo_data_byte2 or Fifo_data_byte1 or Fifo_data_byte0 )
        case (Current_state)
                State_be0:
                        Din     ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};
                State_be1:
                        Din     ={4'b1001,Fifo_data_byte3,24'h0};
                State_be2:
                        Din     ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
                State_be3:
                        Din     ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
                default:
                        Din     ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};
        endcase
 
always @ (Current_state or Fifo_data_en)
        if (Current_state==State_be0||Current_state==State_be1||
           Current_state==State_be2||Current_state==State_be3||
          (Current_state==State_byte0&&Fifo_data_en))
                Wr_en   <=1;
        else
                Wr_en   <=0;
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Packet_number_add       <=0;
        else if (Current_state==State_be0||Current_state==State_be1||
                         Current_state==State_be2||Current_state==State_be3)
                Packet_number_add       <=1;
        else
                Packet_number_add       <=0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Current_state_SYS       <=SYS_idle;
        else
                Current_state_SYS       <=Next_state_SYS;
 
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
        case (Current_state_SYS)
                SYS_idle:
                        if (Rx_mac_rd&&Rx_mac_ra)
                                Next_state_SYS  =SYS_read;
                        else
                                Next_state_SYS  =Current_state_SYS;
                SYS_read:
                        if (Dout[35])
                                Next_state_SYS  =SYS_wait_end;
//                      else if (Empty)
//                              Next_state_SYS  =FF_emtpy_err;
                        else
                                Next_state_SYS  =Current_state_SYS;
                FF_emtpy_err:
                        if (!Empty)
                                Next_state_SYS  =SYS_read;
                        else
                                Next_state_SYS  =Current_state_SYS;
                SYS_wait_end:
                        if (!Rx_mac_rd)
                                Next_state_SYS  =SYS_idle;
                        else
                                Next_state_SYS  =Current_state_SYS;
                default:
                                Next_state_SYS  =SYS_idle;
        endcase
 
 
//gen Rx_mac_ra 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                begin
                Packet_number_add_dl1   <=0;
                Packet_number_add_dl2   <=0;
                end
        else
                begin
                Packet_number_add_dl1   <=Packet_number_add;
                Packet_number_add_dl2   <=Packet_number_add_dl1;
                end
assign  Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
 
always @ (Current_state_SYS or Next_state_SYS)
        if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
                Packet_number_sub               =1;
        else
                Packet_number_sub               =0;
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Packet_number_inFF              <=0;
        else if (Packet_number_add_edge&&!Packet_number_sub)
                Packet_number_inFF              <=Packet_number_inFF + 1;
        else if (!Packet_number_add_edge&&Packet_number_sub)
                Packet_number_inFF              <=Packet_number_inFF - 1;
 
always @ (Packet_number_inFF)
        if (Packet_number_inFF==0)
                Rx_mac_ra       =0;
        else
                Rx_mac_ra       =1;
 
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Add_rd          <=0;
        else if (Current_state_SYS==SYS_read&&!Dout[35])
                Add_rd          <=Add_rd + 1;
 
//
always @ (posedge Reset or posedge Clk_SYS)
        if (Reset)
                Add_rd_gray                     <=0;
        else
                Add_rd_gray                     <={     Add_rd[8],
                                                                Add_rd[8]^Add_rd[7],
                                                                Add_rd[7]^Add_rd[6],
                                                                Add_rd[6]^Add_rd[5],
                                                                Add_rd[5]^Add_rd[4],
                                                                Add_rd[4]^Add_rd[3],
                                                                Add_rd[3]^Add_rd[2],
                                                                Add_rd[2]^Add_rd[1],
                                                                Add_rd[1]^Add_rd[0]};
//
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Add_wr_gray_dl1         <=0;
        else
                Add_wr_gray_dl1         <=Add_wr_gray;
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Add_wr_ungray           <=0;
        else
                Add_wr_ungray   <={
                Add_wr_gray_dl1[8],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
 
//empty signal gen      
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Empty   <=1;
        else if (Add_rd==Add_wr_ungray)
                Empty   <=1;
        else
                Empty   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Dout_dl1        <=0;
        else
                Dout_dl1        <=Dout;
 
assign  Rx_mac_data             =Dout_dl1[31:0];
 
always @ (RX_APPEND_CRC or Dout_dl1 or Dout)
        if (RX_APPEND_CRC)
        Rx_mac_BE       =Dout_dl1[33:32];
    else
        Rx_mac_BE       =Dout[33:32];
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Rx_mac_pa       <=0;
        else if (Rx_mac_sop_tmp_dl1&&Next_state_SYS==SYS_read)
                Rx_mac_pa       <=1;
        else if(Rx_mac_eop)
                Rx_mac_pa       <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Rx_mac_sop_tmp          <=0;
        else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
                Rx_mac_sop_tmp          <=1;
        else
                Rx_mac_sop_tmp          <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                begin
                Rx_mac_sop_tmp_dl1      <=0;
                Rx_mac_sop                      <=0;
                end
        else
                begin
                Rx_mac_sop_tmp_dl1      <=Rx_mac_sop_tmp;
                Rx_mac_sop                      <=Rx_mac_sop_tmp_dl1;
                end
 
 
always @(RX_APPEND_CRC or Dout_dl1 or Dout)
        if(RX_APPEND_CRC)
                Rx_mac_eop              =Dout_dl1[35];
        else
                Rx_mac_eop              =Dout[35];
//******************************************************************************
 
duram #(36,9,"M4K") U_duram(
.data_a         (Din            ),
.wren_a         (Wr_en          ),
.address_a      (Add_wr         ),
.address_b      (Add_rd         ),
.clock_a        (Clk_MAC        ),
.clock_b        (Clk_SYS        ),
.q_b            (Dout           ));
 
endmodule
 
 
 
 
 

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Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_rx/] [MAC_rx_FF.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_rx_FF.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42
43			`module MAC_rx_FF (`
44			`Reset ,`
45			`Clk_MAC ,`
46			`Clk_SYS ,`
47			`//MAC_rx_ctrl interface`
48			`Fifo_data ,`
49			`Fifo_data_en ,`
50			`Fifo_full ,`
51			`Fifo_data_err ,`
52			`Fifo_data_end ,`
53			`//CPU`
54			`RX_APPEND_CRC,`
55			`//user interface`
56			`Rx_mac_ra ,`
57			`Rx_mac_rd ,`
58			`Rx_mac_data ,`
59			`Rx_mac_BE ,`
60			`Rx_mac_sop ,`
61			`Rx_mac_pa,`
62			`Rx_mac_eop`
63			`);`
64			`input Reset ;`
65			`input Clk_MAC ;`
66			`input Clk_SYS ;`
67			`//MAC_rx_ctrl interface`
68			`input[7:0] Fifo_data ;`
69			`input Fifo_data_en ;`
70			`output Fifo_full ;`
71			`input Fifo_data_err ;`
72			`input Fifo_data_end ;`
73			`//CPU`
74			`input RX_APPEND_CRC;`
75			`//user interface`
76			`output Rx_mac_ra ;//`
77			`input Rx_mac_rd ;`
78			`output[31:0] Rx_mac_data ;`
79			`output[1:0] Rx_mac_BE ;`
80			`output Rx_mac_pa ;`
81			`output Rx_mac_sop ;`
82			`output Rx_mac_eop ;`
83
84			`//******************************************************************************`
85			`//internal signals`
86			`//******************************************************************************`
87			`parameter State_byte3 =4'd0;`
88			`parameter State_byte2 =4'd1;`
89			`parameter State_byte1 =4'd2;`
90			`parameter State_byte0 =4'd3;`
91			`parameter State_be0 =4'd4;`
92			`parameter State_be3 =4'd5;`
93			`parameter State_be2 =4'd6;`
94			`parameter State_be1 =4'd7;`
95			`parameter State_err_end =4'd8;`
96			`parameter State_idle =4'd9;`
97
98			`parameter SYS_read =3'd0;`
99			`parameter SYS_wait_end =3'd1;`
100			`parameter SYS_idle =3'd2;`
101			`parameter FF_emtpy_err =3'd3;`
102
103			`reg [8:0] Add_wr;`
104			`reg [8:0] Add_wr_ungray;`
105			`reg [8:0] Add_wr_gray;`
106			`reg [8:0] Add_wr_gray_dl1;`
107			`reg [8:0] Add_wr_reg;`
108
109			`reg [8:0] Add_rd;`
110			`reg [8:0] Add_rd_gray;`
111			`reg [8:0] Add_rd_gray_dl1;`
112			`reg [8:0] Add_rd_ungray;`
113			`reg [35:0] Din;`
114			`wire[35:0] Dout;`
115			`reg Wr_en;`
116			`wire[8:0] Add_wr_pluse;`
117			`reg Full;`
118			`reg Empty /* synthesis syn_keep=1 */;`
119			`reg [3:0] Current_state /* synthesis syn_keep=1 */;`
120			`reg [3:0] Next_state;`
121			`reg [7:0] Fifo_data_byte0;`
122			`reg [7:0] Fifo_data_byte1;`
123			`reg [7:0] Fifo_data_byte2;`
124			`reg [7:0] Fifo_data_byte3;`
125			`reg Fifo_data_en_dl1;`
126			`reg [7:0] Fifo_data_dl1;`
127			`reg Rx_mac_sop_tmp ;`
128			`reg Rx_mac_sop ;`
129			`reg Rx_mac_eop ;`
130			`reg Rx_mac_ra ;`
131			`reg Rx_mac_pa ;`
132
133
134
135			`reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;`
136			`reg [2:0] Next_state_SYS ;`
137			`reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;`
138			`reg Packet_number_sub ;`
139			`wire Packet_number_add_edge;`
140			`reg Packet_number_add_dl1;`
141			`reg Packet_number_add_dl2;`
142			`reg Packet_number_add ;`
143
144			`reg Rx_mac_sop_tmp_dl1;`
145			`reg[35:0] Dout_dl1;`
146			`reg[1:0] Rx_mac_BE ;`
147			`//******************************************************************************`
148			`//domain Clk_MAC,write data to dprom.a-port for write`
149			`//******************************************************************************`
150			`always @ (posedge Clk_MAC or posedge Reset)`
151			`if (Reset)`
152			`Current_state <=State_idle;`
153			`else`
154			`Current_state <=Next_state;`
155
156			`always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)`
157			`case (Current_state)`
158			`State_idle:`
159			`if (Fifo_data_en)`
160			`Next_state =State_byte3;`
161			`else`
162			`Next_state =Current_state;`
163			`State_byte3:`
164			`if (Fifo_data_en)`
165			`Next_state =State_byte2;`
166			`else if (Fifo_data_err)`
167			`Next_state =State_err_end;`
168			`else if (Fifo_data_end)`
169			`Next_state =State_be1;`
170			`else`
171			`Next_state =Current_state;`
172			`State_byte2:`
173			`if (Fifo_data_en)`
174			`Next_state =State_byte1;`
175			`else if (Fifo_data_err)`
176			`Next_state =State_err_end;`
177			`else if (Fifo_data_end)`
178			`Next_state =State_be2;`
179			`else`
180			`Next_state =Current_state;`
181			`State_byte1:`
182			`if (Fifo_data_en)`
183			`Next_state =State_byte0;`
184			`else if (Fifo_data_err)`
185			`Next_state =State_err_end;`
186			`else if (Fifo_data_end)`
187			`Next_state =State_be3;`
188			`else`
189			`Next_state =Current_state;`
190			`State_byte0:`
191			`if (Fifo_data_en)`
192			`Next_state =State_byte3;`
193			`else if (Fifo_data_err)`
194			`Next_state =State_err_end;`
195			`else if (Fifo_data_end)`
196			`Next_state =State_be0;`
197			`else`
198			`Next_state =Current_state;`
199			`State_be1:`
200			`Next_state =State_idle;`
201			`State_be2:`
202			`Next_state =State_idle;`
203			`State_be3:`
204			`Next_state =State_idle;`
205			`State_be0:`
206			`Next_state =State_idle;`
207			`State_err_end:`
208			`Next_state =State_idle;`
209			`default:`
210			`Next_state =State_idle;`
211			`endcase`
212
213			`//`
214			`always @ (posedge Clk_MAC or posedge Reset)`
215			`if (Reset)`
216			`Add_wr_reg <=0;`
217			`else if (Current_state==State_idle)`
218			`Add_wr_reg <=Add_wr;`
219
220			`//`
221
222
223			`always @ (posedge Reset or posedge Clk_MAC)`
224			`if (Reset)`
225			`Add_wr_gray <=0;`
226			`else`
227			`Add_wr_gray <={ Add_wr[8],`
228			`Add_wr[8]^Add_wr[7],`
229			`Add_wr[7]^Add_wr[6],`
230			`Add_wr[6]^Add_wr[5],`
231			`Add_wr[5]^Add_wr[4],`
232			`Add_wr[4]^Add_wr[3],`
233			`Add_wr[3]^Add_wr[2],`
234			`Add_wr[2]^Add_wr[1],`
235			`Add_wr[1]^Add_wr[0]};`
236
237			`//`
238
239			`always @ (posedge Clk_MAC or posedge Reset)`
240			`if (Reset)`
241			`Add_rd_gray_dl1 <=0;`
242			`else`
243			`Add_rd_gray_dl1 <=Add_rd_gray;`
244
245			`always @ (posedge Clk_MAC or posedge Reset)`
246			`if (Reset)`
247			`Add_rd_ungray <=0;`
248			`else`
249			`Add_rd_ungray <={`
250			`Add_rd_gray_dl1[8],`
251			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7],`
252			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6],`
253			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5],`
254			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4],`
255			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3],`
256			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2],`
257			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1],`
258			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1]^Add_rd_gray_dl1[0] };`
259
260			`assign Add_wr_pluse=Add_wr+1;`
261
262			`always @ (posedge Clk_MAC or posedge Reset)`
263			`if (Reset)`
264			`Full <=0;`
265			`else if (Add_wr_pluse==Add_rd_ungray)`
266			`Full <=1;`
267			`else`
268			`Full <=0;`
269
270			`assign Fifo_full =Full;`
271
272			`//`
273			`always @ (posedge Clk_MAC or posedge Reset)`
274			`if (Reset)`
275			`Add_wr <=0;`
276			`else if (Current_state==State_err_end)`
277			`Add_wr <=Add_wr_reg;`
278			`else if (Wr_en&&!Full)`
279			`Add_wr <=Add_wr +1;`
280
281			`//`
282			`always @ (posedge Clk_MAC or posedge Reset)`
283			`if (Reset)`
284			`Fifo_data_en_dl1 <=0;`
285			`else`
286			`Fifo_data_en_dl1 <=Fifo_data_en;`
287
288			`always @ (posedge Clk_MAC or posedge Reset)`
289			`if (Reset)`
290			`Fifo_data_dl1 <=0;`
291			`else`
292			`Fifo_data_dl1 <=Fifo_data;`
293
294			`always @ (posedge Clk_MAC or posedge Reset)`
295			`if (Reset)`
296			`Fifo_data_byte3 <=0;`
297			`else if (Current_state==State_byte3&&Fifo_data_en_dl1)`
298			`Fifo_data_byte3 <=Fifo_data_dl1;`
299
300			`always @ (posedge Clk_MAC or posedge Reset)`
301			`if (Reset)`
302			`Fifo_data_byte2 <=0;`
303			`else if (Current_state==State_byte2&&Fifo_data_en_dl1)`
304			`Fifo_data_byte2 <=Fifo_data_dl1;`
305
306			`always @ (posedge Clk_MAC or posedge Reset)`
307			`if (Reset)`
308			`Fifo_data_byte1 <=0;`
309			`else if (Current_state==State_byte1&&Fifo_data_en_dl1)`
310			`Fifo_data_byte1 <=Fifo_data_dl1;`
311
312			`always @ (posedge Clk_MAC or posedge Reset)`
313			`if (Reset)`
314			`Fifo_data_byte0 <=0;`
315			`else if (Current_state==State_byte0&&Fifo_data_en_dl1)`
316			`Fifo_data_byte0 <=Fifo_data_dl1;`
317
318			`always @ (Current_state or Fifo_data_byte3 or Fifo_data_byte2 or Fifo_data_byte1 or Fifo_data_byte0 )`
319			`case (Current_state)`
320			`State_be0:`
321			`Din ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};`
322			`State_be1:`
323			`Din ={4'b1001,Fifo_data_byte3,24'h0};`
324			`State_be2:`
325			`Din ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};`
326			`State_be3:`
327			`Din ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};`
328			`default:`
329			`Din ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_byte0};`
330			`endcase`
331
332			`always @ (Current_state or Fifo_data_en)`
333			`if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
334			`Current_state==State_be2\|\|Current_state==State_be3\|\|`
335			`(Current_state==State_byte0&&Fifo_data_en))`
336			`Wr_en <=1;`
337			`else`
338			`Wr_en <=0;`
339			`//this signal for read side to handle the packet number in fifo`
340			`always @ (posedge Clk_MAC or posedge Reset)`
341			`if (Reset)`
342			`Packet_number_add <=0;`
343			`else if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
344			`Current_state==State_be2\|\|Current_state==State_be3)`
345			`Packet_number_add <=1;`
346			`else`
347			`Packet_number_add <=0;`
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372			`//******************************************************************************`
373			`//domain Clk_SYS,read data from dprom.b-port for read`
374			`//******************************************************************************`
375
376
377			`always @ (posedge Clk_SYS or posedge Reset)`
378			`if (Reset)`
379			`Current_state_SYS <=SYS_idle;`
380			`else`
381			`Current_state_SYS <=Next_state_SYS;`
382
383			`always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)`
384			`case (Current_state_SYS)`
385			`SYS_idle:`
386			`if (Rx_mac_rd&&Rx_mac_ra)`
387			`Next_state_SYS =SYS_read;`
388			`else`
389			`Next_state_SYS =Current_state_SYS;`
390			`SYS_read:`
391			`if (Dout[35])`
392			`Next_state_SYS =SYS_wait_end;`
393			`// else if (Empty)`
394			`// Next_state_SYS =FF_emtpy_err;`
395			`else`
396			`Next_state_SYS =Current_state_SYS;`
397			`FF_emtpy_err:`
398			`if (!Empty)`
399			`Next_state_SYS =SYS_read;`
400			`else`
401			`Next_state_SYS =Current_state_SYS;`
402			`SYS_wait_end:`
403			`if (!Rx_mac_rd)`
404			`Next_state_SYS =SYS_idle;`
405			`else`
406			`Next_state_SYS =Current_state_SYS;`
407			`default:`
408			`Next_state_SYS =SYS_idle;`
409			`endcase`
410
411
412			`//gen Rx_mac_ra`
413			`always @ (posedge Clk_SYS or posedge Reset)`
414			`if (Reset)`
415			`begin`
416			`Packet_number_add_dl1 <=0;`
417			`Packet_number_add_dl2 <=0;`
418			`end`
419			`else`
420			`begin`
421			`Packet_number_add_dl1 <=Packet_number_add;`
422			`Packet_number_add_dl2 <=Packet_number_add_dl1;`
423			`end`
424			`assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;`
425
426			`always @ (Current_state_SYS or Next_state_SYS)`
427			`if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)`
428			`Packet_number_sub =1;`
429			`else`
430			`Packet_number_sub =0;`
431
432			`always @ (posedge Clk_SYS or posedge Reset)`
433			`if (Reset)`
434			`Packet_number_inFF <=0;`
435			`else if (Packet_number_add_edge&&!Packet_number_sub)`
436			`Packet_number_inFF <=Packet_number_inFF + 1;`
437			`else if (!Packet_number_add_edge&&Packet_number_sub)`
438			`Packet_number_inFF <=Packet_number_inFF - 1;`
439
440			`always @ (Packet_number_inFF)`
441			`if (Packet_number_inFF==0)`
442			`Rx_mac_ra =0;`
443			`else`
444			`Rx_mac_ra =1;`
445
446			`//control Add_rd signal;`
447			`always @ (posedge Clk_SYS or posedge Reset)`
448			`if (Reset)`
449			`Add_rd <=0;`
450			`else if (Current_state_SYS==SYS_read&&!Dout[35])`
451			`Add_rd <=Add_rd + 1;`
452
453			`//`
454			`always @ (posedge Reset or posedge Clk_SYS)`
455			`if (Reset)`
456			`Add_rd_gray <=0;`
457			`else`
458			`Add_rd_gray <={ Add_rd[8],`
459			`Add_rd[8]^Add_rd[7],`
460			`Add_rd[7]^Add_rd[6],`
461			`Add_rd[6]^Add_rd[5],`
462			`Add_rd[5]^Add_rd[4],`
463			`Add_rd[4]^Add_rd[3],`
464			`Add_rd[3]^Add_rd[2],`
465			`Add_rd[2]^Add_rd[1],`
466			`Add_rd[1]^Add_rd[0]};`
467			`//`
468
469			`always @ (posedge Clk_SYS or posedge Reset)`
470			`if (Reset)`
471			`Add_wr_gray_dl1 <=0;`
472			`else`
473			`Add_wr_gray_dl1 <=Add_wr_gray;`
474
475			`always @ (posedge Clk_SYS or posedge Reset)`
476			`if (Reset)`
477			`Add_wr_ungray <=0;`
478			`else`
479			`Add_wr_ungray <={`
480			`Add_wr_gray_dl1[8],`
481			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],`
482			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],`
483			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],`
484			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],`
485			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],`
486			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],`
487			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],`
488			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };`
489
490			`//empty signal gen`
491			`always @ (posedge Clk_SYS or posedge Reset)`
492			`if (Reset)`
493			`Empty <=1;`
494			`else if (Add_rd==Add_wr_ungray)`
495			`Empty <=1;`
496			`else`
497			`Empty <=0;`
498
499
500
501			`always @ (posedge Clk_SYS or posedge Reset)`
502			`if (Reset)`
503			`Dout_dl1 <=0;`
504			`else`
505			`Dout_dl1 <=Dout;`
506
507			`assign Rx_mac_data =Dout_dl1[31:0];`
508
509			`always @ (RX_APPEND_CRC or Dout_dl1 or Dout)`
510			`if (RX_APPEND_CRC)`
511			`Rx_mac_BE =Dout_dl1[33:32];`
512			`else`
513			`Rx_mac_BE =Dout[33:32];`
514
515
516			`always @ (posedge Clk_SYS or posedge Reset)`
517			`if (Reset)`
518			`Rx_mac_pa <=0;`
519			`else if (Rx_mac_sop_tmp_dl1&&Next_state_SYS==SYS_read)`
520			`Rx_mac_pa <=1;`
521			`else if(Rx_mac_eop)`
522			`Rx_mac_pa <=0;`
523
524
525
526			`always @ (posedge Clk_SYS or posedge Reset)`
527			`if (Reset)`
528			`Rx_mac_sop_tmp <=0;`
529			`else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)`
530			`Rx_mac_sop_tmp <=1;`
531			`else`
532			`Rx_mac_sop_tmp <=0;`
533
534
535
536			`always @ (posedge Clk_SYS or posedge Reset)`
537			`if (Reset)`
538			`begin`
539			`Rx_mac_sop_tmp_dl1 <=0;`
540			`Rx_mac_sop <=0;`
541			`end`
542			`else`
543			`begin`
544			`Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;`
545			`Rx_mac_sop <=Rx_mac_sop_tmp_dl1;`
546			`end`
547
548
549			`always @(RX_APPEND_CRC or Dout_dl1 or Dout)`
550			`if(RX_APPEND_CRC)`
551			`Rx_mac_eop =Dout_dl1[35];`
552			`else`
553			`Rx_mac_eop =Dout[35];`
554			`//******************************************************************************`
555
556			`duram #(36,9,"M4K") U_duram(`
557			`.data_a (Din ),`
558			`.wren_a (Wr_en ),`
559			`.address_a (Add_wr ),`
560			`.address_b (Add_rd ),`
561			`.clock_a (Clk_MAC ),`
562			`.clock_b (Clk_SYS ),`
563			`.q_b (Dout ));`
564
565			`endmodule`
566
567
568
569
570