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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_rx/] [MAC_rx_FF.v] - Blame information for rev 6

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_rx_FF.v                                                 ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
//
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//                                           
 
module MAC_rx_FF (
Reset           ,
Clk_MAC     ,
Clk_SYS     ,
//MAC_rx_ctrl interface                                                                                                                                          
Fifo_data               ,
Fifo_data_en    ,
Fifo_full           ,
Fifo_data_err   ,
Fifo_data_end   ,
//CPU
RX_APPEND_CRC,
//user interface                                                                                                                                               
Rx_mac_ra       ,
Rx_mac_rd       ,
Rx_mac_data     ,
Rx_mac_BE       ,
Rx_mac_sop      ,
Rx_mac_pa,
Rx_mac_eop
);
input                   Reset           ;
input                   Clk_MAC     ;
input                   Clk_SYS     ;
                                //MAC_rx_ctrl interface 
input[7:0]               Fifo_data               ;
input                   Fifo_data_en    ;
output                  Fifo_full           ;
input                   Fifo_data_err   ;
input                   Fifo_data_end   ;
                                //CPU
input                   RX_APPEND_CRC;
                                //user interface 
output                  Rx_mac_ra       ;//
input                   Rx_mac_rd       ;
output[31:0]     Rx_mac_data     ;
output[1:0]              Rx_mac_BE       ;
output                  Rx_mac_pa       ;
output                  Rx_mac_sop      ;
output                  Rx_mac_eop      ;
 
//******************************************************************************
//internal signals                                                              
//******************************************************************************
parameter               State_byte3             =4'd0;
parameter               State_byte2             =4'd1;
parameter               State_byte1             =4'd2;
parameter               State_byte0             =4'd3;
parameter               State_be0               =4'd4;
parameter               State_be3               =4'd5;
parameter               State_be2               =4'd6;
parameter               State_be1               =4'd7;
parameter               State_err_end   =4'd8;
parameter               State_idle              =4'd9;
 
parameter               SYS_read                =3'd0;
parameter               SYS_wait_end    =3'd1;
parameter               SYS_idle                =3'd2;
parameter               FF_emtpy_err    =3'd3;
 
reg     [8:0]            Add_wr;
reg     [8:0]            Add_wr_ungray;
reg     [8:0]            Add_wr_gray;
reg     [8:0]            Add_wr_gray_dl1;
reg     [8:0]            Add_wr_reg;
 
reg     [8:0]            Add_rd;
reg     [8:0]            Add_rd_gray;
reg     [8:0]            Add_rd_gray_dl1;
reg     [8:0]            Add_rd_ungray;
reg     [35:0]           Din;
wire[35:0]               Dout;
reg                     Wr_en;
wire[8:0]                Add_wr_pluse;
reg                             Full;
reg                             Empty /* synthesis syn_keep=1 */;
reg     [3:0]            Current_state /* synthesis syn_keep=1 */;
reg     [3:0]            Next_state;
reg     [7:0]            Fifo_data_byte0;
reg     [7:0]            Fifo_data_byte1;
reg     [7:0]            Fifo_data_byte2;
reg     [7:0]            Fifo_data_byte3;
reg                             Fifo_data_en_dl1;
reg     [7:0]            Fifo_data_dl1;
reg                             Rx_mac_sop_tmp  ;
reg                             Rx_mac_sop      ;
reg                             Rx_mac_eop      ;
reg                             Rx_mac_ra       ;
reg                             Rx_mac_pa       ;
 
 
 
reg     [2:0]            Current_state_SYS /* synthesis syn_keep=1 */;
reg     [2:0]            Next_state_SYS ;
reg     [5:0]            Packet_number_inFF /* synthesis syn_keep=1 */;
reg                             Packet_number_sub ;
wire                    Packet_number_add_edge;
reg                             Packet_number_add_dl1;
reg                             Packet_number_add_dl2;
reg                             Packet_number_add ;
reg                             Packet_number_add_tmp    ;
reg                             Packet_number_add_tmp_dl1;
reg                             Packet_number_add_tmp_dl2;
 
reg                     Rx_mac_sop_tmp_dl1;
reg[35:0]                Dout_dl1;
reg[1:0]         Rx_mac_BE       ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************        
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Current_state   <=State_idle;
        else
                Current_state   <=Next_state;
 
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
        case (Current_state)
                State_idle:
                                if (Fifo_data_en)
                                        Next_state      =State_byte3;
                                else
                                        Next_state      =Current_state;
                State_byte3:
                                if (Fifo_data_en)
                                        Next_state      =State_byte2;
                                else if (Fifo_data_err)
                                        Next_state      =State_err_end;
                                else if (Fifo_data_end)
                                        Next_state      =State_be1;
                                else
                                        Next_state      =Current_state;
                State_byte2:
                                if (Fifo_data_en)
                                        Next_state      =State_byte1;
                                else if (Fifo_data_err)
                                        Next_state      =State_err_end;
                                else if (Fifo_data_end)
                                        Next_state      =State_be2;
                                else
                                        Next_state      =Current_state;
                State_byte1:
                                if (Fifo_data_en)
                                        Next_state      =State_byte0;
                                else if (Fifo_data_err)
                                        Next_state      =State_err_end;
                                else if (Fifo_data_end)
                                        Next_state      =State_be3;
                                else
                                        Next_state      =Current_state;
                State_byte0:
                                if (Fifo_data_en)
                                        Next_state      =State_byte3;
                                else if (Fifo_data_err)
                                        Next_state      =State_err_end;
                                else if (Fifo_data_end)
                                        Next_state      =State_be0;
                                else
                                        Next_state      =Current_state;
                State_be1:
                                Next_state              =State_idle;
                State_be2:
                                Next_state              =State_idle;
                State_be3:
                                Next_state              =State_idle;
                State_be0:
                                Next_state              =State_idle;
                State_err_end:
                                Next_state              =State_idle;
                default:
                                Next_state              =State_idle;
        endcase
 
//
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Add_wr_reg              <=0;
        else if (Current_state==State_idle)
                Add_wr_reg              <=Add_wr;
 
//
 
 
always @ (posedge Reset or posedge Clk_MAC)
        if (Reset)
                Add_wr_gray                     <=0;
        else
                Add_wr_gray                     <={     Add_wr[8],
                                                                Add_wr[8]^Add_wr[7],
                                                                Add_wr[7]^Add_wr[6],
                                                                Add_wr[6]^Add_wr[5],
                                                                Add_wr[5]^Add_wr[4],
                                                                Add_wr[4]^Add_wr[3],
                                                                Add_wr[3]^Add_wr[2],
                                                                Add_wr[2]^Add_wr[1],
                                                                Add_wr[1]^Add_wr[0]};
 
//
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Add_rd_gray_dl1                 <=0;
        else
                Add_rd_gray_dl1                 <=Add_rd_gray;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Add_rd_ungray           <=0;
        else
                Add_rd_ungray   <={
                Add_rd_gray_dl1[8],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1],
                Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1]^Add_rd_gray_dl1[0] };
 
assign                  Add_wr_pluse=Add_wr+1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Full    <=0;
        else if (Add_wr_pluse==Add_rd_ungray)
                Full    <=1;
        else
                Full    <=0;
 
assign          Fifo_full =Full;
 
//
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Add_wr  <=0;
        else if (Current_state==State_err_end)
                Add_wr  <=Add_wr_reg;
        else if (Wr_en&&!Full)
                Add_wr  <=Add_wr +1;
 
//
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_en_dl1        <=0;
        else
                Fifo_data_en_dl1        <=Fifo_data_en;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_dl1   <=0;
        else
                Fifo_data_dl1   <=Fifo_data;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_byte3         <=0;
        else if (Current_state==State_byte3&&Fifo_data_en_dl1)
                Fifo_data_byte3         <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_byte2         <=0;
        else if (Current_state==State_byte2&&Fifo_data_en_dl1)
                Fifo_data_byte2         <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Fifo_data_byte1         <=0;
        else if (Current_state==State_byte1&&Fifo_data_en_dl1)
                Fifo_data_byte1         <=Fifo_data_dl1;
 
always @ (Current_state or Fifo_data_byte3 or Fifo_data_byte2 or Fifo_data_byte1 )
        case (Current_state)
                State_be0:
                        Din     ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
                State_be1:
                        Din     ={4'b1001,Fifo_data_byte3,24'h0};
                State_be2:
                        Din     ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
                State_be3:
                        Din     ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
                default:
                        Din     ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
        endcase
 
always @ (Current_state or Fifo_data_en)
        if (Current_state==State_be0||Current_state==State_be1||
           Current_state==State_be2||Current_state==State_be3||
          (Current_state==State_byte0&&Fifo_data_en))
                Wr_en   <=1;
        else
                Wr_en   <=0;
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Packet_number_add_tmp   <=0;
        else if (Current_state==State_be0||Current_state==State_be1||
                         Current_state==State_be2||Current_state==State_be3)
                Packet_number_add_tmp   <=1;
        else
                Packet_number_add_tmp   <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                begin
                Packet_number_add_tmp_dl1       <=0;
                Packet_number_add_tmp_dl2       <=0;
                end
        else
                begin
                Packet_number_add_tmp_dl1       <=Packet_number_add_tmp;
                Packet_number_add_tmp_dl2       <=Packet_number_add_tmp_dl1;
                end
 
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.           
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles           
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Packet_number_add       <=0;
        else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
                Packet_number_add       <=1;
        else
                Packet_number_add       <=0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Current_state_SYS       <=SYS_idle;
        else
                Current_state_SYS       <=Next_state_SYS;
 
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
        case (Current_state_SYS)
                SYS_idle:
                        if (Rx_mac_rd&&Rx_mac_ra)
                                Next_state_SYS  =SYS_read;
                        else
                                Next_state_SYS  =Current_state_SYS;
                SYS_read:
                        if (Dout[35])
                                Next_state_SYS  =SYS_wait_end;
//                      else if (Empty)
//                              Next_state_SYS  =FF_emtpy_err;
                        else
                                Next_state_SYS  =Current_state_SYS;
                FF_emtpy_err:
                        if (!Empty)
                                Next_state_SYS  =SYS_read;
                        else
                                Next_state_SYS  =Current_state_SYS;
                SYS_wait_end:
                        if (!Rx_mac_rd)
                                Next_state_SYS  =SYS_idle;
                        else
                                Next_state_SYS  =Current_state_SYS;
                default:
                                Next_state_SYS  =SYS_idle;
        endcase
 
 
//gen Rx_mac_ra 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                begin
                Packet_number_add_dl1   <=0;
                Packet_number_add_dl2   <=0;
                end
        else
                begin
                Packet_number_add_dl1   <=Packet_number_add;
                Packet_number_add_dl2   <=Packet_number_add_dl1;
                end
assign  Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
 
always @ (Current_state_SYS or Next_state_SYS)
        if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
                Packet_number_sub               =1;
        else
                Packet_number_sub               =0;
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Packet_number_inFF              <=0;
        else if (Packet_number_add_edge&&!Packet_number_sub)
                Packet_number_inFF              <=Packet_number_inFF + 1;
        else if (!Packet_number_add_edge&&Packet_number_sub)
                Packet_number_inFF              <=Packet_number_inFF - 1;
 
always @ (Packet_number_inFF)
        if (Packet_number_inFF==0)
                Rx_mac_ra       =0;
        else
                Rx_mac_ra       =1;
 
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Add_rd          <=0;
        else if (Current_state_SYS==SYS_read&&!Dout[35])
                Add_rd          <=Add_rd + 1;
 
//
always @ (posedge Reset or posedge Clk_SYS)
        if (Reset)
                Add_rd_gray                     <=0;
        else
                Add_rd_gray                     <={     Add_rd[8],
                                                                Add_rd[8]^Add_rd[7],
                                                                Add_rd[7]^Add_rd[6],
                                                                Add_rd[6]^Add_rd[5],
                                                                Add_rd[5]^Add_rd[4],
                                                                Add_rd[4]^Add_rd[3],
                                                                Add_rd[3]^Add_rd[2],
                                                                Add_rd[2]^Add_rd[1],
                                                                Add_rd[1]^Add_rd[0]};
//
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Add_wr_gray_dl1         <=0;
        else
                Add_wr_gray_dl1         <=Add_wr_gray;
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Add_wr_ungray           <=0;
        else
                Add_wr_ungray   <={
                Add_wr_gray_dl1[8],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
                Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
 
//empty signal gen      
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Empty   <=1;
        else if (Add_rd==Add_wr_ungray)
                Empty   <=1;
        else
                Empty   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Dout_dl1        <=0;
        else
                Dout_dl1        <=Dout;
 
assign  Rx_mac_data             =Dout_dl1[31:0];
 
always @ (RX_APPEND_CRC or Dout_dl1 or Dout)
        if (RX_APPEND_CRC)
        Rx_mac_BE       =Dout_dl1[33:32];
    else
        Rx_mac_BE       =Dout[33:32];
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Rx_mac_pa       <=0;
        else if (Rx_mac_sop_tmp_dl1&&Next_state_SYS==SYS_read)
                Rx_mac_pa       <=1;
        else if(Rx_mac_eop)
                Rx_mac_pa       <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                Rx_mac_sop_tmp          <=0;
        else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
                Rx_mac_sop_tmp          <=1;
        else
                Rx_mac_sop_tmp          <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
        if (Reset)
                begin
                Rx_mac_sop_tmp_dl1      <=0;
                Rx_mac_sop                      <=0;
                end
        else
                begin
                Rx_mac_sop_tmp_dl1      <=Rx_mac_sop_tmp;
                Rx_mac_sop                      <=Rx_mac_sop_tmp_dl1;
                end
 
 
always @(RX_APPEND_CRC or Dout_dl1 or Dout)
        if(RX_APPEND_CRC)
                Rx_mac_eop              =Dout_dl1[35];
        else
                Rx_mac_eop              =Dout[35];
//******************************************************************************
 
duram #(36,9,"M4K") U_duram(
.data_a         (Din            ),
.wren_a         (Wr_en          ),
.address_a      (Add_wr         ),
.address_b      (Add_rd         ),
.clock_a        (Clk_MAC        ),
.clock_b        (Clk_SYS        ),
.q_b            (Dout           ));
 
endmodule
 
 
 
 
 

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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_rx/] [MAC_rx_FF.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_rx_FF.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41	6	maverickis	`// $Log: not supported by cvs2svn $`
42			`//`
43			`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
44			`// no message`
45			`//`
46	5	maverickis
47			`module MAC_rx_FF (`
48			`Reset ,`
49			`Clk_MAC ,`
50			`Clk_SYS ,`
51			`//MAC_rx_ctrl interface`
52			`Fifo_data ,`
53			`Fifo_data_en ,`
54			`Fifo_full ,`
55			`Fifo_data_err ,`
56			`Fifo_data_end ,`
57			`//CPU`
58			`RX_APPEND_CRC,`
59			`//user interface`
60			`Rx_mac_ra ,`
61			`Rx_mac_rd ,`
62			`Rx_mac_data ,`
63			`Rx_mac_BE ,`
64			`Rx_mac_sop ,`
65			`Rx_mac_pa,`
66			`Rx_mac_eop`
67			`);`
68			`input Reset ;`
69			`input Clk_MAC ;`
70			`input Clk_SYS ;`
71			`//MAC_rx_ctrl interface`
72			`input[7:0] Fifo_data ;`
73			`input Fifo_data_en ;`
74			`output Fifo_full ;`
75			`input Fifo_data_err ;`
76			`input Fifo_data_end ;`
77			`//CPU`
78			`input RX_APPEND_CRC;`
79			`//user interface`
80			`output Rx_mac_ra ;//`
81			`input Rx_mac_rd ;`
82			`output[31:0] Rx_mac_data ;`
83			`output[1:0] Rx_mac_BE ;`
84			`output Rx_mac_pa ;`
85			`output Rx_mac_sop ;`
86			`output Rx_mac_eop ;`
87
88			`//******************************************************************************`
89			`//internal signals`
90			`//******************************************************************************`
91			`parameter State_byte3 =4'd0;`
92			`parameter State_byte2 =4'd1;`
93			`parameter State_byte1 =4'd2;`
94			`parameter State_byte0 =4'd3;`
95			`parameter State_be0 =4'd4;`
96			`parameter State_be3 =4'd5;`
97			`parameter State_be2 =4'd6;`
98			`parameter State_be1 =4'd7;`
99			`parameter State_err_end =4'd8;`
100			`parameter State_idle =4'd9;`
101
102			`parameter SYS_read =3'd0;`
103			`parameter SYS_wait_end =3'd1;`
104			`parameter SYS_idle =3'd2;`
105			`parameter FF_emtpy_err =3'd3;`
106
107			`reg [8:0] Add_wr;`
108			`reg [8:0] Add_wr_ungray;`
109			`reg [8:0] Add_wr_gray;`
110			`reg [8:0] Add_wr_gray_dl1;`
111			`reg [8:0] Add_wr_reg;`
112
113			`reg [8:0] Add_rd;`
114			`reg [8:0] Add_rd_gray;`
115			`reg [8:0] Add_rd_gray_dl1;`
116			`reg [8:0] Add_rd_ungray;`
117			`reg [35:0] Din;`
118			`wire[35:0] Dout;`
119			`reg Wr_en;`
120			`wire[8:0] Add_wr_pluse;`
121			`reg Full;`
122			`reg Empty /* synthesis syn_keep=1 */;`
123			`reg [3:0] Current_state /* synthesis syn_keep=1 */;`
124			`reg [3:0] Next_state;`
125			`reg [7:0] Fifo_data_byte0;`
126			`reg [7:0] Fifo_data_byte1;`
127			`reg [7:0] Fifo_data_byte2;`
128			`reg [7:0] Fifo_data_byte3;`
129			`reg Fifo_data_en_dl1;`
130			`reg [7:0] Fifo_data_dl1;`
131			`reg Rx_mac_sop_tmp ;`
132			`reg Rx_mac_sop ;`
133			`reg Rx_mac_eop ;`
134			`reg Rx_mac_ra ;`
135			`reg Rx_mac_pa ;`
136
137
138
139			`reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;`
140			`reg [2:0] Next_state_SYS ;`
141			`reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;`
142			`reg Packet_number_sub ;`
143			`wire Packet_number_add_edge;`
144			`reg Packet_number_add_dl1;`
145			`reg Packet_number_add_dl2;`
146			`reg Packet_number_add ;`
147	6	maverickis	`reg Packet_number_add_tmp ;`
148			`reg Packet_number_add_tmp_dl1;`
149			`reg Packet_number_add_tmp_dl2;`
150	5	maverickis
151			`reg Rx_mac_sop_tmp_dl1;`
152			`reg[35:0] Dout_dl1;`
153			`reg[1:0] Rx_mac_BE ;`
154			`//******************************************************************************`
155			`//domain Clk_MAC,write data to dprom.a-port for write`
156			`//******************************************************************************`
157			`always @ (posedge Clk_MAC or posedge Reset)`
158			`if (Reset)`
159			`Current_state <=State_idle;`
160			`else`
161			`Current_state <=Next_state;`
162
163			`always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)`
164			`case (Current_state)`
165			`State_idle:`
166			`if (Fifo_data_en)`
167			`Next_state =State_byte3;`
168			`else`
169			`Next_state =Current_state;`
170			`State_byte3:`
171			`if (Fifo_data_en)`
172			`Next_state =State_byte2;`
173			`else if (Fifo_data_err)`
174			`Next_state =State_err_end;`
175			`else if (Fifo_data_end)`
176			`Next_state =State_be1;`
177			`else`
178			`Next_state =Current_state;`
179			`State_byte2:`
180			`if (Fifo_data_en)`
181			`Next_state =State_byte1;`
182			`else if (Fifo_data_err)`
183			`Next_state =State_err_end;`
184			`else if (Fifo_data_end)`
185			`Next_state =State_be2;`
186			`else`
187			`Next_state =Current_state;`
188			`State_byte1:`
189			`if (Fifo_data_en)`
190			`Next_state =State_byte0;`
191			`else if (Fifo_data_err)`
192			`Next_state =State_err_end;`
193			`else if (Fifo_data_end)`
194			`Next_state =State_be3;`
195			`else`
196			`Next_state =Current_state;`
197			`State_byte0:`
198			`if (Fifo_data_en)`
199			`Next_state =State_byte3;`
200			`else if (Fifo_data_err)`
201			`Next_state =State_err_end;`
202			`else if (Fifo_data_end)`
203			`Next_state =State_be0;`
204			`else`
205			`Next_state =Current_state;`
206			`State_be1:`
207			`Next_state =State_idle;`
208			`State_be2:`
209			`Next_state =State_idle;`
210			`State_be3:`
211			`Next_state =State_idle;`
212			`State_be0:`
213			`Next_state =State_idle;`
214			`State_err_end:`
215			`Next_state =State_idle;`
216			`default:`
217			`Next_state =State_idle;`
218			`endcase`
219
220			`//`
221			`always @ (posedge Clk_MAC or posedge Reset)`
222			`if (Reset)`
223			`Add_wr_reg <=0;`
224			`else if (Current_state==State_idle)`
225			`Add_wr_reg <=Add_wr;`
226
227			`//`
228
229
230			`always @ (posedge Reset or posedge Clk_MAC)`
231			`if (Reset)`
232			`Add_wr_gray <=0;`
233			`else`
234			`Add_wr_gray <={ Add_wr[8],`
235			`Add_wr[8]^Add_wr[7],`
236			`Add_wr[7]^Add_wr[6],`
237			`Add_wr[6]^Add_wr[5],`
238			`Add_wr[5]^Add_wr[4],`
239			`Add_wr[4]^Add_wr[3],`
240			`Add_wr[3]^Add_wr[2],`
241			`Add_wr[2]^Add_wr[1],`
242			`Add_wr[1]^Add_wr[0]};`
243
244			`//`
245
246			`always @ (posedge Clk_MAC or posedge Reset)`
247			`if (Reset)`
248			`Add_rd_gray_dl1 <=0;`
249			`else`
250			`Add_rd_gray_dl1 <=Add_rd_gray;`
251
252			`always @ (posedge Clk_MAC or posedge Reset)`
253			`if (Reset)`
254			`Add_rd_ungray <=0;`
255			`else`
256			`Add_rd_ungray <={`
257			`Add_rd_gray_dl1[8],`
258			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7],`
259			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6],`
260			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5],`
261			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4],`
262			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3],`
263			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2],`
264			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1],`
265			`Add_rd_gray_dl1[8]^Add_rd_gray_dl1[7]^Add_rd_gray_dl1[6]^Add_rd_gray_dl1[5]^Add_rd_gray_dl1[4]^Add_rd_gray_dl1[3]^Add_rd_gray_dl1[2]^Add_rd_gray_dl1[1]^Add_rd_gray_dl1[0] };`
266
267			`assign Add_wr_pluse=Add_wr+1;`
268
269			`always @ (posedge Clk_MAC or posedge Reset)`
270			`if (Reset)`
271			`Full <=0;`
272			`else if (Add_wr_pluse==Add_rd_ungray)`
273			`Full <=1;`
274			`else`
275			`Full <=0;`
276
277			`assign Fifo_full =Full;`
278
279			`//`
280			`always @ (posedge Clk_MAC or posedge Reset)`
281			`if (Reset)`
282			`Add_wr <=0;`
283			`else if (Current_state==State_err_end)`
284			`Add_wr <=Add_wr_reg;`
285			`else if (Wr_en&&!Full)`
286			`Add_wr <=Add_wr +1;`
287
288			`//`
289			`always @ (posedge Clk_MAC or posedge Reset)`
290			`if (Reset)`
291			`Fifo_data_en_dl1 <=0;`
292			`else`
293			`Fifo_data_en_dl1 <=Fifo_data_en;`
294
295			`always @ (posedge Clk_MAC or posedge Reset)`
296			`if (Reset)`
297			`Fifo_data_dl1 <=0;`
298			`else`
299			`Fifo_data_dl1 <=Fifo_data;`
300
301			`always @ (posedge Clk_MAC or posedge Reset)`
302			`if (Reset)`
303			`Fifo_data_byte3 <=0;`
304			`else if (Current_state==State_byte3&&Fifo_data_en_dl1)`
305			`Fifo_data_byte3 <=Fifo_data_dl1;`
306
307			`always @ (posedge Clk_MAC or posedge Reset)`
308			`if (Reset)`
309			`Fifo_data_byte2 <=0;`
310			`else if (Current_state==State_byte2&&Fifo_data_en_dl1)`
311			`Fifo_data_byte2 <=Fifo_data_dl1;`
312
313			`always @ (posedge Clk_MAC or posedge Reset)`
314			`if (Reset)`
315			`Fifo_data_byte1 <=0;`
316			`else if (Current_state==State_byte1&&Fifo_data_en_dl1)`
317			`Fifo_data_byte1 <=Fifo_data_dl1;`
318
319	6	maverickis	`always @ (Current_state or Fifo_data_byte3 or Fifo_data_byte2 or Fifo_data_byte1 )`
320	5	maverickis	`case (Current_state)`
321			`State_be0:`
322	6	maverickis	`Din ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
323	5	maverickis	`State_be1:`
324			`Din ={4'b1001,Fifo_data_byte3,24'h0};`
325			`State_be2:`
326			`Din ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};`
327			`State_be3:`
328			`Din ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};`
329			`default:`
330	6	maverickis	`Din ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
331	5	maverickis	`endcase`
332
333			`always @ (Current_state or Fifo_data_en)`
334			`if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
335			`Current_state==State_be2\|\|Current_state==State_be3\|\|`
336			`(Current_state==State_byte0&&Fifo_data_en))`
337			`Wr_en <=1;`
338			`else`
339			`Wr_en <=0;`
340			`//this signal for read side to handle the packet number in fifo`
341			`always @ (posedge Clk_MAC or posedge Reset)`
342			`if (Reset)`
343	6	maverickis	`Packet_number_add_tmp <=0;`
344	5	maverickis	`else if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
345			`Current_state==State_be2\|\|Current_state==State_be3)`
346	6	maverickis	`Packet_number_add_tmp <=1;`
347			`else`
348			`Packet_number_add_tmp <=0;`
349
350			`always @ (posedge Clk_MAC or posedge Reset)`
351			`if (Reset)`
352			`begin`
353			`Packet_number_add_tmp_dl1 <=0;`
354			`Packet_number_add_tmp_dl2 <=0;`
355			`end`
356			`else`
357			`begin`
358			`Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;`
359			`Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;`
360			`end`
361
362			`//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.`
363			`//expand to two cycles long almost=16 ns`
364			`//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles`
365			`always @ (posedge Clk_MAC or posedge Reset)`
366			`if (Reset)`
367			`Packet_number_add <=0;`
368			`else if (Packet_number_add_tmp_dl1\|\|Packet_number_add_tmp_dl2)`
369	5	maverickis	`Packet_number_add <=1;`
370			`else`
371			`Packet_number_add <=0;`
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396			`//******************************************************************************`
397			`//domain Clk_SYS,read data from dprom.b-port for read`
398			`//******************************************************************************`
399
400
401			`always @ (posedge Clk_SYS or posedge Reset)`
402			`if (Reset)`
403			`Current_state_SYS <=SYS_idle;`
404			`else`
405			`Current_state_SYS <=Next_state_SYS;`
406
407			`always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)`
408			`case (Current_state_SYS)`
409			`SYS_idle:`
410			`if (Rx_mac_rd&&Rx_mac_ra)`
411			`Next_state_SYS =SYS_read;`
412			`else`
413			`Next_state_SYS =Current_state_SYS;`
414			`SYS_read:`
415			`if (Dout[35])`
416			`Next_state_SYS =SYS_wait_end;`
417			`// else if (Empty)`
418			`// Next_state_SYS =FF_emtpy_err;`
419			`else`
420			`Next_state_SYS =Current_state_SYS;`
421			`FF_emtpy_err:`
422			`if (!Empty)`
423			`Next_state_SYS =SYS_read;`
424			`else`
425			`Next_state_SYS =Current_state_SYS;`
426			`SYS_wait_end:`
427			`if (!Rx_mac_rd)`
428			`Next_state_SYS =SYS_idle;`
429			`else`
430			`Next_state_SYS =Current_state_SYS;`
431			`default:`
432			`Next_state_SYS =SYS_idle;`
433			`endcase`
434
435
436			`//gen Rx_mac_ra`
437			`always @ (posedge Clk_SYS or posedge Reset)`
438			`if (Reset)`
439			`begin`
440			`Packet_number_add_dl1 <=0;`
441			`Packet_number_add_dl2 <=0;`
442			`end`
443			`else`
444			`begin`
445			`Packet_number_add_dl1 <=Packet_number_add;`
446			`Packet_number_add_dl2 <=Packet_number_add_dl1;`
447			`end`
448			`assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;`
449
450			`always @ (Current_state_SYS or Next_state_SYS)`
451			`if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)`
452			`Packet_number_sub =1;`
453			`else`
454			`Packet_number_sub =0;`
455
456			`always @ (posedge Clk_SYS or posedge Reset)`
457			`if (Reset)`
458			`Packet_number_inFF <=0;`
459			`else if (Packet_number_add_edge&&!Packet_number_sub)`
460			`Packet_number_inFF <=Packet_number_inFF + 1;`
461			`else if (!Packet_number_add_edge&&Packet_number_sub)`
462			`Packet_number_inFF <=Packet_number_inFF - 1;`
463
464			`always @ (Packet_number_inFF)`
465			`if (Packet_number_inFF==0)`
466			`Rx_mac_ra =0;`
467			`else`
468			`Rx_mac_ra =1;`
469
470			`//control Add_rd signal;`
471			`always @ (posedge Clk_SYS or posedge Reset)`
472			`if (Reset)`
473			`Add_rd <=0;`
474			`else if (Current_state_SYS==SYS_read&&!Dout[35])`
475			`Add_rd <=Add_rd + 1;`
476
477			`//`
478			`always @ (posedge Reset or posedge Clk_SYS)`
479			`if (Reset)`
480			`Add_rd_gray <=0;`
481			`else`
482			`Add_rd_gray <={ Add_rd[8],`
483			`Add_rd[8]^Add_rd[7],`
484			`Add_rd[7]^Add_rd[6],`
485			`Add_rd[6]^Add_rd[5],`
486			`Add_rd[5]^Add_rd[4],`
487			`Add_rd[4]^Add_rd[3],`
488			`Add_rd[3]^Add_rd[2],`
489			`Add_rd[2]^Add_rd[1],`
490			`Add_rd[1]^Add_rd[0]};`
491			`//`
492
493			`always @ (posedge Clk_SYS or posedge Reset)`
494			`if (Reset)`
495			`Add_wr_gray_dl1 <=0;`
496			`else`
497			`Add_wr_gray_dl1 <=Add_wr_gray;`
498
499			`always @ (posedge Clk_SYS or posedge Reset)`
500			`if (Reset)`
501			`Add_wr_ungray <=0;`
502			`else`
503			`Add_wr_ungray <={`
504			`Add_wr_gray_dl1[8],`
505			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],`
506			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],`
507			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],`
508			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],`
509			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],`
510			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],`
511			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],`
512			`Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };`
513
514			`//empty signal gen`
515			`always @ (posedge Clk_SYS or posedge Reset)`
516			`if (Reset)`
517			`Empty <=1;`
518			`else if (Add_rd==Add_wr_ungray)`
519			`Empty <=1;`
520			`else`
521			`Empty <=0;`
522
523
524
525			`always @ (posedge Clk_SYS or posedge Reset)`
526			`if (Reset)`
527			`Dout_dl1 <=0;`
528			`else`
529			`Dout_dl1 <=Dout;`
530
531			`assign Rx_mac_data =Dout_dl1[31:0];`
532
533			`always @ (RX_APPEND_CRC or Dout_dl1 or Dout)`
534			`if (RX_APPEND_CRC)`
535			`Rx_mac_BE =Dout_dl1[33:32];`
536			`else`
537			`Rx_mac_BE =Dout[33:32];`
538
539
540			`always @ (posedge Clk_SYS or posedge Reset)`
541			`if (Reset)`
542			`Rx_mac_pa <=0;`
543			`else if (Rx_mac_sop_tmp_dl1&&Next_state_SYS==SYS_read)`
544			`Rx_mac_pa <=1;`
545			`else if(Rx_mac_eop)`
546			`Rx_mac_pa <=0;`
547
548
549
550			`always @ (posedge Clk_SYS or posedge Reset)`
551			`if (Reset)`
552			`Rx_mac_sop_tmp <=0;`
553			`else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)`
554			`Rx_mac_sop_tmp <=1;`
555			`else`
556			`Rx_mac_sop_tmp <=0;`
557
558
559
560			`always @ (posedge Clk_SYS or posedge Reset)`
561			`if (Reset)`
562			`begin`
563			`Rx_mac_sop_tmp_dl1 <=0;`
564			`Rx_mac_sop <=0;`
565			`end`
566			`else`
567			`begin`
568			`Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;`
569			`Rx_mac_sop <=Rx_mac_sop_tmp_dl1;`
570			`end`
571
572
573			`always @(RX_APPEND_CRC or Dout_dl1 or Dout)`
574			`if(RX_APPEND_CRC)`
575			`Rx_mac_eop =Dout_dl1[35];`
576			`else`
577			`Rx_mac_eop =Dout[35];`
578			`//******************************************************************************`
579
580			`duram #(36,9,"M4K") U_duram(`
581			`.data_a (Din ),`
582			`.wren_a (Wr_en ),`
583			`.address_a (Add_wr ),`
584			`.address_b (Add_rd ),`
585			`.clock_a (Clk_MAC ),`
586			`.clock_b (Clk_SYS ),`
587			`.q_b (Dout ));`
588
589			`endmodule`
590
591
592
593
594