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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_rx/] [MAC_rx_ctrl.v] - Blame information for rev 6

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_rx_ctrl.v                                               ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//                                           
 
module MAC_rx_ctrl (
Reset   ,
Clk         ,
 
//RMII interface                                    
MCrs_dv ,               //
MRxD    ,               //  
MRxErr  ,               //  
//CRC_chk interface                                 
CRC_en    ,
CRC_init  ,
CRC_err  ,
//MAC_rx_add_chk interface                          
MAC_add_en                      ,
MAC_rx_add_chk_err      ,
//broadcast_filter     
broadcast_ptr   ,
broadcast_drop  ,
//flow_control signals      
pause_quanta            ,
pause_quanta_val        ,
//MAC_rx_FF interface                               
Fifo_data               ,
Fifo_data_en    ,
Fifo_data_err   ,
Fifo_data_end   ,
Fifo_full               ,
//RMON interface                
Rx_pkt_type_rmon                ,
Rx_pkt_length_rmon              ,
Rx_apply_rmon           ,
Rx_pkt_err_type_rmon    ,
//CPU                                         
RX_IFG_SET        ,
RX_MAX_LENGTH,
RX_MIN_LENGTH
 
);
 
input                   Reset   ;
input                   Clk         ;
                                //RMII interface  
input                   MCrs_dv ;
input   [7:0]    MRxD    ;
input                   MRxErr  ;
                                //CRC_chk interface
output                  CRC_en  ;
output                  CRC_init;
input           CRC_err ;
                                //MAC_rx_add_chk interface
output                  MAC_add_en                      ;
input                   MAC_rx_add_chk_err      ;
                                //broadcast_filter
output                  broadcast_ptr           ;
input                   broadcast_drop          ;
                                //flow_control signals  
output  [15:0]   pause_quanta            ;
output                  pause_quanta_val        ;
                                //MAC_rx_FF interface
output  [7:0]    Fifo_data               ;
output                  Fifo_data_en    ;
output                  Fifo_data_err   ;
output                  Fifo_data_end   ;
input                   Fifo_full;
                                //RMON interface
output  [15:0]   Rx_pkt_length_rmon              ;
output                  Rx_apply_rmon           ;
output  [2:0]    Rx_pkt_err_type_rmon    ;
output  [2:0]    Rx_pkt_type_rmon                ;
                                //CPU
input   [5:0]    RX_IFG_SET        ;
input   [15:0]   RX_MAX_LENGTH   ;//     1518
input   [6:0]    RX_MIN_LENGTH   ;//     64
 
//******************************************************************************
//internal signals
//******************************************************************************
parameter               State_idle                      =4'd00;
parameter               State_preamble      =4'd01;
parameter               State_SFD           =4'd02;
parameter               State_data          =4'd03;
parameter               State_checkCRC      =4'd04;
parameter               State_OkEnd                     =4'd07;
parameter               State_drop          =4'd08;
parameter               State_ErrEnd            =4'd09;
parameter               State_CRCErrEnd         =4'd10;
parameter               State_FFFullDrop        =4'd11;
parameter               State_FFFullErrEnd      =4'd12;
parameter               State_IFG           =4'd13;
 
parameter               Pause_idle          =4'd0;
parameter               Pause_pre_syn       =4'd1;
parameter               Pause_quanta_hi     =4'd2;
parameter               Pause_quanta_lo     =4'd3;
parameter               Pause_syn           =4'd4;
 
reg     [3:0]            Current_state /* synthesis syn_keep=1 */;
reg     [3:0]            Next_state;
reg     [3:0]            Pause_current /* synthesis syn_keep=1 */;
reg     [3:0]            Pause_next;
reg     [5:0]            IFG_counter;
reg                             Crs_dv  ;
reg     [7:0]            RxD     ;
reg     [7:0]            RxD_dl1 ;
reg                             RxErr   ;
reg     [15:0]           Frame_length_counter;
reg                             Too_long;
reg                             Too_short;
reg                             Fifo_data_en;
reg                             Fifo_data_end;
reg                             Fifo_data_err;
reg                             CRC_en;
reg                             CRC_init;
reg                             Rx_apply_rmon;
reg     [2:0]            Rx_pkt_err_type_rmon;
reg                             MAC_add_en;
reg     [2:0]            Rx_pkt_type_rmon;
reg     [7:0]            pause_quanta_h          ;
reg     [15:0]           pause_quanta            ;
reg                             pause_quanta_val        ;
reg                             pause_quanta_val_tmp;
reg                             pause_frame_ptr         ;
reg                             broadcast_ptr           ;
//******************************************************************************
//delay signals                                                          
//******************************************************************************
 
always @ (posedge Reset or posedge Clk)
        if (Reset)
                begin
                        Crs_dv          <=0;
                        RxD                     <=0;
            RxErr               <=0;
        end
    else
        begin
                        Crs_dv          <=MCrs_dv       ;
                        RxD                     <=MRxD          ;
            RxErr       <=MRxErr        ;
        end
 
always @ (posedge Reset or posedge Clk)
        if (Reset)
                RxD_dl1         <=0;
        else
                RxD_dl1         <=RxD;
 
//******************************************************************************
//State_machine                                                           
//******************************************************************************
 
always @ (posedge Reset or posedge Clk)
        if (Reset)
                Current_state   <=State_idle;
        else
                Current_state   <=Next_state;
 
always @ (*)
                case (Current_state)
                        State_idle:
                                        if (Crs_dv&&RxD==8'h55)
                                                Next_state      =State_preamble;
                                        else
                                                Next_state      =Current_state;
                        State_preamble:
                                        if (!Crs_dv)
                                                Next_state      =State_ErrEnd;
                                        else if (RxErr)
                                                Next_state      =State_drop;
                                        else if (RxD==8'hd5)
                                                Next_state      =State_SFD;
                                        else if (RxD==8'h55)
                                                Next_state      =Current_state;
                                        else
                                                Next_state      =State_drop;
                        State_SFD:
                                        if (!Crs_dv)
                                                Next_state      =State_ErrEnd;
                                        else if (RxErr)
                                                Next_state      =State_drop;
                                        else
                                                Next_state      =State_data;
                        State_data:
                                        if (!Crs_dv&&!Too_short&&!Too_long)
                                                Next_state      =State_checkCRC;
                                        else if (!Crs_dv&&(Too_short||Too_long))
                                                Next_state      =State_ErrEnd;
                                        else if (Fifo_full)
                                                Next_state      =State_FFFullErrEnd;
                                        else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop)
                                                Next_state      =State_drop;
                                        else
                                                Next_state      =State_data;
                        State_checkCRC:
                                         if (CRC_err)
                                                Next_state      =State_CRCErrEnd;
                                         else
                                                Next_state      =State_OkEnd;
                        State_drop:
                                        if (!Crs_dv)
                                                Next_state      =State_ErrEnd;
                                        else
                                                Next_state      =Current_state;
                        State_OkEnd:
                                                Next_state      =State_IFG;
                        State_ErrEnd:
                                                Next_state      =State_IFG;
 
                        State_CRCErrEnd:
                                                Next_state      =State_IFG;
                        State_FFFullDrop:
                                        if (!Crs_dv)
                                                Next_state      =State_IFG;
                                        else
                                                Next_state      =Current_state;
                        State_FFFullErrEnd:
                                                Next_state      =State_FFFullDrop;
                        State_IFG:
                                        if (IFG_counter==RX_IFG_SET)
                                                Next_state      =State_idle;
                                        else
                                                Next_state      =Current_state;
 
                        default:
                                                Next_state      =State_idle;
                endcase
 
 
always @ (posedge Reset or posedge Clk)
        if (Reset)
                IFG_counter             <=0;
        else if (Current_state!=State_IFG)
                IFG_counter             <=0;
        else
                IFG_counter             <=IFG_counter + 1;
//******************************************************************************
//gen fifo interface signals                                                     
//******************************************************************************                     
 
assign  Fifo_data       =RxD_dl1;
 
always @(Current_state)
        if  (Current_state==State_data)
                Fifo_data_en            =1;
        else
                Fifo_data_en            =0;
 
always @(Current_state)
        if      (Current_state==State_ErrEnd||Current_state==State_OkEnd
                 ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
                Fifo_data_end           =1;
        else
                Fifo_data_end           =0;
 
always @(Current_state)
        if      (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
                Fifo_data_err           =1;
        else
                Fifo_data_err           =0;
 
//******************************************************************************
//CRC_chk interface                                               
//****************************************************************************** 
 
always @(Current_state)
        if (Current_state==State_data)
                CRC_en  =1;
        else
                CRC_en  =0;
 
always @(Current_state)
        if (Current_state==State_SFD)
                CRC_init        =1;
        else
                CRC_init        =0;
 
//******************************************************************************
//gen rmon signals                                         
//******************************************************************************        
always @ (posedge Clk or posedge Reset)
        if (Reset)
                Frame_length_counter            <=0;
        else if (Current_state==State_SFD)
                Frame_length_counter            <=1;
        else if (Current_state==State_data)
                Frame_length_counter            <=Frame_length_counter+ 1;
 
always @ (Frame_length_counter or RX_MIN_LENGTH)
        if (Frame_length_counter<RX_MIN_LENGTH)
                Too_short       =1;
        else
                Too_short       =0;
 
always @ (*)
        if (Frame_length_counter>RX_MAX_LENGTH)
                Too_long        =1;
        else
                Too_long        =0;
 
assign Rx_pkt_length_rmon=Frame_length_counter;
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                Rx_apply_rmon   <=0;
        else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
                ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
                Rx_apply_rmon   <=1;
        else
                Rx_apply_rmon   <=0;
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                Rx_pkt_err_type_rmon    <=0;
        else if (Current_state==State_CRCErrEnd)
                Rx_pkt_err_type_rmon    <=3'b001        ;//
        else if (Current_state==State_FFFullErrEnd)
                Rx_pkt_err_type_rmon    <=3'b010        ;// 
        else if (Current_state==State_ErrEnd)
                Rx_pkt_err_type_rmon    <=3'b011        ;//
        else if(Current_state==State_OkEnd)
                Rx_pkt_err_type_rmon    <=3'b100        ;
 
 
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                Rx_pkt_type_rmon                <=0;
        else if (Current_state==State_OkEnd&&pause_frame_ptr)
                Rx_pkt_type_rmon                <=3'b100        ;//
        else if(Current_state==State_SFD&&Next_state==State_data)
                Rx_pkt_type_rmon                <={1'b0,MRxD[7:6]};
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                broadcast_ptr   <=0;
        else if(Current_state==State_IFG)
                broadcast_ptr   <=0;
        else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)
                broadcast_ptr   <=1;
 
 
 
//******************************************************************************
//MAC add checker signals                                                              
//******************************************************************************
always @ (Frame_length_counter or Fifo_data_en)
        if(Frame_length_counter>=0&&Frame_length_counter<=5)
                MAC_add_en      <=Fifo_data_en;
        else
                MAC_add_en      <=0;
 
//******************************************************************************
//flow control signals                                                            
//******************************************************************************
always @ (posedge Clk or posedge Reset)
        if (Reset)
                Pause_current   <=Pause_idle;
        else
                Pause_current   <=Pause_next;
 
always @ (*)
        case (Pause_current)
                Pause_idle      :
                        if(Current_state==State_SFD)
                                Pause_next      =Pause_pre_syn;
                        else
                                Pause_next      =Pause_current;
                Pause_pre_syn:
                        case (Frame_length_counter)
                                16'd0:  if (RxD_dl1==8'h01)
                                                        Pause_next      =Pause_current;
                                                else
                                                        Pause_next      =Pause_idle;
                                16'd1:  if (RxD_dl1==8'h80)
                                                        Pause_next      =Pause_current;
                                                else
                                                        Pause_next      =Pause_idle;
                                16'd2:  if (RxD_dl1==8'hc2)
                                                        Pause_next      =Pause_current;
                                                else
                                                        Pause_next      =Pause_idle;
                                16'd3:  if (RxD_dl1==8'h00)
                                                        Pause_next      =Pause_current;
                                                else
                                                        Pause_next      =Pause_idle;
                                16'd4:  if (RxD_dl1==8'h00)
                                                        Pause_next      =Pause_current;
                                                else
                                                        Pause_next      =Pause_idle;
                                16'd5:  if (RxD_dl1==8'h01)
                                                        Pause_next      =Pause_current;
                                                else
                                                        Pause_next      =Pause_idle;
                                16'd12: if (RxD_dl1==8'h88)
                                                        Pause_next      =Pause_current;
                                                else
                                                        Pause_next      =Pause_idle;
                                16'd13: if (RxD_dl1==8'h08)
                                                        Pause_next      =Pause_current;
                                                else
                                                        Pause_next      =Pause_idle;
                                16'd14: if (RxD_dl1==8'h00)
                                                        Pause_next      =Pause_current;
                                                else
                                                        Pause_next      =Pause_idle;
                                16'd15: if (RxD_dl1==8'h01)
                                                        Pause_next      =Pause_quanta_hi;
                                                else
                                                        Pause_next      =Pause_idle;
                                default:        Pause_next      =Pause_current;
                        endcase
                Pause_quanta_hi :
                        Pause_next      =Pause_quanta_lo;
                Pause_quanta_lo :
                        Pause_next      =Pause_syn;
                Pause_syn               :
                        if (Current_state==State_IFG)
                                Pause_next      =Pause_idle;
                        else
                                Pause_next      =Pause_current;
                default
                        Pause_next      =Pause_idle;
        endcase
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                pause_quanta_h          <=0;
        else if(Pause_current==Pause_quanta_hi)
                pause_quanta_h          <=RxD_dl1;
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                pause_quanta            <=0;
        else if(Pause_current==Pause_quanta_lo)
                pause_quanta            <={pause_quanta_h,RxD_dl1};
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                pause_quanta_val_tmp    <=0;
        else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)
                pause_quanta_val_tmp    <=1;
        else
                pause_quanta_val_tmp    <=0;
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                pause_quanta_val        <=0;
        else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp)
                pause_quanta_val        <=1;
        else
                pause_quanta_val        <=0;
 
always @ (posedge Clk or posedge Reset)
        if (Reset)
                pause_frame_ptr         <=0;
        else if(Pause_current==Pause_syn)
                pause_frame_ptr         <=1;
        else
                pause_frame_ptr         <=0;
 
endmodule
 
 

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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_rx/] [MAC_rx_ctrl.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_rx_ctrl.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40	6	maverickis	`// $Log: not supported by cvs2svn $`
41			`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
42			`// no message`
43			`//`
44	5	maverickis
45			`module MAC_rx_ctrl (`
46			`Reset ,`
47			`Clk ,`
48
49			`//RMII interface`
50			`MCrs_dv , //`
51			`MRxD , //`
52			`MRxErr , //`
53			`//CRC_chk interface`
54			`CRC_en ,`
55			`CRC_init ,`
56			`CRC_err ,`
57			`//MAC_rx_add_chk interface`
58			`MAC_add_en ,`
59			`MAC_rx_add_chk_err ,`
60			`//broadcast_filter`
61			`broadcast_ptr ,`
62			`broadcast_drop ,`
63			`//flow_control signals`
64			`pause_quanta ,`
65			`pause_quanta_val ,`
66			`//MAC_rx_FF interface`
67			`Fifo_data ,`
68			`Fifo_data_en ,`
69			`Fifo_data_err ,`
70			`Fifo_data_end ,`
71			`Fifo_full ,`
72			`//RMON interface`
73			`Rx_pkt_type_rmon ,`
74			`Rx_pkt_length_rmon ,`
75			`Rx_apply_rmon ,`
76			`Rx_pkt_err_type_rmon ,`
77			`//CPU`
78			`RX_IFG_SET ,`
79			`RX_MAX_LENGTH,`
80			`RX_MIN_LENGTH`
81
82			`);`
83
84			`input Reset ;`
85			`input Clk ;`
86			`//RMII interface`
87			`input MCrs_dv ;`
88			`input [7:0] MRxD ;`
89			`input MRxErr ;`
90			`//CRC_chk interface`
91			`output CRC_en ;`
92			`output CRC_init;`
93			`input CRC_err ;`
94			`//MAC_rx_add_chk interface`
95			`output MAC_add_en ;`
96			`input MAC_rx_add_chk_err ;`
97			`//broadcast_filter`
98			`output broadcast_ptr ;`
99			`input broadcast_drop ;`
100			`//flow_control signals`
101			`output [15:0] pause_quanta ;`
102			`output pause_quanta_val ;`
103			`//MAC_rx_FF interface`
104			`output [7:0] Fifo_data ;`
105			`output Fifo_data_en ;`
106			`output Fifo_data_err ;`
107			`output Fifo_data_end ;`
108			`input Fifo_full;`
109			`//RMON interface`
110			`output [15:0] Rx_pkt_length_rmon ;`
111			`output Rx_apply_rmon ;`
112			`output [2:0] Rx_pkt_err_type_rmon ;`
113			`output [2:0] Rx_pkt_type_rmon ;`
114			`//CPU`
115			`input [5:0] RX_IFG_SET ;`
116			`input [15:0] RX_MAX_LENGTH ;// 1518`
117			`input [6:0] RX_MIN_LENGTH ;// 64`
118
119			`//******************************************************************************`
120			`//internal signals`
121			`//******************************************************************************`
122			`parameter State_idle =4'd00;`
123			`parameter State_preamble =4'd01;`
124			`parameter State_SFD =4'd02;`
125			`parameter State_data =4'd03;`
126	6	maverickis	`parameter State_checkCRC =4'd04;`
127	5	maverickis	`parameter State_OkEnd =4'd07;`
128			`parameter State_drop =4'd08;`
129			`parameter State_ErrEnd =4'd09;`
130			`parameter State_CRCErrEnd =4'd10;`
131			`parameter State_FFFullDrop =4'd11;`
132			`parameter State_FFFullErrEnd =4'd12;`
133			`parameter State_IFG =4'd13;`
134
135			`parameter Pause_idle =4'd0;`
136			`parameter Pause_pre_syn =4'd1;`
137			`parameter Pause_quanta_hi =4'd2;`
138			`parameter Pause_quanta_lo =4'd3;`
139			`parameter Pause_syn =4'd4;`
140
141			`reg [3:0] Current_state /* synthesis syn_keep=1 */;`
142			`reg [3:0] Next_state;`
143			`reg [3:0] Pause_current /* synthesis syn_keep=1 */;`
144			`reg [3:0] Pause_next;`
145			`reg [5:0] IFG_counter;`
146			`reg Crs_dv ;`
147			`reg [7:0] RxD ;`
148			`reg [7:0] RxD_dl1 ;`
149			`reg RxErr ;`
150			`reg [15:0] Frame_length_counter;`
151			`reg Too_long;`
152			`reg Too_short;`
153			`reg Fifo_data_en;`
154			`reg Fifo_data_end;`
155			`reg Fifo_data_err;`
156			`reg CRC_en;`
157			`reg CRC_init;`
158			`reg Rx_apply_rmon;`
159			`reg [2:0] Rx_pkt_err_type_rmon;`
160			`reg MAC_add_en;`
161			`reg [2:0] Rx_pkt_type_rmon;`
162			`reg [7:0] pause_quanta_h ;`
163			`reg [15:0] pause_quanta ;`
164			`reg pause_quanta_val ;`
165			`reg pause_quanta_val_tmp;`
166			`reg pause_frame_ptr ;`
167			`reg broadcast_ptr ;`
168			`//******************************************************************************`
169			`//delay signals`
170			`//******************************************************************************`
171
172			`always @ (posedge Reset or posedge Clk)`
173			`if (Reset)`
174			`begin`
175			`Crs_dv <=0;`
176			`RxD <=0;`
177			`RxErr <=0;`
178			`end`
179			`else`
180			`begin`
181			`Crs_dv <=MCrs_dv ;`
182			`RxD <=MRxD ;`
183			`RxErr <=MRxErr ;`
184			`end`
185
186			`always @ (posedge Reset or posedge Clk)`
187			`if (Reset)`
188			`RxD_dl1 <=0;`
189			`else`
190			`RxD_dl1 <=RxD;`
191
192			`//******************************************************************************`
193			`//State_machine`
194			`//******************************************************************************`
195
196			`always @ (posedge Reset or posedge Clk)`
197			`if (Reset)`
198			`Current_state <=State_idle;`
199			`else`
200			`Current_state <=Next_state;`
201
202			`always @ (*)`
203			`case (Current_state)`
204			`State_idle:`
205			`if (Crs_dv&&RxD==8'h55)`
206			`Next_state =State_preamble;`
207			`else`
208			`Next_state =Current_state;`
209			`State_preamble:`
210			`if (!Crs_dv)`
211			`Next_state =State_ErrEnd;`
212			`else if (RxErr)`
213			`Next_state =State_drop;`
214			`else if (RxD==8'hd5)`
215			`Next_state =State_SFD;`
216			`else if (RxD==8'h55)`
217			`Next_state =Current_state;`
218			`else`
219			`Next_state =State_drop;`
220			`State_SFD:`
221			`if (!Crs_dv)`
222			`Next_state =State_ErrEnd;`
223			`else if (RxErr)`
224			`Next_state =State_drop;`
225			`else`
226			`Next_state =State_data;`
227			`State_data:`
228	6	maverickis	`if (!Crs_dv&&!Too_short&&!Too_long)`
229			`Next_state =State_checkCRC;`
230	5	maverickis	`else if (!Crs_dv&&(Too_short\|\|Too_long))`
231			`Next_state =State_ErrEnd;`
232			`else if (Fifo_full)`
233			`Next_state =State_FFFullErrEnd;`
234			`else if (RxErr\|\|MAC_rx_add_chk_err\|\|Too_long\|\|broadcast_drop)`
235			`Next_state =State_drop;`
236			`else`
237	6	maverickis	`Next_state =State_data;`
238			`State_checkCRC:`
239			`if (CRC_err)`
240			`Next_state =State_CRCErrEnd;`
241			`else`
242			`Next_state =State_OkEnd;`
243	5	maverickis	`State_drop:`
244			`if (!Crs_dv)`
245			`Next_state =State_ErrEnd;`
246			`else`
247			`Next_state =Current_state;`
248			`State_OkEnd:`
249			`Next_state =State_IFG;`
250			`State_ErrEnd:`
251			`Next_state =State_IFG;`
252
253			`State_CRCErrEnd:`
254			`Next_state =State_IFG;`
255			`State_FFFullDrop:`
256			`if (!Crs_dv)`
257			`Next_state =State_IFG;`
258			`else`
259			`Next_state =Current_state;`
260			`State_FFFullErrEnd:`
261			`Next_state =State_FFFullDrop;`
262			`State_IFG:`
263			`if (IFG_counter==RX_IFG_SET)`
264			`Next_state =State_idle;`
265			`else`
266			`Next_state =Current_state;`
267
268			`default:`
269			`Next_state =State_idle;`
270			`endcase`
271
272
273			`always @ (posedge Reset or posedge Clk)`
274			`if (Reset)`
275			`IFG_counter <=0;`
276			`else if (Current_state!=State_IFG)`
277			`IFG_counter <=0;`
278			`else`
279			`IFG_counter <=IFG_counter + 1;`
280			`//******************************************************************************`
281			`//gen fifo interface signals`
282			`//******************************************************************************`
283
284			`assign Fifo_data =RxD_dl1;`
285
286			`always @(Current_state)`
287			`if (Current_state==State_data)`
288			`Fifo_data_en =1;`
289			`else`
290			`Fifo_data_en =0;`
291
292			`always @(Current_state)`
293			`if (Current_state==State_ErrEnd\|\|Current_state==State_OkEnd`
294			`\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
295			`Fifo_data_end =1;`
296			`else`
297			`Fifo_data_end =0;`
298
299			`always @(Current_state)`
300			`if (Current_state==State_ErrEnd\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
301			`Fifo_data_err =1;`
302			`else`
303			`Fifo_data_err =0;`
304
305			`//******************************************************************************`
306			`//CRC_chk interface`
307			`//******************************************************************************`
308
309			`always @(Current_state)`
310			`if (Current_state==State_data)`
311			`CRC_en =1;`
312			`else`
313			`CRC_en =0;`
314
315			`always @(Current_state)`
316			`if (Current_state==State_SFD)`
317			`CRC_init =1;`
318			`else`
319			`CRC_init =0;`
320
321			`//******************************************************************************`
322			`//gen rmon signals`
323			`//******************************************************************************`
324			`always @ (posedge Clk or posedge Reset)`
325			`if (Reset)`
326			`Frame_length_counter <=0;`
327			`else if (Current_state==State_SFD)`
328	6	maverickis	`Frame_length_counter <=1;`
329	5	maverickis	`else if (Current_state==State_data)`
330			`Frame_length_counter <=Frame_length_counter+ 1;`
331
332			`always @ (Frame_length_counter or RX_MIN_LENGTH)`
333			`if (Frame_length_counter<RX_MIN_LENGTH)`
334			`Too_short =1;`
335			`else`
336			`Too_short =0;`
337
338			`always @ (*)`
339			`if (Frame_length_counter>RX_MAX_LENGTH)`
340			`Too_long =1;`
341			`else`
342			`Too_long =0;`
343
344			`assign Rx_pkt_length_rmon=Frame_length_counter;`
345
346			`always @ (posedge Clk or posedge Reset)`
347			`if (Reset)`
348			`Rx_apply_rmon <=0;`
349			`else if (Current_state==State_OkEnd\|\|Current_state==State_ErrEnd`
350			`\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
351			`Rx_apply_rmon <=1;`
352			`else`
353			`Rx_apply_rmon <=0;`
354
355			`always @ (posedge Clk or posedge Reset)`
356			`if (Reset)`
357			`Rx_pkt_err_type_rmon <=0;`
358			`else if (Current_state==State_CRCErrEnd)`
359			`Rx_pkt_err_type_rmon <=3'b001 ;//`
360			`else if (Current_state==State_FFFullErrEnd)`
361			`Rx_pkt_err_type_rmon <=3'b010 ;//`
362			`else if (Current_state==State_ErrEnd)`
363			`Rx_pkt_err_type_rmon <=3'b011 ;//`
364			`else if(Current_state==State_OkEnd)`
365			`Rx_pkt_err_type_rmon <=3'b100 ;`
366
367
368
369			`always @ (posedge Clk or posedge Reset)`
370			`if (Reset)`
371			`Rx_pkt_type_rmon <=0;`
372			`else if (Current_state==State_OkEnd&&pause_frame_ptr)`
373			`Rx_pkt_type_rmon <=3'b100 ;//`
374			`else if(Current_state==State_SFD&&Next_state==State_data)`
375			`Rx_pkt_type_rmon <={1'b0,MRxD[7:6]};`
376
377			`always @ (posedge Clk or posedge Reset)`
378			`if (Reset)`
379			`broadcast_ptr <=0;`
380			`else if(Current_state==State_IFG)`
381			`broadcast_ptr <=0;`
382			`else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)`
383			`broadcast_ptr <=1;`
384
385
386
387			`//******************************************************************************`
388			`//MAC add checker signals`
389			`//******************************************************************************`
390			`always @ (Frame_length_counter or Fifo_data_en)`
391			`if(Frame_length_counter>=0&&Frame_length_counter<=5)`
392			`MAC_add_en <=Fifo_data_en;`
393			`else`
394			`MAC_add_en <=0;`
395
396			`//******************************************************************************`
397			`//flow control signals`
398			`//******************************************************************************`
399			`always @ (posedge Clk or posedge Reset)`
400			`if (Reset)`
401			`Pause_current <=Pause_idle;`
402			`else`
403			`Pause_current <=Pause_next;`
404
405			`always @ (*)`
406			`case (Pause_current)`
407			`Pause_idle :`
408			`if(Current_state==State_SFD)`
409			`Pause_next =Pause_pre_syn;`
410			`else`
411			`Pause_next =Pause_current;`
412			`Pause_pre_syn:`
413			`case (Frame_length_counter)`
414			`16'd0: if (RxD_dl1==8'h01)`
415			`Pause_next =Pause_current;`
416			`else`
417			`Pause_next =Pause_idle;`
418			`16'd1: if (RxD_dl1==8'h80)`
419			`Pause_next =Pause_current;`
420			`else`
421			`Pause_next =Pause_idle;`
422			`16'd2: if (RxD_dl1==8'hc2)`
423			`Pause_next =Pause_current;`
424			`else`
425			`Pause_next =Pause_idle;`
426			`16'd3: if (RxD_dl1==8'h00)`
427			`Pause_next =Pause_current;`
428			`else`
429			`Pause_next =Pause_idle;`
430			`16'd4: if (RxD_dl1==8'h00)`
431			`Pause_next =Pause_current;`
432			`else`
433			`Pause_next =Pause_idle;`
434			`16'd5: if (RxD_dl1==8'h01)`
435			`Pause_next =Pause_current;`
436			`else`
437			`Pause_next =Pause_idle;`
438			`16'd12: if (RxD_dl1==8'h88)`
439			`Pause_next =Pause_current;`
440			`else`
441			`Pause_next =Pause_idle;`
442			`16'd13: if (RxD_dl1==8'h08)`
443			`Pause_next =Pause_current;`
444			`else`
445			`Pause_next =Pause_idle;`
446			`16'd14: if (RxD_dl1==8'h00)`
447			`Pause_next =Pause_current;`
448			`else`
449			`Pause_next =Pause_idle;`
450			`16'd15: if (RxD_dl1==8'h01)`
451			`Pause_next =Pause_quanta_hi;`
452			`else`
453			`Pause_next =Pause_idle;`
454			`default: Pause_next =Pause_current;`
455			`endcase`
456			`Pause_quanta_hi :`
457			`Pause_next =Pause_quanta_lo;`
458			`Pause_quanta_lo :`
459			`Pause_next =Pause_syn;`
460			`Pause_syn :`
461			`if (Current_state==State_IFG)`
462			`Pause_next =Pause_idle;`
463			`else`
464			`Pause_next =Pause_current;`
465			`default`
466			`Pause_next =Pause_idle;`
467			`endcase`
468
469			`always @ (posedge Clk or posedge Reset)`
470			`if (Reset)`
471			`pause_quanta_h <=0;`
472			`else if(Pause_current==Pause_quanta_hi)`
473			`pause_quanta_h <=RxD_dl1;`
474
475			`always @ (posedge Clk or posedge Reset)`
476			`if (Reset)`
477			`pause_quanta <=0;`
478			`else if(Pause_current==Pause_quanta_lo)`
479			`pause_quanta <={pause_quanta_h,RxD_dl1};`
480
481			`always @ (posedge Clk or posedge Reset)`
482			`if (Reset)`
483			`pause_quanta_val_tmp <=0;`
484			`else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)`
485			`pause_quanta_val_tmp <=1;`
486			`else`
487			`pause_quanta_val_tmp <=0;`
488
489			`always @ (posedge Clk or posedge Reset)`
490			`if (Reset)`
491			`pause_quanta_val <=0;`
492			`else if(Current_state==State_OkEnd&&Pause_current==Pause_syn\|\|pause_quanta_val_tmp)`
493			`pause_quanta_val <=1;`
494			`else`
495			`pause_quanta_val <=0;`
496
497			`always @ (posedge Clk or posedge Reset)`
498			`if (Reset)`
499			`pause_frame_ptr <=0;`
500			`else if(Pause_current==Pause_syn)`
501			`pause_frame_ptr <=1;`
502			`else`
503			`pause_frame_ptr <=0;`
504
505			`endmodule`
506
507