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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_top.v] - Blame information for rev 33

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1 5 maverickis
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  MAC_top.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
7
////                                                              ////
8
////  Author(s):                                                  ////
9 7 maverickis
////      - Jon Gao (gaojon@yahoo.com)                            ////
10 5 maverickis
////                                                              ////
11
////                                                              ////
12
//////////////////////////////////////////////////////////////////////
13
////                                                              ////
14
//// Copyright (C) 2001 Authors                                   ////
15
////                                                              ////
16
//// This source file may be used and distributed without         ////
17
//// restriction provided that this copyright statement is not    ////
18
//// removed from the file and that any derivative work contains  ////
19
//// the original copyright notice and the associated disclaimer. ////
20
////                                                              ////
21
//// This source file is free software; you can redistribute it   ////
22
//// and/or modify it under the terms of the GNU Lesser General   ////
23
//// Public License as published by the Free Software Foundation; ////
24
//// either version 2.1 of the License, or (at your option) any   ////
25
//// later version.                                               ////
26
////                                                              ////
27
//// This source is distributed in the hope that it will be       ////
28
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
29
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
30
//// PURPOSE.  See the GNU Lesser General Public License for more ////
31
//// details.                                                     ////
32
////                                                              ////
33
//// You should have received a copy of the GNU Lesser General    ////
34
//// Public License along with this source; if not, download it   ////
35
//// from http://www.opencores.org/lgpl.shtml                     ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
//                                                                    
39
// CVS Revision History                                               
40
//                                                                    
41 6 maverickis
// $Log: not supported by cvs2svn $
42 28 maverickis
// Revision 1.3  2006/01/19 14:07:52  maverickist
43
// verification is complete.
44
//
45 7 maverickis
// Revision 1.2  2005/12/16 06:44:13  Administrator
46
// replaced tab with space.
47
// passed 9.6k length frame test.
48
//
49 6 maverickis
// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
50
// no message
51
// 
52 5 maverickis
 
53
module MAC_top(
54 7 maverickis
                //system signals
55
input           Reset                   ,
56
input           Clk_125M                ,
57
input           Clk_user                ,
58
input           Clk_reg                 ,
59
output  [2:0]   Speed                   ,
60
                //user interface 
61
output          Rx_mac_ra               ,
62
input           Rx_mac_rd               ,
63
output  [31:0]  Rx_mac_data             ,
64
output  [1:0]   Rx_mac_BE               ,
65
output          Rx_mac_pa               ,
66
output          Rx_mac_sop              ,
67
output          Rx_mac_eop              ,
68
                //user interface 
69
output          Tx_mac_wa               ,
70
input           Tx_mac_wr               ,
71
input   [31:0]  Tx_mac_data             ,
72
input   [1:0]   Tx_mac_BE               ,//big endian
73
input           Tx_mac_sop              ,
74
input           Tx_mac_eop              ,
75 28 maverickis
                //pkg_lgth fifo
76
input           Pkg_lgth_fifo_rd        ,
77
output          Pkg_lgth_fifo_ra        ,
78
output  [15:0]  Pkg_lgth_fifo_data      ,
79 7 maverickis
                //Phy interface          
80
                //Phy interface         
81
output          Gtx_clk                 ,//used only in GMII mode
82
input           Rx_clk                  ,
83
input           Tx_clk                  ,//used only in MII mode
84
output          Tx_er                   ,
85
output          Tx_en                   ,
86
output  [7:0]   Txd                     ,
87
input           Rx_er                   ,
88
input           Rx_dv                   ,
89
input   [7:0]   Rxd                     ,
90
input           Crs                     ,
91
input           Col                     ,
92
                //host interface
93
input           CSB                     ,
94
input           WRB                     ,
95
input   [15:0]  CD_in                   ,
96
output  [15:0]  CD_out                  ,
97
input   [7:0]   CA                      ,
98
                //mdx
99 28 maverickis
output          Mdo,                // MII Management Data Output
100
output          MdoEn,              // MII Management Data Output Enable
101
input           Mdi,
102 7 maverickis
output          Mdc                      // MII Management Data Clock       
103 5 maverickis
 
104
);
105
//******************************************************************************
106
//internal signals                                                              
107
//******************************************************************************
108 7 maverickis
                //RMON interface
109
wire    [15:0]  Rx_pkt_length_rmon      ;
110
wire            Rx_apply_rmon           ;
111
wire    [2:0]   Rx_pkt_err_type_rmon    ;
112
wire    [2:0]   Rx_pkt_type_rmon        ;
113
wire    [2:0]   Tx_pkt_type_rmon        ;
114
wire    [15:0]  Tx_pkt_length_rmon      ;
115
wire            Tx_apply_rmon           ;
116
wire    [2:0]   Tx_pkt_err_type_rmon    ;
117
                //PHY interface
118
wire            MCrs_dv                 ;
119
wire    [7:0]   MRxD                    ;
120
wire            MRxErr                  ;
121
                //flow_control signals  
122
wire    [15:0]  pause_quanta            ;
123
wire            pause_quanta_val        ;
124
                //PHY interface
125
wire    [7:0]   MTxD                    ;
126
wire            MTxEn                   ;
127
wire            MCRS                    ;
128
                //interface clk signals
129
wire            MAC_tx_clk              ;
130
wire            MAC_rx_clk              ;
131
wire            MAC_tx_clk_div          ;
132
wire            MAC_rx_clk_div          ;
133
                //reg signals   
134
wire    [4:0]    Tx_Hwmark                               ;
135
wire    [4:0]    Tx_Lwmark                               ;
136
wire                    pause_frame_send_en             ;
137
wire    [15:0]   pause_quanta_set                ;
138
wire                    MAC_tx_add_en                   ;
139
wire                    FullDuplex                      ;
140
wire    [3:0]    MaxRetry                        ;
141
wire    [5:0]    IFGset                                  ;
142
wire    [7:0]    MAC_tx_add_prom_data    ;
143
wire    [2:0]    MAC_tx_add_prom_add             ;
144
wire                    MAC_tx_add_prom_wr              ;
145
wire                    tx_pause_en                             ;
146
wire                    xoff_cpu                        ;
147
wire                    xon_cpu                 ;
148 28 maverickis
                        //Rx host interface      
149 7 maverickis
wire                    MAC_rx_add_chk_en               ;
150
wire    [7:0]    MAC_rx_add_prom_data    ;
151
wire    [2:0]    MAC_rx_add_prom_add             ;
152
wire                    MAC_rx_add_prom_wr              ;
153
wire                    broadcast_filter_en         ;
154
wire    [15:0]   broadcast_MAX           ;
155
wire                    RX_APPEND_CRC                   ;
156
wire    [4:0]    Rx_Hwmark                           ;
157
wire    [4:0]    Rx_Lwmark                           ;
158
wire                    CRC_chk_en                              ;
159
wire    [5:0]    RX_IFG_SET                              ;
160
wire    [15:0]   RX_MAX_LENGTH                   ;
161
wire    [6:0]    RX_MIN_LENGTH                   ;
162
                                        //RMON host interface    
163
wire    [5:0]    CPU_rd_addr                             ;
164
wire                    CPU_rd_apply                    ;
165
wire                    CPU_rd_grant                    ;
166
wire    [31:0]   CPU_rd_dout                             ;
167
                                        //Phy int host interface 
168
wire                    Line_loop_en                    ;
169
                                        //MII to CPU             
170
wire    [7:0]    Divider                         ;
171
wire    [15:0]   CtrlData                        ;
172
wire    [4:0]    Rgad                            ;
173
wire    [4:0]    Fiad                            ;
174
wire            NoPre                           ;
175
wire            WCtrlData                       ;
176
wire            RStat                           ;
177
wire            ScanStat                        ;
178
wire            Busy                            ;
179
wire            LinkFail                        ;
180
wire            Nvalid                          ;
181
wire    [15:0]   Prsd                            ;
182
wire            WCtrlDataStart                  ;
183
wire            RStatStart                      ;
184
wire            UpdateMIIRX_DATAReg             ;
185
wire    [15:0]  broadcast_bucket_depth              ;
186
wire    [15:0]  broadcast_bucket_interval           ;
187 28 maverickis
wire            Pkg_lgth_fifo_empty;
188
 
189
reg             rx_pkg_lgth_fifo_wr_tmp;
190
reg             rx_pkg_lgth_fifo_wr_tmp_pl1;
191
reg             rx_pkg_lgth_fifo_wr;
192 7 maverickis
 
193 5 maverickis
//******************************************************************************
194
//internal signals                                                              
195
//******************************************************************************
196
MAC_rx U_MAC_rx(
197 7 maverickis
.Reset                      (Reset                      ),
198
.Clk_user                   (Clk_user                   ),
199
.Clk                        (MAC_rx_clk_div             ),
200
 //RMII interface           (//PHY interface            ),  
201
.MCrs_dv                    (MCrs_dv                    ),
202
.MRxD                       (MRxD                       ),
203
.MRxErr                     (MRxErr                     ),
204
 //flow_control signals     (//flow_control signals     ),  
205
.pause_quanta               (pause_quanta               ),
206
.pause_quanta_val           (pause_quanta_val           ),
207
 //user interface           (//user interface           ),  
208
.Rx_mac_ra                  (Rx_mac_ra                  ),
209
.Rx_mac_rd                  (Rx_mac_rd                  ),
210
.Rx_mac_data                (Rx_mac_data                ),
211
.Rx_mac_BE                  (Rx_mac_BE                  ),
212
.Rx_mac_pa                  (Rx_mac_pa                  ),
213
.Rx_mac_sop                 (Rx_mac_sop                 ),
214
.Rx_mac_eop                 (Rx_mac_eop                 ),
215
 //CPU                      (//CPU                      ),  
216
.MAC_rx_add_chk_en          (MAC_rx_add_chk_en          ),
217
.MAC_add_prom_data          (MAC_rx_add_prom_data       ),
218
.MAC_add_prom_add           (MAC_rx_add_prom_add        ),
219
.MAC_add_prom_wr            (MAC_rx_add_prom_wr         ),
220
.broadcast_filter_en        (broadcast_filter_en        ),
221
.broadcast_bucket_depth     (broadcast_bucket_depth     ),
222
.broadcast_bucket_interval  (broadcast_bucket_interval  ),
223
.RX_APPEND_CRC              (RX_APPEND_CRC              ),
224
.Rx_Hwmark                  (Rx_Hwmark                  ),
225
.Rx_Lwmark                  (Rx_Lwmark                  ),
226
.CRC_chk_en                 (CRC_chk_en                 ),
227
.RX_IFG_SET                 (RX_IFG_SET                 ),
228
.RX_MAX_LENGTH              (RX_MAX_LENGTH              ),
229
.RX_MIN_LENGTH              (RX_MIN_LENGTH              ),
230
 //RMON interface           (//RMON interface           ),  
231
.Rx_pkt_length_rmon         (Rx_pkt_length_rmon         ),
232
.Rx_apply_rmon              (Rx_apply_rmon              ),
233
.Rx_pkt_err_type_rmon       (Rx_pkt_err_type_rmon       ),
234
.Rx_pkt_type_rmon           (Rx_pkt_type_rmon           )
235 5 maverickis
);
236
 
237
MAC_tx U_MAC_tx(
238 7 maverickis
.Reset                      (Reset                      ),
239
.Clk                        (MAC_tx_clk_div             ),
240 5 maverickis
.Clk_user                   (Clk_user                   ),
241
 //PHY interface            (//PHY interface            ),
242 7 maverickis
.TxD                        (MTxD                       ),
243
.TxEn                       (MTxEn                      ),
244
.CRS                        (MCRS                       ),
245 5 maverickis
 //RMON                     (//RMON                     ),
246 7 maverickis
.Tx_pkt_type_rmon           (Tx_pkt_type_rmon           ),
247
.Tx_pkt_length_rmon         (Tx_pkt_length_rmon         ),
248
.Tx_apply_rmon              (Tx_apply_rmon              ),
249 5 maverickis
.Tx_pkt_err_type_rmon       (Tx_pkt_err_type_rmon       ),
250
 //user interface           (//user interface           ),
251 7 maverickis
.Tx_mac_wa                  (Tx_mac_wa                  ),
252
.Tx_mac_wr                  (Tx_mac_wr                  ),
253
.Tx_mac_data                (Tx_mac_data                ),
254
.Tx_mac_BE                  (Tx_mac_BE                  ),
255
.Tx_mac_sop                 (Tx_mac_sop                 ),
256
.Tx_mac_eop                 (Tx_mac_eop                 ),
257 5 maverickis
 //host interface           (//host interface           ),
258 7 maverickis
.Tx_Hwmark                  (Tx_Hwmark                  ),
259
.Tx_Lwmark                  (Tx_Lwmark                  ),
260
.pause_frame_send_en        (pause_frame_send_en        ),
261
.pause_quanta_set           (pause_quanta_set           ),
262
.MAC_tx_add_en              (MAC_tx_add_en              ),
263
.FullDuplex                 (FullDuplex                 ),
264
.MaxRetry                   (MaxRetry                   ),
265
.IFGset                     (IFGset                     ),
266
.MAC_add_prom_data          (MAC_tx_add_prom_data       ),
267
.MAC_add_prom_add           (MAC_tx_add_prom_add        ),
268
.MAC_add_prom_wr            (MAC_tx_add_prom_wr         ),
269
.tx_pause_en                (tx_pause_en                ),
270
.xoff_cpu                   (xoff_cpu                   ),
271
.xon_cpu                    (xon_cpu                    ),
272
 //MAC_rx_flow              (//MAC_rx_flow              ),
273
.pause_quanta               (pause_quanta               ),
274
.pause_quanta_val           (pause_quanta_val           )
275 5 maverickis
);
276
 
277 28 maverickis
 
278
assign Pkg_lgth_fifo_ra=!Pkg_lgth_fifo_empty;
279
always @ (posedge Reset or posedge MAC_rx_clk_div)
280
    if (Reset)
281
        rx_pkg_lgth_fifo_wr_tmp <=0;
282
    else if(Rx_apply_rmon&&Rx_pkt_err_type_rmon==3'b100)
283
        rx_pkg_lgth_fifo_wr_tmp <=1;
284
    else
285
        rx_pkg_lgth_fifo_wr_tmp <=0;
286
 
287
always @ (posedge Reset or posedge MAC_rx_clk_div)
288
    if (Reset)
289
        rx_pkg_lgth_fifo_wr_tmp_pl1 <=0;
290
    else
291
        rx_pkg_lgth_fifo_wr_tmp_pl1 <=rx_pkg_lgth_fifo_wr_tmp;
292
 
293
always @ (posedge Reset or posedge MAC_rx_clk_div)
294
    if (Reset)
295
        rx_pkg_lgth_fifo_wr <=0;
296
    else if(rx_pkg_lgth_fifo_wr_tmp&!rx_pkg_lgth_fifo_wr_tmp_pl1)
297
        rx_pkg_lgth_fifo_wr <=1;
298
    else
299
        rx_pkg_lgth_fifo_wr <=0;
300
 
301
afifo U_rx_pkg_lgth_fifo (
302
.din                        (RX_APPEND_CRC?Rx_pkt_length_rmon:Rx_pkt_length_rmon-4),
303
.wr_en                      (rx_pkg_lgth_fifo_wr        ),
304
.wr_clk                     (MAC_rx_clk_div             ),
305
.rd_en                      (Pkg_lgth_fifo_rd           ),
306
.rd_clk                     (Clk_user                   ),
307
.ainit                      (Reset                      ),
308
.dout                       (Pkg_lgth_fifo_data         ),
309
.full                       (                           ),
310
.almost_full                (                           ),
311
.empty                      (Pkg_lgth_fifo_empty        ),
312
.wr_count                   (                           ),
313
.rd_count                   (                           ),
314
.rd_ack                     (                           ),
315
.wr_ack                     (                           ));
316
 
317
 
318 5 maverickis
RMON U_RMON(
319 7 maverickis
.Clk                        (Clk_reg                    ),
320
.Reset                      (Reset                      ),
321 5 maverickis
 //Tx_RMON                  (//Tx_RMON                  ),
322 7 maverickis
.Tx_pkt_type_rmon           (Tx_pkt_type_rmon           ),
323
.Tx_pkt_length_rmon         (Tx_pkt_length_rmon         ),
324
.Tx_apply_rmon              (Tx_apply_rmon              ),
325 5 maverickis
.Tx_pkt_err_type_rmon       (Tx_pkt_err_type_rmon       ),
326
 //Tx_RMON                  (//Tx_RMON                  ),
327 7 maverickis
.Rx_pkt_type_rmon           (Rx_pkt_type_rmon           ),
328
.Rx_pkt_length_rmon         (Rx_pkt_length_rmon         ),
329
.Rx_apply_rmon              (Rx_apply_rmon              ),
330 5 maverickis
.Rx_pkt_err_type_rmon       (Rx_pkt_err_type_rmon       ),
331
 //CPU                      (//CPU                      ),
332 7 maverickis
.CPU_rd_addr                (CPU_rd_addr                ),
333
.CPU_rd_apply               (CPU_rd_apply               ),
334
.CPU_rd_grant               (CPU_rd_grant               ),
335
.CPU_rd_dout                (CPU_rd_dout                )
336 5 maverickis
);
337
 
338
Phy_int U_Phy_int(
339 7 maverickis
.Reset                      (Reset                      ),
340
.MAC_rx_clk                 (MAC_rx_clk                 ),
341
.MAC_tx_clk                 (MAC_tx_clk                 ),
342 5 maverickis
 //Rx interface             (//Rx interface             ),
343 7 maverickis
.MCrs_dv                    (MCrs_dv                    ),
344
.MRxD                       (MRxD                       ),
345
.MRxErr                     (MRxErr                     ),
346 5 maverickis
 //Tx interface             (//Tx interface             ),
347 7 maverickis
.MTxD                       (MTxD                       ),
348
.MTxEn                      (MTxEn                      ),
349
.MCRS                       (MCRS                       ),
350 5 maverickis
 //Phy interface            (//Phy interface            ),
351 7 maverickis
.Tx_er                      (Tx_er                      ),
352
.Tx_en                      (Tx_en                      ),
353
.Txd                        (Txd                        ),
354
.Rx_er                      (Rx_er                      ),
355
.Rx_dv                      (Rx_dv                      ),
356
.Rxd                        (Rxd                        ),
357
.Crs                        (Crs                        ),
358
.Col                        (Col                        ),
359 5 maverickis
 //host interface           (//host interface           ),
360 7 maverickis
.Line_loop_en               (Line_loop_en               ),
361
.Speed                      (Speed                      )
362 5 maverickis
);
363
 
364
Clk_ctrl U_Clk_ctrl(
365 7 maverickis
.Reset                      (Reset                      ),
366
.Clk_125M                   (Clk_125M                   ),
367 5 maverickis
 //host interface           (//host interface           ),
368 7 maverickis
.Speed                      (Speed                      ),
369
 //Phy interface            (//Phy interface            ),
370
.Gtx_clk                    (Gtx_clk                    ),
371
.Rx_clk                     (Rx_clk                     ),
372
.Tx_clk                     (Tx_clk                     ),
373 5 maverickis
 //interface clk            (//interface clk            ),
374 7 maverickis
.MAC_tx_clk                 (MAC_tx_clk                 ),
375
.MAC_rx_clk                 (MAC_rx_clk                 ),
376
.MAC_tx_clk_div             (MAC_tx_clk_div             ),
377
.MAC_rx_clk_div             (MAC_rx_clk_div             )
378 5 maverickis
);
379
 
380
eth_miim U_eth_miim(
381 7 maverickis
.Clk                        (Clk_reg                    ),
382 5 maverickis
.Reset                      (Reset                      ),
383
.Divider                    (Divider                    ),
384
.NoPre                      (NoPre                      ),
385
.CtrlData                   (CtrlData                   ),
386
.Rgad                       (Rgad                       ),
387
.Fiad                       (Fiad                       ),
388
.WCtrlData                  (WCtrlData                  ),
389
.RStat                      (RStat                      ),
390
.ScanStat                   (ScanStat                   ),
391 28 maverickis
.Mdo                        (Mdo                        ),
392
.MdoEn                      (MdoEn                      ),
393
.Mdi                        (Mdi                        ),
394 5 maverickis
.Mdc                        (Mdc                        ),
395
.Busy                       (Busy                       ),
396
.Prsd                       (Prsd                       ),
397
.LinkFail                   (LinkFail                   ),
398
.Nvalid                     (Nvalid                     ),
399
.WCtrlDataStart             (WCtrlDataStart             ),
400
.RStatStart                 (RStatStart                 ),
401 7 maverickis
.UpdateMIIRX_DATAReg        (UpdateMIIRX_DATAReg        ));
402 5 maverickis
 
403 7 maverickis
Reg_int U_Reg_int(
404
.Reset                          (Reset                          ),
405
.Clk_reg                        (Clk_reg                        ),
406
.CSB                        (CSB                        ),
407
.WRB                        (WRB                        ),
408
.CD_in                      (CD_in                      ),
409
.CD_out                     (CD_out                     ),
410
.CA                         (CA                         ),
411
 //Tx host interface        (//Tx host interface        ),
412
.Tx_Hwmark                                  (Tx_Hwmark                              ),
413
.Tx_Lwmark                                  (Tx_Lwmark                              ),
414
.pause_frame_send_en            (pause_frame_send_en            ),
415
.pause_quanta_set                   (pause_quanta_set               ),
416
.MAC_tx_add_en                      (MAC_tx_add_en                          ),
417
.FullDuplex                     (FullDuplex                     ),
418
.MaxRetry                           (MaxRetry                       ),
419
.IFGset                                     (IFGset                                         ),
420
.MAC_tx_add_prom_data       (MAC_tx_add_prom_data           ),
421
.MAC_tx_add_prom_add            (MAC_tx_add_prom_add            ),
422
.MAC_tx_add_prom_wr                 (MAC_tx_add_prom_wr             ),
423
.tx_pause_en                            (tx_pause_en                            ),
424
.xoff_cpu                           (xoff_cpu                       ),
425
.xon_cpu                        (xon_cpu                        ),
426
 //Rx host interface        (//Rx host interface            ),
427
.MAC_rx_add_chk_en                  (MAC_rx_add_chk_en              ),
428
.MAC_rx_add_prom_data       (MAC_rx_add_prom_data           ),
429
.MAC_rx_add_prom_add            (MAC_rx_add_prom_add            ),
430
.MAC_rx_add_prom_wr                 (MAC_rx_add_prom_wr             ),
431
.broadcast_filter_en        (broadcast_filter_en            ),
432
.broadcast_bucket_depth     (broadcast_bucket_depth     ),
433
.broadcast_bucket_interval  (broadcast_bucket_interval  ),
434
.RX_APPEND_CRC                      (RX_APPEND_CRC                          ),
435
.Rx_Hwmark                              (Rx_Hwmark                                      ),
436
.Rx_Lwmark                  (Rx_Lwmark                  ),
437
.CRC_chk_en                                 (CRC_chk_en                             ),
438
.RX_IFG_SET                                 (RX_IFG_SET                             ),
439
.RX_MAX_LENGTH                      (RX_MAX_LENGTH                          ),
440
.RX_MIN_LENGTH                      (RX_MIN_LENGTH                          ),
441
 //RMON host interface      (//RMON host interface      ),
442
.CPU_rd_addr                            (CPU_rd_addr                            ),
443
.CPU_rd_apply                       (CPU_rd_apply                           ),
444
.CPU_rd_grant                       (CPU_rd_grant                           ),
445
.CPU_rd_dout                            (CPU_rd_dout                            ),
446
 //Phy int host interface   (//Phy int host interface   ),
447
.Line_loop_en                       (Line_loop_en                           ),
448
.Speed                                      (Speed                                          ),
449
 //MII to CPU               (//MII to CPU               ),
450
.Divider                        (Divider                        ),
451
.CtrlData                       (CtrlData                       ),
452
.Rgad                           (Rgad                           ),
453
.Fiad                           (Fiad                           ),
454
.NoPre                          (NoPre                          ),
455
.WCtrlData                      (WCtrlData                      ),
456
.RStat                          (RStat                          ),
457
.ScanStat                       (ScanStat                       ),
458
.Busy                           (Busy                           ),
459
.LinkFail                       (LinkFail                       ),
460
.Nvalid                         (Nvalid                         ),
461
.Prsd                           (Prsd                           ),
462
.WCtrlDataStart                 (WCtrlDataStart                 ),
463
.RStatStart                     (RStatStart                     ),
464
.UpdateMIIRX_DATAReg            (UpdateMIIRX_DATAReg            )
465
);
466
 
467 5 maverickis
endmodule
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