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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_top.v] - Blame information for rev 6

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_top.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
// no message
// 
 
module MAC_top(
                                //system signals
input                   Reset                                   ,
input                   Clk_125M                                ,
input                   Clk_user                                ,
input                   Clk_reg                                 ,
                                //user interface 
output                  Rx_mac_ra                               ,
input                   Rx_mac_rd                               ,
output  [31:0]   Rx_mac_data                             ,
output  [1:0]    Rx_mac_BE                               ,
output                  Rx_mac_pa                               ,
output                  Rx_mac_sop                              ,
output                  Rx_mac_eop                              ,
                                //user interface 
output                  Tx_mac_wa                       ,
input                   Tx_mac_wr                       ,
input   [31:0]   Tx_mac_data                     ,
input   [1:0]    Tx_mac_BE                               ,//big endian
input                   Tx_mac_sop                      ,
input                   Tx_mac_eop                              ,
                                //Phy interface          
                                //Phy interface                 
output                  Gtx_clk                                 ,//used only in GMII mode
input                   Rx_clk                                  ,
input                   Tx_clk                                  ,//used only in MII mode
output                  Tx_er                                   ,
output                  Tx_en                                   ,
output  [7:0]    Txd                                             ,
input                   Rx_er                                   ,
input                   Rx_dv                                   ,
input   [7:0]    Rxd                                             ,
input                   Crs                                             ,
input                   Col                                             ,
                                //Tx host interface 
input   [4:0]    Tx_Hwmark                               ,
input   [4:0]    Tx_Lwmark                               ,
input                   pause_frame_send_en             ,
input   [15:0]   pause_quanta_set                ,
input                   MAC_tx_add_en                   ,
input                   FullDuplex                      ,
input   [3:0]    MaxRetry                        ,
input   [5:0]    IFGset                                  ,
input   [7:0]    MAC_tx_add_prom_data    ,
input   [2:0]    MAC_tx_add_prom_add             ,
input                   MAC_tx_add_prom_wr              ,
input                   tx_pause_en                             ,
input                   xoff_cpu                        ,
input                   xon_cpu                 ,
                                //Rx host interface     
input                   MAC_rx_add_chk_en               ,
input   [7:0]    MAC_rx_add_prom_data    ,
input   [2:0]    MAC_rx_add_prom_add             ,
input                   MAC_rx_add_prom_wr              ,
input                   broadcast_filter_en         ,
input   [15:0]   broadcast_MAX           ,
input                   RX_APPEND_CRC                   ,
input                   CRC_chk_en                              ,
input   [5:0]    RX_IFG_SET                              ,
input   [15:0]   RX_MAX_LENGTH                   ,//     1518
input   [6:0]    RX_MIN_LENGTH                   ,//     64
                                //RMON host interface
input   [5:0]    CPU_rd_addr                             ,
input                   CPU_rd_apply                    ,
output                  CPU_rd_grant                    ,
output  [31:0]   CPU_rd_dout                             ,
                                //Phy int host interface     
input                   Line_loop_en                    ,
input   [2:0]    Speed                                   ,
                                //MII to CPU 
input   [7:0]    Divider                         ,// Divider for the host clock
input  [15:0]    CtrlData                        ,// Control Data (to be written to the PHY reg.)
input   [4:0]    Rgad                            ,// Register Address (within the PHY)
input   [4:0]    Fiad                            ,// PHY Address
input           NoPre                           ,// No Preamble (no 32-bit preamble)
input           WCtrlData                       ,// Write Control Data operation
input           RStat                           ,// Read Status operation
input           ScanStat                        ,// Scan Status operation
output          Busy                            ,// Busy Signal
output          LinkFail                        ,// Link Integrity Signal
output          Nvalid                          ,// Invalid Status (qualifier for the valid scan result)
output [15:0]    Prsd                            ,// Read Status Data (data read from the PHY)
output          WCtrlDataStart                  ,// This signals resets the WCTRLDATA bit in the MIIM Command register
output          RStatStart                      ,// This signal resets the RSTAT BIT in the MIIM Command register
output          UpdateMIIRX_DATAReg             ,// Updates MII RX_DATA register with read data
                                //MII interface signals
inout           Mdio                    ,// MII Management Data In
output          Mdc                             ,// MII Management Data Clock           
 
);
//******************************************************************************
//internal signals                                                              
//******************************************************************************
                                //RMON interface
wire    [15:0]   Rx_pkt_length_rmon              ;
wire                    Rx_apply_rmon           ;
wire    [2:0]    Rx_pkt_err_type_rmon    ;
wire    [2:0]    Rx_pkt_type_rmon                ;
wire    [2:0]    Tx_pkt_type_rmon                ;
wire    [15:0]   Tx_pkt_length_rmon              ;
wire                    Tx_apply_rmon           ;
wire    [2:0]    Tx_pkt_err_type_rmon    ;
                                //PHY interface
wire                    MCrs_dv                                 ;
wire    [7:0]    MRxD                                    ;
wire                    MRxErr                                  ;
                                //flow_control signals  
wire    [15:0]   pause_quanta                    ;
wire                    pause_quanta_val                ;
                                //PHY interface
wire    [7:0]    MTxD                            ;
wire                    MTxEn                   ;
wire                    MCRS                                    ;
                                //interface clk signals
wire                    MAC_tx_clk                              ;
wire                    MAC_rx_clk                              ;
wire                    MAC_tx_clk_div                  ;
wire                    MAC_rx_clk_div                  ;
//******************************************************************************
//internal signals                                                              
//******************************************************************************
MAC_rx U_MAC_rx(
.Reset                          (Reset                          ),
.Clk_user                   (Clk_user                   ),
.Clk                        (MAC_rx_clk_div             ),
 //RMII interface           (//PHY interface            ),  
.MCrs_dv                                (MCrs_dv                                ),
.MRxD                               (MRxD                                       ),
.MRxErr                             (MRxErr                                     ),
 //flow_control signals     (//flow_control signals     ),  
.pause_quanta                   (pause_quanta                   ),
.pause_quanta_val               (pause_quanta_val               ),
 //user interface           (//user interface           ),  
.Rx_mac_ra                      (Rx_mac_ra                      ),
.Rx_mac_rd                      (Rx_mac_rd                      ),
.Rx_mac_data                (Rx_mac_data                        ),
.Rx_mac_BE                      (Rx_mac_BE                      ),
.Rx_mac_pa                      (Rx_mac_pa                      ),
.Rx_mac_sop                     (Rx_mac_sop                     ),
.Rx_mac_eop                     (Rx_mac_eop                     ),
 //CPU                      (//CPU                      ),  
.MAC_rx_add_chk_en                  (MAC_rx_add_chk_en                  ),
.MAC_add_prom_data                  (MAC_rx_add_prom_data               ),
.MAC_add_prom_add               (MAC_rx_add_prom_add        ),
.MAC_add_prom_wr                    (MAC_rx_add_prom_wr                 ),
.broadcast_filter_en        (broadcast_filter_en                ),
.broadcast_MAX                  (broadcast_MAX                  ),
.RX_APPEND_CRC              (RX_APPEND_CRC              ),
.CRC_chk_en                                     (CRC_chk_en                                     ),
.RX_IFG_SET                     (RX_IFG_SET                     ),
.RX_MAX_LENGTH              (RX_MAX_LENGTH                      ),
.RX_MIN_LENGTH              (RX_MIN_LENGTH                      ),
 //RMON interface           (//RMON interface           ),  
.Rx_pkt_length_rmon                 (Rx_pkt_length_rmon                 ),
.Rx_apply_rmon              (Rx_apply_rmon                      ),
.Rx_pkt_err_type_rmon       (Rx_pkt_err_type_rmon               ),
.Rx_pkt_type_rmon                   (Rx_pkt_type_rmon           )
);
 
MAC_tx U_MAC_tx(
.Reset                                  (Reset                                  ),
.Clk                        (MAC_tx_clk_div                 ),
.Clk_user                   (Clk_user                   ),
 //PHY interface            (//PHY interface            ),
.TxD                                (MTxD                                   ),
.TxEn                       (MTxEn                          ),
.CRS                                        (MCRS                                           ),
 //RMON                     (//RMON                     ),
.Tx_pkt_type_rmon               (Tx_pkt_type_rmon               ),
.Tx_pkt_length_rmon             (Tx_pkt_length_rmon             ),
.Tx_apply_rmon              (Tx_apply_rmon                  ),
.Tx_pkt_err_type_rmon       (Tx_pkt_err_type_rmon       ),
 //user interface           (//user interface           ),
.Tx_mac_wa                      (Tx_mac_wa                      ),
.Tx_mac_wr                      (Tx_mac_wr                      ),
.Tx_mac_data                (Tx_mac_data                    ),
.Tx_mac_BE                              (Tx_mac_BE                              ),
.Tx_mac_sop                     (Tx_mac_sop                     ),
.Tx_mac_eop                             (Tx_mac_eop                             ),
 //host interface           (//host interface           ),
.Tx_Hwmark                              (Tx_Hwmark                              ),
.Tx_Lwmark                              (Tx_Lwmark                              ),
.pause_frame_send_en        (pause_frame_send_en            ),
.pause_quanta_set               (pause_quanta_set               ),
.MAC_tx_add_en                  (MAC_tx_add_en                  ),
.FullDuplex                 (FullDuplex                     ),
.MaxRetry                       (MaxRetry                       ),
.IFGset                                 (IFGset                                 ),
.MAC_add_prom_data              (MAC_tx_add_prom_data       ),
.MAC_add_prom_add               (MAC_tx_add_prom_add        ),
.MAC_add_prom_wr                    (MAC_tx_add_prom_wr             ),
.tx_pause_en                        (tx_pause_en                            ),
.xoff_cpu                       (xoff_cpu                       ),
.xon_cpu                        (xon_cpu                        ),
 //MAC_rx_flow              (//MAC_rx_flow                  ),
.pause_quanta               (pause_quanta                   ),
.pause_quanta_val               (pause_quanta_val               )
);
 
RMON U_RMON(
.Clk                                            (Clk_reg                                        ),
.Reset                                  (Reset                                  ),
 //Tx_RMON                  (//Tx_RMON                  ),
.Tx_pkt_type_rmon               (Tx_pkt_type_rmon               ),
.Tx_pkt_length_rmon             (Tx_pkt_length_rmon             ),
.Tx_apply_rmon              (Tx_apply_rmon                  ),
.Tx_pkt_err_type_rmon       (Tx_pkt_err_type_rmon       ),
 //Tx_RMON                  (//Tx_RMON                  ),
.Rx_pkt_type_rmon               (Rx_pkt_type_rmon               ),
.Rx_pkt_length_rmon             (Rx_pkt_length_rmon             ),
.Rx_apply_rmon              (Rx_apply_rmon                  ),
.Rx_pkt_err_type_rmon       (Rx_pkt_err_type_rmon       ),
 //CPU                      (//CPU                      ),
.CPU_rd_addr                        (CPU_rd_addr                            ),
.CPU_rd_apply                   (CPU_rd_apply                   ),
.CPU_rd_grant                   (CPU_rd_grant                   ),
.CPU_rd_dout                        (CPU_rd_dout                            )
);
 
Phy_int U_Phy_int(
.Reset                                          (Reset                                          ),
.MAC_rx_clk                             (MAC_rx_clk                             ),
.MAC_tx_clk                             (MAC_tx_clk                             ),
 //Rx interface             (//Rx interface             ),
.MCrs_dv                                    (MCrs_dv                                ),
.MRxD                                   (MRxD                                   ),
.MRxErr                                 (MRxErr                                 ),
 //Tx interface             (//Tx interface             ),
.MTxD                           (MTxD                           ),
.MTxEn                      (MTxEn                          ),
.MCRS                                   (MCRS                                   ),
 //Phy interface            (//Phy interface            ),
.Tx_er                                  (Tx_er                                  ),
.Tx_en                                  (Tx_en                                  ),
.Txd                                        (Txd                                            ),
.Rx_er                                  (Rx_er                                  ),
.Rx_dv                                  (Rx_dv                                  ),
.Rxd                                        (Rxd                                            ),
.Crs                                        (Crs                                            ),
.Col                                        (Col                                            ),
 //host interface           (//host interface           ),
.Line_loop_en                   (Line_loop_en                   ),
.Speed                                  (Speed                      )
);
 
Clk_ctrl U_Clk_ctrl(
.Reset                                          (Reset                                          ),
.Clk_125M                           (Clk_125M                       ),
 //host interface           (//host interface           ),
.Speed                              (Speed                                  ),
 //Phy interface                (//Phy interface                ),
.Gtx_clk                                (Gtx_clk                                ),
.Rx_clk                             (Rx_clk                                 ),
.Tx_clk                             (Tx_clk                                 ),
 //interface clk            (//interface clk            ),
.MAC_tx_clk                         (MAC_tx_clk                     ),
.MAC_rx_clk                         (MAC_rx_clk                     ),
.MAC_tx_clk_div             (MAC_tx_clk_div                 ),
.MAC_rx_clk_div             (MAC_rx_clk_div                 )
);
 
eth_miim U_eth_miim(
.Clk                                            (Clk_reg                    ),
.Reset                      (Reset                      ),
.Divider                    (Divider                    ),
.NoPre                      (NoPre                      ),
.CtrlData                   (CtrlData                   ),
.Rgad                       (Rgad                       ),
.Fiad                       (Fiad                       ),
.WCtrlData                  (WCtrlData                  ),
.RStat                      (RStat                      ),
.ScanStat                   (ScanStat                   ),
.Mdio                       (Mdio                       ),
.Mdc                        (Mdc                        ),
.Busy                       (Busy                       ),
.Prsd                       (Prsd                       ),
.LinkFail                   (LinkFail                   ),
.Nvalid                     (Nvalid                     ),
.WCtrlDataStart             (WCtrlDataStart             ),
.RStatStart                 (RStatStart                 ),
.UpdateMIIRX_DATAReg            (UpdateMIIRX_DATAReg            ));
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_top.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_top.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41	6	maverickis	`// $Log: not supported by cvs2svn $`
42			`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`
43			`// no message`
44			`//`
45	5	maverickis
46			`module MAC_top(`
47			`//system signals`
48			`input Reset ,`
49			`input Clk_125M ,`
50			`input Clk_user ,`
51			`input Clk_reg ,`
52			`//user interface`
53			`output Rx_mac_ra ,`
54			`input Rx_mac_rd ,`
55			`output [31:0] Rx_mac_data ,`
56			`output [1:0] Rx_mac_BE ,`
57			`output Rx_mac_pa ,`
58			`output Rx_mac_sop ,`
59			`output Rx_mac_eop ,`
60			`//user interface`
61			`output Tx_mac_wa ,`
62			`input Tx_mac_wr ,`
63			`input [31:0] Tx_mac_data ,`
64			`input [1:0] Tx_mac_BE ,//big endian`
65			`input Tx_mac_sop ,`
66			`input Tx_mac_eop ,`
67			`//Phy interface`
68			`//Phy interface`
69			`output Gtx_clk ,//used only in GMII mode`
70			`input Rx_clk ,`
71			`input Tx_clk ,//used only in MII mode`
72			`output Tx_er ,`
73			`output Tx_en ,`
74			`output [7:0] Txd ,`
75			`input Rx_er ,`
76			`input Rx_dv ,`
77			`input [7:0] Rxd ,`
78			`input Crs ,`
79			`input Col ,`
80			`//Tx host interface`
81			`input [4:0] Tx_Hwmark ,`
82			`input [4:0] Tx_Lwmark ,`
83			`input pause_frame_send_en ,`
84			`input [15:0] pause_quanta_set ,`
85			`input MAC_tx_add_en ,`
86			`input FullDuplex ,`
87			`input [3:0] MaxRetry ,`
88			`input [5:0] IFGset ,`
89			`input [7:0] MAC_tx_add_prom_data ,`
90			`input [2:0] MAC_tx_add_prom_add ,`
91			`input MAC_tx_add_prom_wr ,`
92			`input tx_pause_en ,`
93			`input xoff_cpu ,`
94			`input xon_cpu ,`
95			`//Rx host interface`
96			`input MAC_rx_add_chk_en ,`
97			`input [7:0] MAC_rx_add_prom_data ,`
98			`input [2:0] MAC_rx_add_prom_add ,`
99			`input MAC_rx_add_prom_wr ,`
100			`input broadcast_filter_en ,`
101			`input [15:0] broadcast_MAX ,`
102			`input RX_APPEND_CRC ,`
103			`input CRC_chk_en ,`
104			`input [5:0] RX_IFG_SET ,`
105			`input [15:0] RX_MAX_LENGTH ,// 1518`
106			`input [6:0] RX_MIN_LENGTH ,// 64`
107			`//RMON host interface`
108			`input [5:0] CPU_rd_addr ,`
109			`input CPU_rd_apply ,`
110			`output CPU_rd_grant ,`
111			`output [31:0] CPU_rd_dout ,`
112			`//Phy int host interface`
113			`input Line_loop_en ,`
114			`input [2:0] Speed ,`
115			`//MII to CPU`
116			`input [7:0] Divider ,// Divider for the host clock`
117			`input [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)`
118			`input [4:0] Rgad ,// Register Address (within the PHY)`
119			`input [4:0] Fiad ,// PHY Address`
120			`input NoPre ,// No Preamble (no 32-bit preamble)`
121			`input WCtrlData ,// Write Control Data operation`
122			`input RStat ,// Read Status operation`
123			`input ScanStat ,// Scan Status operation`
124			`output Busy ,// Busy Signal`
125			`output LinkFail ,// Link Integrity Signal`
126			`output Nvalid ,// Invalid Status (qualifier for the valid scan result)`
127			`output [15:0] Prsd ,// Read Status Data (data read from the PHY)`
128			`output WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register`
129			`output RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register`
130			`output UpdateMIIRX_DATAReg ,// Updates MII RX_DATA register with read data`
131			`//MII interface signals`
132			`inout Mdio ,// MII Management Data In`
133			`output Mdc ,// MII Management Data Clock`
134
135			`);`
136			`//******************************************************************************`
137			`//internal signals`
138			`//******************************************************************************`
139			`//RMON interface`
140			`wire [15:0] Rx_pkt_length_rmon ;`
141			`wire Rx_apply_rmon ;`
142			`wire [2:0] Rx_pkt_err_type_rmon ;`
143			`wire [2:0] Rx_pkt_type_rmon ;`
144			`wire [2:0] Tx_pkt_type_rmon ;`
145			`wire [15:0] Tx_pkt_length_rmon ;`
146			`wire Tx_apply_rmon ;`
147			`wire [2:0] Tx_pkt_err_type_rmon ;`
148			`//PHY interface`
149			`wire MCrs_dv ;`
150			`wire [7:0] MRxD ;`
151			`wire MRxErr ;`
152			`//flow_control signals`
153			`wire [15:0] pause_quanta ;`
154			`wire pause_quanta_val ;`
155			`//PHY interface`
156			`wire [7:0] MTxD ;`
157			`wire MTxEn ;`
158			`wire MCRS ;`
159			`//interface clk signals`
160			`wire MAC_tx_clk ;`
161			`wire MAC_rx_clk ;`
162			`wire MAC_tx_clk_div ;`
163			`wire MAC_rx_clk_div ;`
164			`//******************************************************************************`
165			`//internal signals`
166			`//******************************************************************************`
167			`MAC_rx U_MAC_rx(`
168			`.Reset (Reset ),`
169			`.Clk_user (Clk_user ),`
170			`.Clk (MAC_rx_clk_div ),`
171			`//RMII interface (//PHY interface ),`
172			`.MCrs_dv (MCrs_dv ),`
173			`.MRxD (MRxD ),`
174			`.MRxErr (MRxErr ),`
175			`//flow_control signals (//flow_control signals ),`
176			`.pause_quanta (pause_quanta ),`
177			`.pause_quanta_val (pause_quanta_val ),`
178			`//user interface (//user interface ),`
179			`.Rx_mac_ra (Rx_mac_ra ),`
180			`.Rx_mac_rd (Rx_mac_rd ),`
181			`.Rx_mac_data (Rx_mac_data ),`
182			`.Rx_mac_BE (Rx_mac_BE ),`
183			`.Rx_mac_pa (Rx_mac_pa ),`
184			`.Rx_mac_sop (Rx_mac_sop ),`
185			`.Rx_mac_eop (Rx_mac_eop ),`
186			`//CPU (//CPU ),`
187			`.MAC_rx_add_chk_en (MAC_rx_add_chk_en ),`
188			`.MAC_add_prom_data (MAC_rx_add_prom_data ),`
189			`.MAC_add_prom_add (MAC_rx_add_prom_add ),`
190			`.MAC_add_prom_wr (MAC_rx_add_prom_wr ),`
191			`.broadcast_filter_en (broadcast_filter_en ),`
192			`.broadcast_MAX (broadcast_MAX ),`
193			`.RX_APPEND_CRC (RX_APPEND_CRC ),`
194			`.CRC_chk_en (CRC_chk_en ),`
195			`.RX_IFG_SET (RX_IFG_SET ),`
196			`.RX_MAX_LENGTH (RX_MAX_LENGTH ),`
197			`.RX_MIN_LENGTH (RX_MIN_LENGTH ),`
198			`//RMON interface (//RMON interface ),`
199			`.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),`
200			`.Rx_apply_rmon (Rx_apply_rmon ),`
201			`.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),`
202			`.Rx_pkt_type_rmon (Rx_pkt_type_rmon )`
203			`);`
204
205			`MAC_tx U_MAC_tx(`
206			`.Reset (Reset ),`
207			`.Clk (MAC_tx_clk_div ),`
208			`.Clk_user (Clk_user ),`
209			`//PHY interface (//PHY interface ),`
210			`.TxD (MTxD ),`
211			`.TxEn (MTxEn ),`
212			`.CRS (MCRS ),`
213			`//RMON (//RMON ),`
214			`.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),`
215			`.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),`
216			`.Tx_apply_rmon (Tx_apply_rmon ),`
217			`.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),`
218			`//user interface (//user interface ),`
219			`.Tx_mac_wa (Tx_mac_wa ),`
220			`.Tx_mac_wr (Tx_mac_wr ),`
221			`.Tx_mac_data (Tx_mac_data ),`
222			`.Tx_mac_BE (Tx_mac_BE ),`
223			`.Tx_mac_sop (Tx_mac_sop ),`
224			`.Tx_mac_eop (Tx_mac_eop ),`
225			`//host interface (//host interface ),`
226			`.Tx_Hwmark (Tx_Hwmark ),`
227			`.Tx_Lwmark (Tx_Lwmark ),`
228			`.pause_frame_send_en (pause_frame_send_en ),`
229			`.pause_quanta_set (pause_quanta_set ),`
230			`.MAC_tx_add_en (MAC_tx_add_en ),`
231			`.FullDuplex (FullDuplex ),`
232			`.MaxRetry (MaxRetry ),`
233			`.IFGset (IFGset ),`
234			`.MAC_add_prom_data (MAC_tx_add_prom_data ),`
235			`.MAC_add_prom_add (MAC_tx_add_prom_add ),`
236			`.MAC_add_prom_wr (MAC_tx_add_prom_wr ),`
237			`.tx_pause_en (tx_pause_en ),`
238			`.xoff_cpu (xoff_cpu ),`
239			`.xon_cpu (xon_cpu ),`
240			`//MAC_rx_flow (//MAC_rx_flow ),`
241			`.pause_quanta (pause_quanta ),`
242			`.pause_quanta_val (pause_quanta_val )`
243			`);`
244
245			`RMON U_RMON(`
246			`.Clk (Clk_reg ),`
247			`.Reset (Reset ),`
248			`//Tx_RMON (//Tx_RMON ),`
249			`.Tx_pkt_type_rmon (Tx_pkt_type_rmon ),`
250			`.Tx_pkt_length_rmon (Tx_pkt_length_rmon ),`
251			`.Tx_apply_rmon (Tx_apply_rmon ),`
252			`.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),`
253			`//Tx_RMON (//Tx_RMON ),`
254			`.Rx_pkt_type_rmon (Rx_pkt_type_rmon ),`
255			`.Rx_pkt_length_rmon (Rx_pkt_length_rmon ),`
256			`.Rx_apply_rmon (Rx_apply_rmon ),`
257			`.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ),`
258			`//CPU (//CPU ),`
259			`.CPU_rd_addr (CPU_rd_addr ),`
260			`.CPU_rd_apply (CPU_rd_apply ),`
261			`.CPU_rd_grant (CPU_rd_grant ),`
262			`.CPU_rd_dout (CPU_rd_dout )`
263			`);`
264
265			`Phy_int U_Phy_int(`
266			`.Reset (Reset ),`
267			`.MAC_rx_clk (MAC_rx_clk ),`
268			`.MAC_tx_clk (MAC_tx_clk ),`
269			`//Rx interface (//Rx interface ),`
270			`.MCrs_dv (MCrs_dv ),`
271			`.MRxD (MRxD ),`
272			`.MRxErr (MRxErr ),`
273			`//Tx interface (//Tx interface ),`
274			`.MTxD (MTxD ),`
275			`.MTxEn (MTxEn ),`
276			`.MCRS (MCRS ),`
277			`//Phy interface (//Phy interface ),`
278			`.Tx_er (Tx_er ),`
279			`.Tx_en (Tx_en ),`
280			`.Txd (Txd ),`
281			`.Rx_er (Rx_er ),`
282			`.Rx_dv (Rx_dv ),`
283			`.Rxd (Rxd ),`
284			`.Crs (Crs ),`
285			`.Col (Col ),`
286			`//host interface (//host interface ),`
287			`.Line_loop_en (Line_loop_en ),`
288			`.Speed (Speed )`
289			`);`
290
291			`Clk_ctrl U_Clk_ctrl(`
292			`.Reset (Reset ),`
293			`.Clk_125M (Clk_125M ),`
294			`//host interface (//host interface ),`
295			`.Speed (Speed ),`
296			`//Phy interface (//Phy interface ),`
297			`.Gtx_clk (Gtx_clk ),`
298			`.Rx_clk (Rx_clk ),`
299			`.Tx_clk (Tx_clk ),`
300			`//interface clk (//interface clk ),`
301			`.MAC_tx_clk (MAC_tx_clk ),`
302			`.MAC_rx_clk (MAC_rx_clk ),`
303			`.MAC_tx_clk_div (MAC_tx_clk_div ),`
304			`.MAC_rx_clk_div (MAC_rx_clk_div )`
305			`);`
306
307			`eth_miim U_eth_miim(`
308			`.Clk (Clk_reg ),`
309			`.Reset (Reset ),`
310			`.Divider (Divider ),`
311			`.NoPre (NoPre ),`
312			`.CtrlData (CtrlData ),`
313			`.Rgad (Rgad ),`
314			`.Fiad (Fiad ),`
315			`.WCtrlData (WCtrlData ),`
316			`.RStat (RStat ),`
317			`.ScanStat (ScanStat ),`
318			`.Mdio (Mdio ),`
319			`.Mdc (Mdc ),`
320			`.Busy (Busy ),`
321			`.Prsd (Prsd ),`
322			`.LinkFail (LinkFail ),`
323			`.Nvalid (Nvalid ),`
324			`.WCtrlDataStart (WCtrlDataStart ),`
325			`.RStatStart (RStatStart ),`
326			`.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ));`
327
328			`endmodule`
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