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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_tx/] [CRC_gen.v] - Blame information for rev 6

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1 5 maverickis 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  CRC_gen.v                                                   ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Jon Gao (gaojon@yahoo.com)                            ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
41 6 maverickis 
// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
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// no message
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//
45 5 maverickis 
 
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module CRC_gen (
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Reset           ,
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Clk             ,
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Init        ,
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Frame_data      ,
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Data_en     ,
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CRC_rd          ,
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CRC_end         ,
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CRC_out
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);
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input                   Reset           ;
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input                   Clk             ;
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input                   Init        ;
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input[7:0]               Frame_data      ;
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input                   Data_en     ;
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input                   CRC_rd          ;
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output[7:0]              CRC_out     ;
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output                  CRC_end         ;
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//******************************************************************************
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//internal signals
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//******************************************************************************
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reg[7:0]         CRC_out     ;
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reg[31:0]                CRC_reg;
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reg                             CRC_end;
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reg[3:0]         Counter;
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//******************************************************************************
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//******************************************************************************
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//input data width is 8bit, and the first bit is bit[0]
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function[31:0]   NextCRC;
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        input[7:0]               D;
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        input[31:0]              C;
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        reg[31:0]                NewCRC;
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        begin
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        NewCRC[0]=C[24]^C[30]^D[1]^D[7];
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        NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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        NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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        NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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        NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
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        NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
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        NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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        NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
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        NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
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        NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
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        NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
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        NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
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        NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
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        NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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        NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
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        NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
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        NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
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        NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
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        NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
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        NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
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        NewCRC[20]=C[12]^C[28]^D[3];
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        NewCRC[21]=C[13]^C[29]^D[2];
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        NewCRC[22]=C[14]^C[24]^D[7];
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        NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
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        NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
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        NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
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        NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
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        NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
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        NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
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        NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
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        NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
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        NewCRC[31]=C[23]^C[29]^D[2];
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        NextCRC=NewCRC;
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        end
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                endfunction
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//******************************************************************************
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always @ (posedge Clk or posedge Reset)
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        if (Reset)
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                CRC_reg         <=32'hffffffff;
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        else if (Init)
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                CRC_reg         <=32'hffffffff;
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        else if (Data_en)
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                CRC_reg         <=NextCRC(Frame_data,CRC_reg);
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        else if (CRC_rd)
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                CRC_reg         <={CRC_reg[23:0],8'hff};
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always @ (CRC_rd or CRC_reg)
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        if (CRC_rd)
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                CRC_out         <=~{
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                                                CRC_reg[24],
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                                                CRC_reg[25],
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                                                CRC_reg[26],
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                                                CRC_reg[27],
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                                                CRC_reg[28],
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                                                CRC_reg[29],
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                                                CRC_reg[30],
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                                                CRC_reg[31]
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                                                };
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        else
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                CRC_out         <=0;
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//caculate CRC out length ,4 cycles
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//CRC_end aligned to last CRC checksum data
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always @(posedge Clk or posedge Reset)
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        if (Reset)
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                Counter         <=0;
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        else if (!CRC_rd)
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                Counter         <=0;
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        else
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                Counter         <=Counter + 1;
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always @ (Counter)
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        if (Counter==3)
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                CRC_end=1;
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        else
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                CRC_end=0;
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endmodule
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