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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_tx/] [MAC_tx_addr_add.v] - Blame information for rev 33

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MAC_tx_addr_add.v                                           ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Jon Gao (gaojon@yahoo.com)                            ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//                                                                    
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// CVS Revision History                                               
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//                                                                    
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// $Log: not supported by cvs2svn $
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// Revision 1.2  2005/12/16 06:44:18  Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
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// no message
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//                                           
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module MAC_tx_addr_add (
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Reset               ,
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Clk                 ,
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MAC_tx_addr_init    ,
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MAC_tx_addr_rd      ,
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MAC_tx_addr_data    ,
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//CPU               ,
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MAC_add_prom_data   ,
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MAC_add_prom_add    ,
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MAC_add_prom_wr
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);
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input           Reset               ;
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input           Clk                 ;
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input           MAC_tx_addr_rd      ;
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input           MAC_tx_addr_init    ;
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output  [7:0]   MAC_tx_addr_data    ;
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                //CPU               ;
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input   [7:0]   MAC_add_prom_data   ;
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input   [2:0]   MAC_add_prom_add    ;
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input           MAC_add_prom_wr     ;
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//******************************************************************************   
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//internal signals                                                              
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//******************************************************************************
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reg [2:0]       add_rd;
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wire[2:0]       add_wr;
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wire[7:0]       din;
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wire[7:0]       dout;
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wire            wr_en;
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reg             MAC_add_prom_wr_dl1;
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reg             MAC_add_prom_wr_dl2;
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//******************************************************************************   
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//write data from cpu to prom                                                              
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//******************************************************************************
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always @ (posedge Clk or posedge Reset)
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    if (Reset)
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        begin
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        MAC_add_prom_wr_dl1     <=0;
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        MAC_add_prom_wr_dl2     <=0;
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        end
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    else
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        begin
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        MAC_add_prom_wr_dl1     <=MAC_add_prom_wr;
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        MAC_add_prom_wr_dl2     <=MAC_add_prom_wr_dl1;
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        end
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assign # 2 wr_en   =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
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assign # 2 add_wr  =MAC_add_prom_add;
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assign # 2 din     =MAC_add_prom_data;
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//******************************************************************************   
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//read data from cpu to prom                                                              
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//******************************************************************************
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always @ (posedge Clk or posedge Reset)
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    if (Reset)
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        add_rd       <=0;
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    else if (MAC_tx_addr_init)
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        add_rd       <=0;
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    else if (MAC_tx_addr_rd)
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        add_rd       <=add_rd + 1;
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assign MAC_tx_addr_data=dout;
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//******************************************************************************   
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//b port for read ,a port for write .
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//******************************************************************************
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duram #(8,3,"M512","DUAL_PORT") U_duram(
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.data_a         (din            ),
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.wren_a         (wr_en          ),
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.address_a      (add_wr         ),
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.address_b      (add_rd         ),
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.clock_a        (Clk            ),
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.clock_b        (Clk            ),
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.q_b            (dout           ));
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endmodule
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