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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [MAC_tx/] [Ramdon_gen.v] - Blame information for rev 33

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1 5 maverickis
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Ramdon_gen.v                                                ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Jon Gao (gaojon@yahoo.com)                            ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//                                                                    
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// CVS Revision History                                               
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//                                                                    
41 6 maverickis
// $Log: not supported by cvs2svn $
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// Revision 1.2  2005/12/16 06:44:19  Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
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// no message
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//                                           
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module Ramdon_gen(
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Reset           ,
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Clk             ,
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Init            ,
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RetryCnt        ,
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Random_time_meet
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);
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input           Reset           ;
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input           Clk             ;
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input           Init            ;
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input   [3:0]   RetryCnt        ;
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output          Random_time_meet;
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//******************************************************************************
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//internal signals                                                              
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//******************************************************************************
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reg [9:0]       Random_sequence ;
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reg [9:0]       Ramdom          ;
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reg [9:0]       Ramdom_counter  ;
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reg [7:0]       Slot_time_counter; //256*2=512bit=1 slot time
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reg             Random_time_meet;
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//******************************************************************************
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always @ (posedge Clk or posedge Reset)
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    if (Reset)
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        Random_sequence     <=0;
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    else
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        Random_sequence     <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])};
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always @ (RetryCnt or Random_sequence)
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    case (RetryCnt)
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        4'h0    :   Ramdom={9'b0,Random_sequence[0]};
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        4'h1    :   Ramdom={8'b0,Random_sequence[1:0]};
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        4'h2    :   Ramdom={7'b0,Random_sequence[2:0]};
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        4'h3    :   Ramdom={6'b0,Random_sequence[3:0]};
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        4'h4    :   Ramdom={5'b0,Random_sequence[4:0]};
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        4'h5    :   Ramdom={4'b0,Random_sequence[5:0]};
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        4'h6    :   Ramdom={3'b0,Random_sequence[6:0]};
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        4'h7    :   Ramdom={2'b0,Random_sequence[7:0]};
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        4'h8    :   Ramdom={1'b0,Random_sequence[8:0]};
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        4'h9    :   Ramdom={     Random_sequence[9:0]};
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        default :   Ramdom={     Random_sequence[9:0]};
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    endcase
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always @ (posedge Clk or posedge Reset)
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    if (Reset)
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        Slot_time_counter       <=0;
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    else if(Init)
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        Slot_time_counter       <=0;
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    else if(!Random_time_meet)
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        Slot_time_counter       <=Slot_time_counter+1;
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always @ (posedge Clk or posedge Reset)
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    if (Reset)
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        Ramdom_counter      <=0;
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    else if (Init)
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        Ramdom_counter      <=Ramdom;
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    else if (Ramdom_counter!=0&&Slot_time_counter==255)
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        Ramdom_counter      <=Ramdom_counter -1 ;
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always @ (posedge Clk or posedge Reset)
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    if (Reset)
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        Random_time_meet    <=1;
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    else if (Init)
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        Random_time_meet    <=0;
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    else if (Ramdom_counter==0)
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        Random_time_meet    <=1;
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endmodule
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