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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [Phy_int.v] - Blame information for rev 5

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Phy_int.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $ 
 
module Phy_int (
Reset                           ,
MAC_rx_clk                      ,
MAC_tx_clk                      ,
//Rx interface      ,
MCrs_dv                         ,
MRxD                            ,
MRxErr                          ,
//Tx interface      ,
MTxD                    ,
MTxEn               ,
MCRS                            ,
//Phy interface     ,
Tx_er                           ,
Tx_en                           ,
Txd                                     ,
Rx_er                           ,
Rx_dv                           ,
Rxd                                     ,
Crs                                     ,
Col                                     ,
//host interface    ,
Line_loop_en            ,
Speed
 
);
input                   Reset                           ;
input                   MAC_rx_clk                      ;
input                   MAC_tx_clk                      ;
                                //Rx interface
output                  MCrs_dv                         ;
output  [7:0]    MRxD                            ;
output                  MRxErr                          ;
                                //Tx interface
input   [7:0]    MTxD                    ;
input                   MTxEn               ;
output                  MCRS                            ;
                                //Phy interface
output                  Tx_er                           ;
output                  Tx_en                           ;
output  [7:0]    Txd                                     ;
input                   Rx_er                           ;
input                   Rx_dv                           ;
input   [7:0]    Rxd                                     ;
input                   Crs                                     ;
input                   Col                                     ;
                                //host interface
input                   Line_loop_en            ;
input   [2:0]    Speed                           ;
//******************************************************************************
//internal signals                                                              
//******************************************************************************
reg             [7:0]    MTxD_dl1                ;
reg                             MTxEn_dl1               ;
reg                             Tx_odd_data_ptr         ;
reg                             Rx_odd_data_ptr         ;
reg                             Tx_en                           ;
reg             [7:0]    Txd                                     ;
reg                             MCrs_dv                         ;
reg             [7:0]    MRxD                            ;
reg                             Rx_er_dl1                       ;
reg                             Rx_dv_dl1                       ;
reg             [7:0]    Rxd_dl1                         ;
reg             [7:0]    Rxd_dl2                         ;
reg                             Crs_dl1                         ;
reg                             Col_dl1                         ;
//******************************************************************************
//Tx control                                                              
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_tx_clk or posedge Reset)
        if (Reset)
                begin
                MTxD_dl1                        <=0;
        MTxEn_dl1               <=0;
        end
    else
                begin
                MTxD_dl1                        <=MTxD  ;
        MTxEn_dl1               <=MTxEn ;
        end
 
always @ (posedge MAC_tx_clk or posedge Reset)
        if (Reset)
                Tx_odd_data_ptr         <=0;
        else if (!MTxD_dl1)
                Tx_odd_data_ptr         <=0;
        else
                Tx_odd_data_ptr         <=!Tx_odd_data_ptr;
 
 
always @ (posedge MAC_tx_clk or posedge Reset)
        if (Reset)
                Txd                                     <=0;
        else if(Speed[2]&&MTxEn_dl1)
                Txd                                     <=MTxD_dl1;
        else if(MTxEn_dl1&&!Tx_odd_data_ptr)
                Txd                                     <={4'b0,MTxD_dl1[3:0]};
        else if(MTxEn_dl1&&Tx_odd_data_ptr)
                Txd                                     <={4'b0,MTxD_dl1[7:4]};
        else
                Txd                                     <=0;
 
always @ (posedge MAC_tx_clk or posedge Reset)
        if (Reset)
                Tx_en                           <=0;
        else if(MTxEn_dl1)
                Tx_en                           <=MTxEn_dl1;
 
assign Tx_er=0;
 
//******************************************************************************
//Rx control                                                              
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_rx_clk or posedge Reset)
        if (Reset)
                begin
                Rx_er_dl1                       <=0;
                Rx_dv_dl1               <=0;
                Rxd_dl1                 <=0;
                Rxd_dl2                 <=0;
                Crs_dl1                 <=0;
                Col_dl1                 <=0;
                end
        else
                begin
                Rx_er_dl1                       <=Rx_er         ;
                Rx_dv_dl1               <=Rx_dv         ;
                Rxd_dl1                 <=Rxd           ;
                Rxd_dl2                 <=Rxd_dl1       ;
                Crs_dl1                 <=Crs           ;
                Col_dl1                 <=Col           ;
                end
 
 
 
assign MRxErr   =Rx_er_dl1              ;
assign MCRS     =Crs_dl1                ;
 
always @ (posedge MAC_rx_clk or posedge Reset)
        if (Reset)
                MCrs_dv                 <=0;
        else if(Line_loop_en)
                MCrs_dv                 <=Tx_en;
        else if(Rx_dv_dl1)
                MCrs_dv                 <=1;
        else
                MCrs_dv                 <=0;
 
always @ (posedge MAC_rx_clk or posedge Reset)
        if (Reset)
                Rx_odd_data_ptr         <=0;
        else if (!Rx_dv_dl1)
                Rx_odd_data_ptr         <=0;
        else
                Rx_odd_data_ptr         <=!Rx_odd_data_ptr;
 
always @ (posedge MAC_rx_clk or posedge Reset)
        if (Reset)
                MRxD                    <=0;
        else if(Line_loop_en)
                MRxD                    <=Txd;
        else if(Speed[2]&&Rx_dv_dl1)
                MRxD                    <=Rxd_dl1;
        else if(Rx_dv_dl1&&Rx_odd_data_ptr)
                MRxD                    <={Rxd_dl1[3:0],Rxd_dl2[3:0]};
 
 
endmodule

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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [Phy_int.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Phy_int.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42
43			`module Phy_int (`
44			`Reset ,`
45			`MAC_rx_clk ,`
46			`MAC_tx_clk ,`
47			`//Rx interface ,`
48			`MCrs_dv ,`
49			`MRxD ,`
50			`MRxErr ,`
51			`//Tx interface ,`
52			`MTxD ,`
53			`MTxEn ,`
54			`MCRS ,`
55			`//Phy interface ,`
56			`Tx_er ,`
57			`Tx_en ,`
58			`Txd ,`
59			`Rx_er ,`
60			`Rx_dv ,`
61			`Rxd ,`
62			`Crs ,`
63			`Col ,`
64			`//host interface ,`
65			`Line_loop_en ,`
66			`Speed`
67
68			`);`
69			`input Reset ;`
70			`input MAC_rx_clk ;`
71			`input MAC_tx_clk ;`
72			`//Rx interface`
73			`output MCrs_dv ;`
74			`output [7:0] MRxD ;`
75			`output MRxErr ;`
76			`//Tx interface`
77			`input [7:0] MTxD ;`
78			`input MTxEn ;`
79			`output MCRS ;`
80			`//Phy interface`
81			`output Tx_er ;`
82			`output Tx_en ;`
83			`output [7:0] Txd ;`
84			`input Rx_er ;`
85			`input Rx_dv ;`
86			`input [7:0] Rxd ;`
87			`input Crs ;`
88			`input Col ;`
89			`//host interface`
90			`input Line_loop_en ;`
91			`input [2:0] Speed ;`
92			`//******************************************************************************`
93			`//internal signals`
94			`//******************************************************************************`
95			`reg [7:0] MTxD_dl1 ;`
96			`reg MTxEn_dl1 ;`
97			`reg Tx_odd_data_ptr ;`
98			`reg Rx_odd_data_ptr ;`
99			`reg Tx_en ;`
100			`reg [7:0] Txd ;`
101			`reg MCrs_dv ;`
102			`reg [7:0] MRxD ;`
103			`reg Rx_er_dl1 ;`
104			`reg Rx_dv_dl1 ;`
105			`reg [7:0] Rxd_dl1 ;`
106			`reg [7:0] Rxd_dl2 ;`
107			`reg Crs_dl1 ;`
108			`reg Col_dl1 ;`
109			`//******************************************************************************`
110			`//Tx control`
111			`//******************************************************************************`
112			`//reg boundery signals`
113			`always @ (posedge MAC_tx_clk or posedge Reset)`
114			`if (Reset)`
115			`begin`
116			`MTxD_dl1 <=0;`
117			`MTxEn_dl1 <=0;`
118			`end`
119			`else`
120			`begin`
121			`MTxD_dl1 <=MTxD ;`
122			`MTxEn_dl1 <=MTxEn ;`
123			`end`
124
125			`always @ (posedge MAC_tx_clk or posedge Reset)`
126			`if (Reset)`
127			`Tx_odd_data_ptr <=0;`
128			`else if (!MTxD_dl1)`
129			`Tx_odd_data_ptr <=0;`
130			`else`
131			`Tx_odd_data_ptr <=!Tx_odd_data_ptr;`
132
133
134			`always @ (posedge MAC_tx_clk or posedge Reset)`
135			`if (Reset)`
136			`Txd <=0;`
137			`else if(Speed[2]&&MTxEn_dl1)`
138			`Txd <=MTxD_dl1;`
139			`else if(MTxEn_dl1&&!Tx_odd_data_ptr)`
140			`Txd <={4'b0,MTxD_dl1[3:0]};`
141			`else if(MTxEn_dl1&&Tx_odd_data_ptr)`
142			`Txd <={4'b0,MTxD_dl1[7:4]};`
143			`else`
144			`Txd <=0;`
145
146			`always @ (posedge MAC_tx_clk or posedge Reset)`
147			`if (Reset)`
148			`Tx_en <=0;`
149			`else if(MTxEn_dl1)`
150			`Tx_en <=MTxEn_dl1;`
151
152			`assign Tx_er=0;`
153
154			`//******************************************************************************`
155			`//Rx control`
156			`//******************************************************************************`
157			`//reg boundery signals`
158			`always @ (posedge MAC_rx_clk or posedge Reset)`
159			`if (Reset)`
160			`begin`
161			`Rx_er_dl1 <=0;`
162			`Rx_dv_dl1 <=0;`
163			`Rxd_dl1 <=0;`
164			`Rxd_dl2 <=0;`
165			`Crs_dl1 <=0;`
166			`Col_dl1 <=0;`
167			`end`
168			`else`
169			`begin`
170			`Rx_er_dl1 <=Rx_er ;`
171			`Rx_dv_dl1 <=Rx_dv ;`
172			`Rxd_dl1 <=Rxd ;`
173			`Rxd_dl2 <=Rxd_dl1 ;`
174			`Crs_dl1 <=Crs ;`
175			`Col_dl1 <=Col ;`
176			`end`
177
178
179
180			`assign MRxErr =Rx_er_dl1 ;`
181			`assign MCRS =Crs_dl1 ;`
182
183			`always @ (posedge MAC_rx_clk or posedge Reset)`
184			`if (Reset)`
185			`MCrs_dv <=0;`
186			`else if(Line_loop_en)`
187			`MCrs_dv <=Tx_en;`
188			`else if(Rx_dv_dl1)`
189			`MCrs_dv <=1;`
190			`else`
191			`MCrs_dv <=0;`
192
193			`always @ (posedge MAC_rx_clk or posedge Reset)`
194			`if (Reset)`
195			`Rx_odd_data_ptr <=0;`
196			`else if (!Rx_dv_dl1)`
197			`Rx_odd_data_ptr <=0;`
198			`else`
199			`Rx_odd_data_ptr <=!Rx_odd_data_ptr;`
200
201			`always @ (posedge MAC_rx_clk or posedge Reset)`
202			`if (Reset)`
203			`MRxD <=0;`
204			`else if(Line_loop_en)`
205			`MRxD <=Txd;`
206			`else if(Speed[2]&&Rx_dv_dl1)`
207			`MRxD <=Rxd_dl1;`
208			`else if(Rx_dv_dl1&&Rx_odd_data_ptr)`
209			`MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};`
210
211
212			`endmodule`