URL https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk

Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [Phy_int.v] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Phy_int.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.2  2005/12/13 12:15:36  Administrator
// no message
//
// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
// no message
// 
 
module Phy_int (
Reset                           ,
MAC_rx_clk                      ,
MAC_tx_clk                      ,
//Rx interface      ,
MCrs_dv                         ,
MRxD                            ,
MRxErr                          ,
//Tx interface      ,
MTxD                    ,
MTxEn               ,
MCRS                            ,
//Phy interface     ,
Tx_er                           ,
Tx_en                           ,
Txd                                     ,
Rx_er                           ,
Rx_dv                           ,
Rxd                                     ,
Crs                                     ,
Col                                     ,
//host interface    ,
Line_loop_en            ,
Speed
 
);
input                   Reset                           ;
input                   MAC_rx_clk                      ;
input                   MAC_tx_clk                      ;
                                //Rx interface
output                  MCrs_dv                         ;
output  [7:0]    MRxD                            ;
output                  MRxErr                          ;
                                //Tx interface
input   [7:0]    MTxD                    ;
input                   MTxEn               ;
output                  MCRS                            ;
                                //Phy interface
output                  Tx_er                           ;
output                  Tx_en                           ;
output  [7:0]    Txd                                     ;
input                   Rx_er                           ;
input                   Rx_dv                           ;
input   [7:0]    Rxd                                     ;
input                   Crs                                     ;
input                   Col                                     ;
                                //host interface
input                   Line_loop_en            ;
input   [2:0]    Speed                           ;
//******************************************************************************
//internal signals                                                              
//******************************************************************************
reg             [7:0]    MTxD_dl1                ;
reg                             MTxEn_dl1               ;
reg                             Tx_odd_data_ptr         ;
reg                             Rx_odd_data_ptr         ;
reg                             Tx_en                           ;
reg             [7:0]    Txd                                     ;
reg                             MCrs_dv                         ;
reg             [7:0]    MRxD                            ;
reg                             Rx_er_dl1                       ;
reg                             Rx_dv_dl1                       ;
reg                             Rx_dv_dl2                       ;
reg             [7:0]    Rxd_dl1                         ;
reg             [7:0]    Rxd_dl2                         ;
reg                             Crs_dl1                         ;
reg                             Col_dl1                         ;
//******************************************************************************
//Tx control                                                              
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_tx_clk or posedge Reset)
        if (Reset)
                begin
                MTxD_dl1                        <=0;
        MTxEn_dl1               <=0;
        end
    else
                begin
                MTxD_dl1                        <=MTxD  ;
        MTxEn_dl1               <=MTxEn ;
        end
 
always @ (posedge MAC_tx_clk or posedge Reset)
        if (Reset)
                Tx_odd_data_ptr         <=0;
        else if (!MTxD_dl1)
                Tx_odd_data_ptr         <=0;
        else
                Tx_odd_data_ptr         <=!Tx_odd_data_ptr;
 
 
always @ (posedge MAC_tx_clk or posedge Reset)
        if (Reset)
                Txd                                     <=0;
        else if(Speed[2]&&MTxEn_dl1)
                Txd                                     <=MTxD_dl1;
        else if(MTxEn_dl1&&!Tx_odd_data_ptr)
                Txd                                     <={4'b0,MTxD_dl1[3:0]};
        else if(MTxEn_dl1&&Tx_odd_data_ptr)
                Txd                                     <={4'b0,MTxD_dl1[7:4]};
        else
                Txd                                     <=0;
 
always @ (posedge MAC_tx_clk or posedge Reset)
        if (Reset)
                Tx_en                           <=0;
        else if(MTxEn_dl1)
                Tx_en                           <=1;
        else
                Tx_en                           <=0;
 
assign Tx_er=0;
 
//******************************************************************************
//Rx control                                                              
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_rx_clk or posedge Reset)
        if (Reset)
                begin
                Rx_er_dl1                       <=0;
                Rx_dv_dl1               <=0;
                Rx_dv_dl2                       <=0      ;
                Rxd_dl1                 <=0;
                Rxd_dl2                 <=0;
                Crs_dl1                 <=0;
                Col_dl1                 <=0;
                end
        else
                begin
                Rx_er_dl1                       <=Rx_er         ;
                Rx_dv_dl1               <=Rx_dv         ;
                Rx_dv_dl2                       <=Rx_dv_dl1     ;
                Rxd_dl1                 <=Rxd           ;
                Rxd_dl2                 <=Rxd_dl1       ;
                Crs_dl1                 <=Crs           ;
                Col_dl1                 <=Col           ;
                end
 
assign MRxErr   =Rx_er_dl1              ;
assign MCRS     =Crs_dl1                ;
 
always @ (posedge MAC_rx_clk or posedge Reset)
        if (Reset)
                MCrs_dv                 <=0;
        else if(Line_loop_en)
                MCrs_dv                 <=Tx_en;
        else if(Rx_dv_dl2)
                MCrs_dv                 <=1;
        else
                MCrs_dv                 <=0;
 
always @ (posedge MAC_rx_clk or posedge Reset)
        if (Reset)
                Rx_odd_data_ptr         <=0;
        else if (!Rx_dv_dl1)
                Rx_odd_data_ptr         <=0;
        else
                Rx_odd_data_ptr         <=!Rx_odd_data_ptr;
 
always @ (posedge MAC_rx_clk or posedge Reset)
        if (Reset)
                MRxD                    <=0;
        else if(Line_loop_en)
                MRxD                    <=Txd;
        else if(Speed[2]&&Rx_dv_dl2)
                MRxD                    <=Rxd_dl2;
        else if(Rx_dv_dl1&&Rx_odd_data_ptr)
                MRxD                    <={Rxd_dl1[3:0],Rxd_dl2[3:0]};
 
 
endmodule

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Phy_int.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41	6	maverickis	`// $Log: not supported by cvs2svn $`
42			`// Revision 1.2 2005/12/13 12:15:36 Administrator`
43			`// no message`
44			`//`
45			`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`
46			`// no message`
47			`//`
48	5	maverickis
49			`module Phy_int (`
50			`Reset ,`
51			`MAC_rx_clk ,`
52			`MAC_tx_clk ,`
53			`//Rx interface ,`
54			`MCrs_dv ,`
55			`MRxD ,`
56			`MRxErr ,`
57			`//Tx interface ,`
58			`MTxD ,`
59			`MTxEn ,`
60			`MCRS ,`
61			`//Phy interface ,`
62			`Tx_er ,`
63			`Tx_en ,`
64			`Txd ,`
65			`Rx_er ,`
66			`Rx_dv ,`
67			`Rxd ,`
68			`Crs ,`
69			`Col ,`
70			`//host interface ,`
71			`Line_loop_en ,`
72			`Speed`
73
74			`);`
75			`input Reset ;`
76			`input MAC_rx_clk ;`
77			`input MAC_tx_clk ;`
78			`//Rx interface`
79			`output MCrs_dv ;`
80			`output [7:0] MRxD ;`
81			`output MRxErr ;`
82			`//Tx interface`
83			`input [7:0] MTxD ;`
84			`input MTxEn ;`
85			`output MCRS ;`
86			`//Phy interface`
87			`output Tx_er ;`
88			`output Tx_en ;`
89			`output [7:0] Txd ;`
90			`input Rx_er ;`
91			`input Rx_dv ;`
92			`input [7:0] Rxd ;`
93			`input Crs ;`
94			`input Col ;`
95			`//host interface`
96			`input Line_loop_en ;`
97			`input [2:0] Speed ;`
98			`//******************************************************************************`
99			`//internal signals`
100			`//******************************************************************************`
101			`reg [7:0] MTxD_dl1 ;`
102			`reg MTxEn_dl1 ;`
103			`reg Tx_odd_data_ptr ;`
104			`reg Rx_odd_data_ptr ;`
105			`reg Tx_en ;`
106			`reg [7:0] Txd ;`
107			`reg MCrs_dv ;`
108			`reg [7:0] MRxD ;`
109			`reg Rx_er_dl1 ;`
110			`reg Rx_dv_dl1 ;`
111	6	maverickis	`reg Rx_dv_dl2 ;`
112	5	maverickis	`reg [7:0] Rxd_dl1 ;`
113			`reg [7:0] Rxd_dl2 ;`
114			`reg Crs_dl1 ;`
115			`reg Col_dl1 ;`
116			`//******************************************************************************`
117			`//Tx control`
118			`//******************************************************************************`
119			`//reg boundery signals`
120			`always @ (posedge MAC_tx_clk or posedge Reset)`
121			`if (Reset)`
122			`begin`
123			`MTxD_dl1 <=0;`
124			`MTxEn_dl1 <=0;`
125			`end`
126			`else`
127			`begin`
128			`MTxD_dl1 <=MTxD ;`
129			`MTxEn_dl1 <=MTxEn ;`
130			`end`
131
132			`always @ (posedge MAC_tx_clk or posedge Reset)`
133			`if (Reset)`
134			`Tx_odd_data_ptr <=0;`
135			`else if (!MTxD_dl1)`
136			`Tx_odd_data_ptr <=0;`
137			`else`
138			`Tx_odd_data_ptr <=!Tx_odd_data_ptr;`
139
140
141			`always @ (posedge MAC_tx_clk or posedge Reset)`
142			`if (Reset)`
143			`Txd <=0;`
144			`else if(Speed[2]&&MTxEn_dl1)`
145			`Txd <=MTxD_dl1;`
146			`else if(MTxEn_dl1&&!Tx_odd_data_ptr)`
147			`Txd <={4'b0,MTxD_dl1[3:0]};`
148			`else if(MTxEn_dl1&&Tx_odd_data_ptr)`
149			`Txd <={4'b0,MTxD_dl1[7:4]};`
150			`else`
151			`Txd <=0;`
152
153			`always @ (posedge MAC_tx_clk or posedge Reset)`
154			`if (Reset)`
155			`Tx_en <=0;`
156			`else if(MTxEn_dl1)`
157	6	maverickis	`Tx_en <=1;`
158			`else`
159			`Tx_en <=0;`
160	5	maverickis
161			`assign Tx_er=0;`
162
163			`//******************************************************************************`
164			`//Rx control`
165			`//******************************************************************************`
166			`//reg boundery signals`
167			`always @ (posedge MAC_rx_clk or posedge Reset)`
168			`if (Reset)`
169			`begin`
170			`Rx_er_dl1 <=0;`
171			`Rx_dv_dl1 <=0;`
172	6	maverickis	`Rx_dv_dl2 <=0 ;`
173	5	maverickis	`Rxd_dl1 <=0;`
174			`Rxd_dl2 <=0;`
175			`Crs_dl1 <=0;`
176			`Col_dl1 <=0;`
177			`end`
178			`else`
179			`begin`
180			`Rx_er_dl1 <=Rx_er ;`
181			`Rx_dv_dl1 <=Rx_dv ;`
182	6	maverickis	`Rx_dv_dl2 <=Rx_dv_dl1 ;`
183	5	maverickis	`Rxd_dl1 <=Rxd ;`
184			`Rxd_dl2 <=Rxd_dl1 ;`
185			`Crs_dl1 <=Crs ;`
186			`Col_dl1 <=Col ;`
187			`end`
188
189			`assign MRxErr =Rx_er_dl1 ;`
190			`assign MCRS =Crs_dl1 ;`
191
192			`always @ (posedge MAC_rx_clk or posedge Reset)`
193			`if (Reset)`
194			`MCrs_dv <=0;`
195			`else if(Line_loop_en)`
196			`MCrs_dv <=Tx_en;`
197	6	maverickis	`else if(Rx_dv_dl2)`
198	5	maverickis	`MCrs_dv <=1;`
199			`else`
200			`MCrs_dv <=0;`
201
202			`always @ (posedge MAC_rx_clk or posedge Reset)`
203			`if (Reset)`
204			`Rx_odd_data_ptr <=0;`
205			`else if (!Rx_dv_dl1)`
206			`Rx_odd_data_ptr <=0;`
207			`else`
208			`Rx_odd_data_ptr <=!Rx_odd_data_ptr;`
209
210			`always @ (posedge MAC_rx_clk or posedge Reset)`
211			`if (Reset)`
212			`MRxD <=0;`
213			`else if(Line_loop_en)`
214			`MRxD <=Txd;`
215	6	maverickis	`else if(Speed[2]&&Rx_dv_dl2)`
216			`MRxD <=Rxd_dl2;`
217	5	maverickis	`else if(Rx_dv_dl1&&Rx_odd_data_ptr)`
218			`MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};`
219
220
221			`endmodule`

Browse

Tools

Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [Phy_int.v] - Blame information for rev 6