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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Phy_int.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.3  2005/12/16 06:44:14  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2  2005/12/13 12:15:36  Administrator
// no message
//
// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
// no message
// 
 
module Phy_int (
Reset               ,
MAC_rx_clk          ,
MAC_tx_clk          ,
//Rx interface      ,
MCrs_dv             ,
MRxD                ,
MRxErr              ,
//Tx interface      ,
MTxD                ,
MTxEn               ,
MCRS                ,
//Phy interface     ,
Tx_er               ,
Tx_en               ,
Txd                 ,
Rx_er               ,
Rx_dv               ,
Rxd                 ,
Crs                 ,
Col                 ,
//host interface    ,
Line_loop_en        ,
Speed
 
);
input           Reset               ;
input           MAC_rx_clk          ;
input           MAC_tx_clk          ;
                //Rx interface
output          MCrs_dv             ;
output  [7:0]   MRxD                ;
output          MRxErr              ;
                //Tx interface
input   [7:0]   MTxD                ;
input           MTxEn               ;
output          MCRS                ;
                //Phy interface
output          Tx_er               ;
output          Tx_en               ;
output  [7:0]   Txd                 ;
input           Rx_er               ;
input           Rx_dv               ;
input   [7:0]   Rxd                 ;
input           Crs                 ;
input           Col                 ;
                //host interface
input           Line_loop_en        ;
input   [2:0]   Speed               ;
//******************************************************************************
//internal signals                                                              
//******************************************************************************
reg     [7:0]   MTxD_dl1            ;
reg             MTxEn_dl1           ;
reg             Tx_odd_data_ptr     ;
reg             Rx_odd_data_ptr     ;
reg             Tx_en               ;
reg     [7:0]   Txd                 ;
reg             MCrs_dv             ;
reg     [7:0]   MRxD                ;
reg             Rx_er_dl1           ;
reg             Rx_dv_dl1           ;
reg             Rx_dv_dl2           ;
reg     [7:0]   Rxd_dl1             ;
reg     [7:0]   Rxd_dl2             ;
reg             Crs_dl1             ;
reg             Col_dl1             ;
//******************************************************************************
//Tx control                                                              
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_tx_clk or posedge Reset)
    if (Reset)
        begin
        MTxD_dl1            <=0;
        MTxEn_dl1           <=0;
        end
    else
        begin
        MTxD_dl1            <=MTxD  ;
        MTxEn_dl1           <=MTxEn ;
        end
 
always @ (posedge MAC_tx_clk or posedge Reset)
    if (Reset)
        Tx_odd_data_ptr     <=0;
    else if (!MTxD_dl1)
        Tx_odd_data_ptr     <=0;
    else
        Tx_odd_data_ptr     <=!Tx_odd_data_ptr;
 
 
always @ (posedge MAC_tx_clk or posedge Reset)
    if (Reset)
        Txd                 <=0;
    else if(Speed[2]&&MTxEn_dl1)
        Txd                 <=MTxD_dl1;
    else if(MTxEn_dl1&&!Tx_odd_data_ptr)
        Txd                 <={4'b0,MTxD_dl1[3:0]};
    else if(MTxEn_dl1&&Tx_odd_data_ptr)
        Txd                 <={4'b0,MTxD_dl1[7:4]};
    else
        Txd                 <=0;
 
always @ (posedge MAC_tx_clk or posedge Reset)
    if (Reset)
        Tx_en               <=0;
    else if(MTxEn_dl1)
        Tx_en               <=1;
    else
        Tx_en               <=0;
 
assign Tx_er=0;
 
//******************************************************************************
//Rx control                                                              
//******************************************************************************
//reg boundery signals
always @ (posedge MAC_rx_clk or posedge Reset)
    if (Reset)
        begin
        Rx_er_dl1           <=0;
        Rx_dv_dl1           <=0;
        Rx_dv_dl2           <=0 ;
        Rxd_dl1             <=0;
        Rxd_dl2             <=0;
        Crs_dl1             <=0;
        Col_dl1             <=0;
        end
    else
        begin
        Rx_er_dl1           <=Rx_er     ;
        Rx_dv_dl1           <=Rx_dv     ;
        Rx_dv_dl2           <=Rx_dv_dl1 ;
        Rxd_dl1             <=Rxd       ;
        Rxd_dl2             <=Rxd_dl1   ;
        Crs_dl1             <=Crs       ;
        Col_dl1             <=Col       ;
        end
 
assign MRxErr   =Rx_er_dl1      ;
assign MCRS     =Crs_dl1        ;
 
always @ (posedge MAC_rx_clk or posedge Reset)
    if (Reset)
        MCrs_dv         <=0;
    else if(Line_loop_en)
        MCrs_dv         <=Tx_en;
    else if(Rx_dv_dl2)
        MCrs_dv         <=1;
    else
        MCrs_dv         <=0;
 
always @ (posedge MAC_rx_clk or posedge Reset)
    if (Reset)
        Rx_odd_data_ptr     <=0;
    else if (!Rx_dv_dl1)
        Rx_odd_data_ptr     <=0;
    else
        Rx_odd_data_ptr     <=!Rx_odd_data_ptr;
 
always @ (posedge MAC_rx_clk or posedge Reset)
    if (Reset)
        MRxD            <=0;
    else if(Line_loop_en)
        MRxD            <=Txd;
    else if(Speed[2]&&Rx_dv_dl2)
        MRxD            <=Rxd_dl2;
    else if(Rx_dv_dl1&&Rx_odd_data_ptr)
        MRxD            <={Rxd_dl1[3:0],Rxd_dl2[3:0]};
 
endmodule

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Phy_int.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9	7	maverickis	`//// - Jon Gao (gaojon@yahoo.com) ////`
10	5	maverickis	`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41	6	maverickis	`// $Log: not supported by cvs2svn $`
42	7	maverickis	`// Revision 1.3 2005/12/16 06:44:14 Administrator`
43			`// replaced tab with space.`
44			`// passed 9.6k length frame test.`
45			`//`
46	6	maverickis	`// Revision 1.2 2005/12/13 12:15:36 Administrator`
47			`// no message`
48			`//`
49			`// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator`
50			`// no message`
51			`//`
52	5	maverickis
53			`module Phy_int (`
54	7	maverickis	`Reset ,`
55			`MAC_rx_clk ,`
56			`MAC_tx_clk ,`
57	5	maverickis	`//Rx interface ,`
58	7	maverickis	`MCrs_dv ,`
59			`MRxD ,`
60			`MRxErr ,`
61	5	maverickis	`//Tx interface ,`
62	7	maverickis	`MTxD ,`
63			`MTxEn ,`
64			`MCRS ,`
65	5	maverickis	`//Phy interface ,`
66	7	maverickis	`Tx_er ,`
67			`Tx_en ,`
68			`Txd ,`
69			`Rx_er ,`
70			`Rx_dv ,`
71			`Rxd ,`
72			`Crs ,`
73			`Col ,`
74	5	maverickis	`//host interface ,`
75	7	maverickis	`Line_loop_en ,`
76			`Speed`
77	5	maverickis
78			`);`
79	7	maverickis	`input Reset ;`
80			`input MAC_rx_clk ;`
81			`input MAC_tx_clk ;`
82			`//Rx interface`
83			`output MCrs_dv ;`
84			`output [7:0] MRxD ;`
85			`output MRxErr ;`
86			`//Tx interface`
87			`input [7:0] MTxD ;`
88			`input MTxEn ;`
89			`output MCRS ;`
90			`//Phy interface`
91			`output Tx_er ;`
92			`output Tx_en ;`
93			`output [7:0] Txd ;`
94			`input Rx_er ;`
95			`input Rx_dv ;`
96			`input [7:0] Rxd ;`
97			`input Crs ;`
98			`input Col ;`
99			`//host interface`
100			`input Line_loop_en ;`
101			`input [2:0] Speed ;`
102	5	maverickis	`//******************************************************************************`
103			`//internal signals`
104			`//******************************************************************************`
105	7	maverickis	`reg [7:0] MTxD_dl1 ;`
106			`reg MTxEn_dl1 ;`
107			`reg Tx_odd_data_ptr ;`
108			`reg Rx_odd_data_ptr ;`
109			`reg Tx_en ;`
110			`reg [7:0] Txd ;`
111			`reg MCrs_dv ;`
112			`reg [7:0] MRxD ;`
113			`reg Rx_er_dl1 ;`
114			`reg Rx_dv_dl1 ;`
115			`reg Rx_dv_dl2 ;`
116			`reg [7:0] Rxd_dl1 ;`
117			`reg [7:0] Rxd_dl2 ;`
118			`reg Crs_dl1 ;`
119			`reg Col_dl1 ;`
120	5	maverickis	`//******************************************************************************`
121			`//Tx control`
122			`//******************************************************************************`
123			`//reg boundery signals`
124			`always @ (posedge MAC_tx_clk or posedge Reset)`
125	7	maverickis	`if (Reset)`
126			`begin`
127			`MTxD_dl1 <=0;`
128			`MTxEn_dl1 <=0;`
129	5	maverickis	`end`
130			`else`
131	7	maverickis	`begin`
132			`MTxD_dl1 <=MTxD ;`
133			`MTxEn_dl1 <=MTxEn ;`
134	5	maverickis	`end`
135
136			`always @ (posedge MAC_tx_clk or posedge Reset)`
137	7	maverickis	`if (Reset)`
138			`Tx_odd_data_ptr <=0;`
139			`else if (!MTxD_dl1)`
140			`Tx_odd_data_ptr <=0;`
141			`else`
142			`Tx_odd_data_ptr <=!Tx_odd_data_ptr;`
143
144	5	maverickis
145			`always @ (posedge MAC_tx_clk or posedge Reset)`
146	7	maverickis	`if (Reset)`
147			`Txd <=0;`
148			`else if(Speed[2]&&MTxEn_dl1)`
149			`Txd <=MTxD_dl1;`
150			`else if(MTxEn_dl1&&!Tx_odd_data_ptr)`
151			`Txd <={4'b0,MTxD_dl1[3:0]};`
152			`else if(MTxEn_dl1&&Tx_odd_data_ptr)`
153			`Txd <={4'b0,MTxD_dl1[7:4]};`
154			`else`
155			`Txd <=0;`
156	5	maverickis
157			`always @ (posedge MAC_tx_clk or posedge Reset)`
158	7	maverickis	`if (Reset)`
159			`Tx_en <=0;`
160			`else if(MTxEn_dl1)`
161			`Tx_en <=1;`
162			`else`
163			`Tx_en <=0;`
164	5	maverickis
165			`assign Tx_er=0;`
166
167			`//******************************************************************************`
168			`//Rx control`
169			`//******************************************************************************`
170			`//reg boundery signals`
171			`always @ (posedge MAC_rx_clk or posedge Reset)`
172	7	maverickis	`if (Reset)`
173			`begin`
174			`Rx_er_dl1 <=0;`
175			`Rx_dv_dl1 <=0;`
176			`Rx_dv_dl2 <=0 ;`
177			`Rxd_dl1 <=0;`
178			`Rxd_dl2 <=0;`
179			`Crs_dl1 <=0;`
180			`Col_dl1 <=0;`
181			`end`
182			`else`
183			`begin`
184			`Rx_er_dl1 <=Rx_er ;`
185			`Rx_dv_dl1 <=Rx_dv ;`
186			`Rx_dv_dl2 <=Rx_dv_dl1 ;`
187			`Rxd_dl1 <=Rxd ;`
188			`Rxd_dl2 <=Rxd_dl1 ;`
189			`Crs_dl1 <=Crs ;`
190			`Col_dl1 <=Col ;`
191			`end`
192	5	maverickis
193	7	maverickis	`assign MRxErr =Rx_er_dl1 ;`
194			`assign MCRS =Crs_dl1 ;`
195	5	maverickis
196			`always @ (posedge MAC_rx_clk or posedge Reset)`
197	7	maverickis	`if (Reset)`
198			`MCrs_dv <=0;`
199			`else if(Line_loop_en)`
200			`MCrs_dv <=Tx_en;`
201			`else if(Rx_dv_dl2)`
202			`MCrs_dv <=1;`
203			`else`
204			`MCrs_dv <=0;`
205	5	maverickis
206			`always @ (posedge MAC_rx_clk or posedge Reset)`
207	7	maverickis	`if (Reset)`
208			`Rx_odd_data_ptr <=0;`
209			`else if (!Rx_dv_dl1)`
210			`Rx_odd_data_ptr <=0;`
211			`else`
212			`Rx_odd_data_ptr <=!Rx_odd_data_ptr;`
213
214	5	maverickis	`always @ (posedge MAC_rx_clk or posedge Reset)`
215	7	maverickis	`if (Reset)`
216			`MRxD <=0;`
217			`else if(Line_loop_en)`
218			`MRxD <=Txd;`
219			`else if(Speed[2]&&Rx_dv_dl2)`
220			`MRxD <=Rxd_dl2;`
221			`else if(Rx_dv_dl1&&Rx_odd_data_ptr)`
222			`MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]};`
223
224			`endmodule`

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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [Phy_int.v] - Blame information for rev 7