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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  RMON_CTRL.v                                             ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: not supported by cvs2svn $
// Revision 1.2  2005/12/16 06:44:19  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//  
module RMON_CTRL (
Clk             ,
Reset           ,
//RMON_CTRL        
Reg_apply_0     ,
Reg_addr_0      ,
Reg_data_0      ,
Reg_next_0      ,
Reg_apply_1     ,
Reg_addr_1      ,
Reg_data_1      ,
Reg_next_1      ,
//dual-port ram
Addra               ,
Dina                ,
Douta               ,
Wea                 ,
//CPU                  
CPU_rd_addr     ,
CPU_rd_apply        ,
CPU_rd_grant        ,
CPU_rd_dout
 
);
input           Clk             ;
input           Reset           ;
                //RMON_CTRL
input           Reg_apply_0     ;
input   [4:0]   Reg_addr_0      ;
input   [15:0]  Reg_data_0      ;
output          Reg_next_0      ;
input           Reg_apply_1     ;
input   [4:0]   Reg_addr_1      ;
input   [15:0]  Reg_data_1      ;
output          Reg_next_1      ;
                //dual-port ram 
                //port-a for Rmon  
output  [5:0]   Addra               ;
output  [31:0]  Dina                ;
input   [31:0]  Douta               ;
output          Wea                 ;
                //CPU
input   [5:0]   CPU_rd_addr         ;
input           CPU_rd_apply        ;
output          CPU_rd_grant        ;
output  [31:0]  CPU_rd_dout         ;
 
 
 
 
//******************************************************************************
//internal signals                                                              
//******************************************************************************
 
parameter       StateCPU        =5'd00;
parameter       StateMAC0       =5'd01;
parameter       StateMAC1       =5'd02;
 
 
reg [4:0]       CurrentState;
reg [4:0]       NextState;
reg [4:0]       CurrentState_reg;
 
reg [4:0]       StepCounter;
reg [31:0]      DoutaReg;
reg [5:0]       Addra               ;
reg [31:0]      Dina;
reg             Reg_next_0      ;
reg             Reg_next_1      ;
reg             Write;
reg             Read;
reg             Pipeline;
reg [31:0]      CPU_rd_dout         ;
reg             CPU_rd_apply_reg    ;
//******************************************************************************
//State Machine                                                            
//******************************************************************************
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        CurrentState    <=StateMAC0;
    else
        CurrentState    <=NextState;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        CurrentState_reg    <=StateMAC0;
    else if(CurrentState!=StateCPU)
        CurrentState_reg    <=CurrentState;
 
always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg
                                       or Reg_apply_1
                                       or StepCounter
                                       )
    case(CurrentState)
        StateMAC0:
            if(!Reg_apply_0&&CPU_rd_apply_reg)
                NextState   =StateCPU;
            else if(!Reg_apply_0)
                NextState   =StateMAC1;
            else
                NextState   =CurrentState;
        StateMAC1:
            if(!Reg_apply_1&&CPU_rd_apply_reg)
                NextState   =StateCPU;
            else if(!Reg_apply_1)
                NextState   =StateMAC0;
            else
                NextState   =CurrentState;
        StateCPU:
            if (StepCounter==3)
                case (CurrentState_reg)
                    StateMAC0   :NextState  =StateMAC0 ;
                    StateMAC1   :NextState  =StateMAC1 ;
                    default     :NextState  =StateMAC0;
                endcase
            else
                NextState   =CurrentState;
 
        default:
                NextState   =StateMAC0;
    endcase
 
 
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        StepCounter     <=0;
    else if(NextState!=CurrentState)
        StepCounter     <=0;
    else if (StepCounter!=4'hf)
        StepCounter     <=StepCounter + 1;
 
//******************************************************************************
//temp signals                                                            
//******************************************************************************
always @(StepCounter)
    if( StepCounter==1||StepCounter==4||
        StepCounter==7||StepCounter==10)
        Read    =1;
    else
        Read    =0;
 
always @(StepCounter or CurrentState)
    if( StepCounter==2||StepCounter==5||
        StepCounter==8||StepCounter==11)
        Pipeline    =1;
    else
        Pipeline    =0;
 
always @(StepCounter or CurrentState)
    if( StepCounter==3||StepCounter==6||
        StepCounter==9||StepCounter==12)
        Write   =1;
    else
        Write   =0;
 
always @(posedge Clk or posedge Reset)
    if (Reset)
        DoutaReg        <=0;
    else if (Read)
        DoutaReg        <=Douta;
 
 
//******************************************************************************
//gen output signals                                                        
//******************************************************************************    
//Addra 
always @(*)
    case(CurrentState)
        StateMAC0 :     Addra={1'd0 ,Reg_addr_0 };
        StateMAC1 :     Addra={1'd1 ,Reg_addr_1 };
        StateCPU:       Addra=CPU_rd_addr;
        default:        Addra=0;
        endcase
 
//Dina
always @(posedge Clk or posedge Reset)
    if (Reset)
        Dina    <=0;
    else
        case(CurrentState)
            StateMAC0 :     Dina<=Douta+Reg_data_0 ;
            StateMAC1 :     Dina<=Douta+Reg_data_1 ;
            StateCPU:       Dina<=0;
            default:        Dina<=0;
        endcase
 
assign  Wea     =Write;
//Reg_next
always @(CurrentState or Pipeline)
    if(CurrentState==StateMAC0)
        Reg_next_0  =Pipeline;
    else
        Reg_next_0  =0;
 
always @(CurrentState or Pipeline)
    if(CurrentState==StateMAC1)
        Reg_next_1  =Pipeline;
    else
        Reg_next_1  =0;
 
 
//CPU_rd_grant   
reg     CPU_rd_apply_dl1;
reg     CPU_rd_apply_dl2;
//rising edge
always @ (posedge Clk or posedge Reset)
    if (Reset)
        begin
        CPU_rd_apply_dl1        <=0;
        CPU_rd_apply_dl2        <=0;
        end
    else
        begin
        CPU_rd_apply_dl1        <=CPU_rd_apply;
        CPU_rd_apply_dl2        <=CPU_rd_apply_dl1;
        end
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        CPU_rd_apply_reg    <=0;
    else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)
        CPU_rd_apply_reg    <=1;
    else if (CurrentState==StateCPU&&Write)
        CPU_rd_apply_reg    <=0;
 
assign CPU_rd_grant =!CPU_rd_apply_reg;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        CPU_rd_dout     <=0;
    else if (Pipeline&&CurrentState==StateCPU)
        CPU_rd_dout     <=Douta;
 
endmodule

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// RMON_CTRL.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9	7	maverickis	`//// - Jon Gao (gaojon@yahoo.com) ////`
10	5	maverickis	`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41	6	maverickis	`// $Log: not supported by cvs2svn $`
42	7	maverickis	`// Revision 1.2 2005/12/16 06:44:19 Administrator`
43			`// replaced tab with space.`
44			`// passed 9.6k length frame test.`
45			`//`
46	6	maverickis	`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
47			`// no message`
48			`//`
49	5	maverickis	`module RMON_CTRL (`
50	7	maverickis	`Clk ,`
51			`Reset ,`
52	5	maverickis	`//RMON_CTRL`
53	7	maverickis	`Reg_apply_0 ,`
54			`Reg_addr_0 ,`
55			`Reg_data_0 ,`
56			`Reg_next_0 ,`
57			`Reg_apply_1 ,`
58			`Reg_addr_1 ,`
59			`Reg_data_1 ,`
60			`Reg_next_1 ,`
61	5	maverickis	`//dual-port ram`
62	7	maverickis	`Addra ,`
63			`Dina ,`
64			`Douta ,`
65			`Wea ,`
66	5	maverickis	`//CPU`
67	7	maverickis	`CPU_rd_addr ,`
68			`CPU_rd_apply ,`
69			`CPU_rd_grant ,`
70	5	maverickis	`CPU_rd_dout`
71
72			`);`
73	7	maverickis	`input Clk ;`
74			`input Reset ;`
75			`//RMON_CTRL`
76			`input Reg_apply_0 ;`
77			`input [4:0] Reg_addr_0 ;`
78			`input [15:0] Reg_data_0 ;`
79			`output Reg_next_0 ;`
80			`input Reg_apply_1 ;`
81			`input [4:0] Reg_addr_1 ;`
82			`input [15:0] Reg_data_1 ;`
83			`output Reg_next_1 ;`
84			`//dual-port ram`
85			`//port-a for Rmon`
86			`output [5:0] Addra ;`
87			`output [31:0] Dina ;`
88			`input [31:0] Douta ;`
89			`output Wea ;`
90			`//CPU`
91			`input [5:0] CPU_rd_addr ;`
92			`input CPU_rd_apply ;`
93			`output CPU_rd_grant ;`
94			`output [31:0] CPU_rd_dout ;`
95	5	maverickis
96
97
98
99			`//******************************************************************************`
100			`//internal signals`
101			`//******************************************************************************`
102
103	7	maverickis	`parameter StateCPU =5'd00;`
104			`parameter StateMAC0 =5'd01;`
105			`parameter StateMAC1 =5'd02;`
106	5	maverickis
107
108	7	maverickis	`reg [4:0] CurrentState;`
109			`reg [4:0] NextState;`
110			`reg [4:0] CurrentState_reg;`
111	5	maverickis
112	7	maverickis	`reg [4:0] StepCounter;`
113			`reg [31:0] DoutaReg;`
114			`reg [5:0] Addra ;`
115			`reg [31:0] Dina;`
116			`reg Reg_next_0 ;`
117			`reg Reg_next_1 ;`
118			`reg Write;`
119			`reg Read;`
120			`reg Pipeline;`
121			`reg [31:0] CPU_rd_dout ;`
122			`reg CPU_rd_apply_reg ;`
123	5	maverickis	`//******************************************************************************`
124			`//State Machine`
125			`//******************************************************************************`
126
127			`always @(posedge Clk or posedge Reset)`
128	7	maverickis	`if (Reset)`
129			`CurrentState <=StateMAC0;`
130			`else`
131			`CurrentState <=NextState;`
132
133	5	maverickis	`always @(posedge Clk or posedge Reset)`
134	7	maverickis	`if (Reset)`
135			`CurrentState_reg <=StateMAC0;`
136			`else if(CurrentState!=StateCPU)`
137			`CurrentState_reg <=CurrentState;`
138
139	5	maverickis	`always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg`
140	7	maverickis	`or Reg_apply_1`
141			`or StepCounter`
142			`)`
143			`case(CurrentState)`
144			`StateMAC0:`
145			`if(!Reg_apply_0&&CPU_rd_apply_reg)`
146			`NextState =StateCPU;`
147			`else if(!Reg_apply_0)`
148			`NextState =StateMAC1;`
149			`else`
150			`NextState =CurrentState;`
151			`StateMAC1:`
152			`if(!Reg_apply_1&&CPU_rd_apply_reg)`
153			`NextState =StateCPU;`
154			`else if(!Reg_apply_1)`
155			`NextState =StateMAC0;`
156			`else`
157			`NextState =CurrentState;`
158			`StateCPU:`
159			`if (StepCounter==3)`
160			`case (CurrentState_reg)`
161			`StateMAC0 :NextState =StateMAC0 ;`
162			`StateMAC1 :NextState =StateMAC1 ;`
163			`default :NextState =StateMAC0;`
164			`endcase`
165			`else`
166			`NextState =CurrentState;`
167
168			`default:`
169			`NextState =StateMAC0;`
170			`endcase`
171
172	5	maverickis
173
174			`always @(posedge Clk or posedge Reset)`
175	7	maverickis	`if (Reset)`
176			`StepCounter <=0;`
177			`else if(NextState!=CurrentState)`
178			`StepCounter <=0;`
179			`else if (StepCounter!=4'hf)`
180			`StepCounter <=StepCounter + 1;`
181	5	maverickis
182			`//******************************************************************************`
183			`//temp signals`
184			`//******************************************************************************`
185			`always @(StepCounter)`
186	7	maverickis	`if( StepCounter==1\|\|StepCounter==4\|\|`
187			`StepCounter==7\|\|StepCounter==10)`
188			`Read =1;`
189			`else`
190			`Read =0;`
191	5	maverickis
192			`always @(StepCounter or CurrentState)`
193	7	maverickis	`if( StepCounter==2\|\|StepCounter==5\|\|`
194			`StepCounter==8\|\|StepCounter==11)`
195			`Pipeline =1;`
196			`else`
197			`Pipeline =0;`
198
199	5	maverickis	`always @(StepCounter or CurrentState)`
200	7	maverickis	`if( StepCounter==3\|\|StepCounter==6\|\|`
201			`StepCounter==9\|\|StepCounter==12)`
202			`Write =1;`
203			`else`
204			`Write =0;`
205
206	5	maverickis	`always @(posedge Clk or posedge Reset)`
207	7	maverickis	`if (Reset)`
208			`DoutaReg <=0;`
209			`else if (Read)`
210			`DoutaReg <=Douta;`
211
212
213	5	maverickis	`//******************************************************************************`
214			`//gen output signals`
215	7	maverickis	`//******************************************************************************`
216			`//Addra`
217	5	maverickis	`always @(*)`
218	7	maverickis	`case(CurrentState)`
219			`StateMAC0 : Addra={1'd0 ,Reg_addr_0 };`
220			`StateMAC1 : Addra={1'd1 ,Reg_addr_1 };`
221			`StateCPU: Addra=CPU_rd_addr;`
222			`default: Addra=0;`
223			`endcase`
224
225	5	maverickis	`//Dina`
226			`always @(posedge Clk or posedge Reset)`
227	7	maverickis	`if (Reset)`
228			`Dina <=0;`
229			`else`
230			`case(CurrentState)`
231			`StateMAC0 : Dina<=Douta+Reg_data_0 ;`
232			`StateMAC1 : Dina<=Douta+Reg_data_1 ;`
233			`StateCPU: Dina<=0;`
234			`default: Dina<=0;`
235			`endcase`
236
237			`assign Wea =Write;`
238	5	maverickis	`//Reg_next`
239			`always @(CurrentState or Pipeline)`
240	7	maverickis	`if(CurrentState==StateMAC0)`
241			`Reg_next_0 =Pipeline;`
242			`else`
243			`Reg_next_0 =0;`
244
245	5	maverickis	`always @(CurrentState or Pipeline)`
246	7	maverickis	`if(CurrentState==StateMAC1)`
247			`Reg_next_1 =Pipeline;`
248			`else`
249			`Reg_next_1 =0;`
250	5	maverickis
251
252			`//CPU_rd_grant`
253	7	maverickis	`reg CPU_rd_apply_dl1;`
254			`reg CPU_rd_apply_dl2;`
255	5	maverickis	`//rising edge`
256			`always @ (posedge Clk or posedge Reset)`
257	7	maverickis	`if (Reset)`
258			`begin`
259			`CPU_rd_apply_dl1 <=0;`
260	5	maverickis	`CPU_rd_apply_dl2 <=0;`
261	7	maverickis	`end`
262			`else`
263			`begin`
264			`CPU_rd_apply_dl1 <=CPU_rd_apply;`
265	5	maverickis	`CPU_rd_apply_dl2 <=CPU_rd_apply_dl1;`
266	7	maverickis	`end`
267	5	maverickis
268			`always @ (posedge Clk or posedge Reset)`
269	7	maverickis	`if (Reset)`
270			`CPU_rd_apply_reg <=0;`
271			`else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)`
272			`CPU_rd_apply_reg <=1;`
273			`else if (CurrentState==StateCPU&&Write)`
274			`CPU_rd_apply_reg <=0;`
275	5	maverickis
276	7	maverickis	`assign CPU_rd_grant =!CPU_rd_apply_reg;`
277	5	maverickis
278			`always @ (posedge Clk or posedge Reset)`
279	7	maverickis	`if (Reset)`
280			`CPU_rd_dout <=0;`
281			`else if (Pipeline&&CurrentState==StateCPU)`
282			`CPU_rd_dout <=Douta;`
283	5	maverickis
284	7	maverickis	`endmodule`

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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [RMON/] [RMON_ctrl.v] - Blame information for rev 7