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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [TECH/] [altera/] [duram.v] - Blame information for rev 33

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Line No. Rev Author Line
1 22 maverickis 
module duram(
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data_a,
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data_b,
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wren_a,
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wren_b,
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address_a,
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address_b,
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clock_a,
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clock_b,
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q_a,
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q_b);   //synthesis syn_black_box
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parameter DATA_WIDTH    = 32;
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parameter ADDR_WIDTH    = 5;
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parameter BLK_RAM_TYPE  = "AUTO";
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parameter DURAM_MODE    = "BIDIR_DUAL_PORT";
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parameter ADDR_DEPTH    = 2**ADDR_WIDTH;
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input   [DATA_WIDTH -1:0]   data_a;
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input                       wren_a;
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input   [ADDR_WIDTH -1:0]   address_a;
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input                       clock_a;
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output  [DATA_WIDTH -1:0]   q_a;
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input   [DATA_WIDTH -1:0]   data_b;
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input                       wren_b;
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input   [ADDR_WIDTH -1:0]   address_b;
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input                       clock_b;
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output  [DATA_WIDTH -1:0]   q_b;
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altsyncram U_altsyncram (
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.wren_a         (wren_a),
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.wren_b         (wren_b),
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.data_a         (data_a),
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.data_b         (data_b),
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.address_a      (address_a),
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.address_b      (address_b),
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.clock0         (clock_a),
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.clock1         (clock_b),
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.q_a            (q_a),
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.q_b            (q_b),
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// synopsys translate_off
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.aclr0 (),
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.aclr1 (),
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.addressstall_a (),
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.addressstall_b (),
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.byteena_a (),
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.byteena_b (),
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.clocken0 (),
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.clocken1 (),
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.rden_b ()
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// synopsys translate_on
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);
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    defparam
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        U_altsyncram.intended_device_family = "Stratix",
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        U_altsyncram.ram_block_type = BLK_RAM_TYPE,
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        U_altsyncram.operation_mode = DURAM_MODE,
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        U_altsyncram.width_a = DATA_WIDTH,
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        U_altsyncram.widthad_a = ADDR_WIDTH,
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//      U_altsyncram.numwords_a = 256,
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        U_altsyncram.width_b = DATA_WIDTH,
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        U_altsyncram.widthad_b = ADDR_WIDTH,
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//      U_altsyncram.numwords_b = 256,
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        U_altsyncram.lpm_type = "altsyncram",
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        U_altsyncram.width_byteena_a = 1,
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        U_altsyncram.width_byteena_b = 1,
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        U_altsyncram.outdata_reg_a = "UNREGISTERED",
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        U_altsyncram.outdata_aclr_a = "NONE",
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        U_altsyncram.outdata_reg_b = "UNREGISTERED",
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        U_altsyncram.indata_aclr_a = "NONE",
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        U_altsyncram.wrcontrol_aclr_a = "NONE",
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        U_altsyncram.address_aclr_a = "NONE",
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        U_altsyncram.indata_reg_b = "CLOCK1",
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        U_altsyncram.address_reg_b = "CLOCK1",
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        U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1",
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        U_altsyncram.indata_aclr_b = "NONE",
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        U_altsyncram.wrcontrol_aclr_b = "NONE",
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        U_altsyncram.address_aclr_b = "NONE",
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        U_altsyncram.outdata_aclr_b = "NONE",
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        U_altsyncram.power_up_uninitialized = "FALSE";
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endmodule
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