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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [TECH/] [xilinx/] [CLK_SWITCH.v] - Blame information for rev 33

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1 22 maverickis
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  CLK_SWITCH.v                                                  ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Jon Gao (gaojon@yahoo.com)                            ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//                                                                    
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// CVS Revision History                                               
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//                                                                    
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// $Log: not supported by cvs2svn $
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// Revision 1.1  2006/06/22 09:01:42  Administrator
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// no message
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//
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// Revision 1.2  2005/12/16 06:44:20  Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
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// no message
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// 
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//////////////////////////////////////////////////////////////////////
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// This file can only used for simulation .
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// You need to replace it with your own element according to technology
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//////////////////////////////////////////////////////////////////////
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module CLK_SWITCH (
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input       IN_0,
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input       IN_1,
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input       SW  ,
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output      OUT
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);
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BUFGMUX U_BUFGMUX (
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.O          (OUT        ),
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.I0         (IN_0       ),
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.I1         (IN_1       ),
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.S          (SW         ));
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//assign OUT=SW?IN_1:IN_0;
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endmodule

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