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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [miim/] [eth_outputcontrol.v] - Blame information for rev 33

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_outputcontrol.v                                         ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//
// Revision 1.2  2005/04/27 15:58:46  Administrator
// no message
//
// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator
// no message
//
// Revision 1.4  2002/07/09 20:11:59  mohor
// Comment removed.
//
// Revision 1.3  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.2  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3  2001/06/01 22:28:56  mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
 
`timescale 1ns/10ps
 
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
 
parameter Tp = 1;
 
input         Clk;                // Host Clock
input         Reset;              // General Reset
input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
input         NoPre;              // No Preamble (no 32-bit preamble)
input         InProgress;         // Operation in progress
input         ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
input   [6:0] BitCounter;         // Bit Counter
input         MdcEn_n;            // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
 
output        Mdo;                // MII Management Data Output
output        MdoEn;              // MII Management Data Output Enable
 
wire          SerialEn;
 
reg           MdoEn_2d;
reg           MdoEn_d;
reg           MdoEn;
 
reg           Mdo_2d;
reg           Mdo_d;
reg           Mdo;                // MII Management Data Output
 
 
 
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn =  WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
                | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
 
 
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      MdoEn_2d <= #Tp 1'b0;
      MdoEn_d <= #Tp 1'b0;
      MdoEn <= #Tp 1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin
          MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
          MdoEn_d <= #Tp MdoEn_2d;
          MdoEn <= #Tp MdoEn_d;
        end
    end
end
 
 
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      Mdo_2d <= #Tp 1'b0;
      Mdo_d <= #Tp 1'b0;
      Mdo <= #Tp 1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin
          Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
          Mdo_d <= #Tp ShiftedBit | Mdo_2d;
          Mdo <= #Tp Mdo_d;
        end
    end
end
 
 
 
endmodule

Line No.	Rev	Author	Line
1	5	maverickis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_outputcontrol.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	6	maverickis	`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
45			`// no message`
46			`//`
47	5	maverickis	`// Revision 1.2 2005/04/27 15:58:46 Administrator`
48			`// no message`
49			`//`
50			`// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator`
51			`// no message`
52			`//`
53			`// Revision 1.4 2002/07/09 20:11:59 mohor`
54			`// Comment removed.`
55			`//`
56			`// Revision 1.3 2002/01/23 10:28:16 mohor`
57			`// Link in the header changed.`
58			`//`
59			`// Revision 1.2 2001/10/19 08:43:51 mohor`
60			`// eth_timescale.v changed to timescale.v This is done because of the`
61			`// simulation of the few cores in a one joined project.`
62			`//`
63			`// Revision 1.1 2001/08/06 14:44:29 mohor`
64			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
65			`// Include files fixed to contain no path.`
66			`// File names and module names changed ta have a eth_ prologue in the name.`
67			`// File eth_timescale.v is used to define timescale`
68			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
69			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
70			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
71			`// is done due to the ASIC tools.`
72			`//`
73			`// Revision 1.1 2001/07/30 21:23:42 mohor`
74			`// Directory structure changed. Files checked and joind together.`
75			`//`
76			`// Revision 1.3 2001/06/01 22:28:56 mohor`
77			`// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.`
78			`//`
79			`//`
80
81			`timescale 1ns/10ps
82
83			`module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);`
84
85			`parameter Tp = 1;`
86
87			`input Clk; // Host Clock`
88			`input Reset; // General Reset`
89			`input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)`
90			`input NoPre; // No Preamble (no 32-bit preamble)`
91			`input InProgress; // Operation in progress`
92			`input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal`
93			`input [6:0] BitCounter; // Bit Counter`
94			`input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.`
95
96			`output Mdo; // MII Management Data Output`
97			`output MdoEn; // MII Management Data Output Enable`
98
99			`wire SerialEn;`
100
101			`reg MdoEn_2d;`
102			`reg MdoEn_d;`
103			`reg MdoEn;`
104
105			`reg Mdo_2d;`
106			`reg Mdo_d;`
107			`reg Mdo; // MII Management Data Output`
108
109
110
111			`// Generation of the Serial Enable signal (enables the serialization of the data)`
112			`assign SerialEn = WriteOp & InProgress & ( BitCounter>31 \| ( ( BitCounter == 0 ) & NoPre ) )`
113			`\| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) \| ( ( BitCounter == 0 ) & NoPre ));`
114
115
116			`// Generation of the MdoEn signal`
117			`always @ (posedge Clk or posedge Reset)`
118			`begin`
119			`if(Reset)`
120			`begin`
121			`MdoEn_2d <= #Tp 1'b0;`
122			`MdoEn_d <= #Tp 1'b0;`
123			`MdoEn <= #Tp 1'b0;`
124			`end`
125			`else`
126			`begin`
127			`if(MdcEn_n)`
128			`begin`
129			`MdoEn_2d <= #Tp SerialEn \| InProgress & BitCounter<32;`
130			`MdoEn_d <= #Tp MdoEn_2d;`
131			`MdoEn <= #Tp MdoEn_d;`
132			`end`
133			`end`
134			`end`
135
136
137			`// Generation of the Mdo signal.`
138			`always @ (posedge Clk or posedge Reset)`
139			`begin`
140			`if(Reset)`
141			`begin`
142			`Mdo_2d <= #Tp 1'b0;`
143			`Mdo_d <= #Tp 1'b0;`
144			`Mdo <= #Tp 1'b0;`
145			`end`
146			`else`
147			`begin`
148			`if(MdcEn_n)`
149			`begin`
150			`Mdo_2d <= #Tp ~SerialEn & BitCounter<32;`
151			`Mdo_d <= #Tp ShiftedBit \| Mdo_2d;`
152			`Mdo <= #Tp Mdo_d;`
153			`end`
154			`end`
155			`end`
156
157
158
159			`endmodule`

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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [miim/] [eth_outputcontrol.v] - Blame information for rev 33