OpenCores
URL https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk

Subversion Repositories ethernet_tri_mode

[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [miim/] [eth_shiftreg.v] - Blame information for rev 33

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 maverickis
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_shiftreg.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 6 maverickis
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
45
// no message
46
//
47 5 maverickis
// Revision 1.2  2005/04/27 15:58:47  Administrator
48
// no message
49
//
50
// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator
51
// no message
52
//
53
// Revision 1.5  2002/08/14 18:16:59  mohor
54
// LinkFail signal was not latching appropriate bit.
55
//
56
// Revision 1.4  2002/03/02 21:06:01  mohor
57
// LinkFail signal was not latching appropriate bit.
58
//
59
// Revision 1.3  2002/01/23 10:28:16  mohor
60
// Link in the header changed.
61
//
62
// Revision 1.2  2001/10/19 08:43:51  mohor
63
// eth_timescale.v changed to timescale.v This is done because of the
64
// simulation of the few cores in a one joined project.
65
//
66
// Revision 1.1  2001/08/06 14:44:29  mohor
67
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
68
// Include files fixed to contain no path.
69
// File names and module names changed ta have a eth_ prologue in the name.
70
// File eth_timescale.v is used to define timescale
71
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
72
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
73
// and Mdo_OE. The bidirectional signal must be created on the top level. This
74
// is done due to the ASIC tools.
75
//
76
// Revision 1.1  2001/07/30 21:23:42  mohor
77
// Directory structure changed. Files checked and joind together.
78
//
79
// Revision 1.3  2001/06/01 22:28:56  mohor
80
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
81
//
82
//
83
 
84
`timescale 1ns/10ps
85
 
86
 
87
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
88
                    LatchByte, ShiftedBit, Prsd, LinkFail);
89
 
90
 
91
parameter Tp=1;
92
 
93
input       Clk;              // Input clock (Host clock)
94
input       Reset;            // Reset signal
95
input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
96
input       Mdi;              // MII input data
97
input [4:0] Fiad;             // PHY address
98
input [4:0] Rgad;             // Register address (within the selected PHY)
99
input [15:0]CtrlData;         // Control data (data to be written to the PHY)
100
input       WriteOp;          // The current operation is a PHY register write operation
101
input [3:0] ByteSelect;       // Byte select
102
input [1:0] LatchByte;        // Byte select for latching (read operation)
103
 
104
output      ShiftedBit;       // Bit shifted out of the shift register
105
output[15:0]Prsd;             // Read Status Data (data read from the PHY)
106
output      LinkFail;         // Link Integrity Signal
107
 
108
reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out
109
reg   [15:0]Prsd;
110
reg         LinkFail;
111
 
112
 
113
 
114
 
115
// ShiftReg[7:0] :: Shift Register Data
116
always @ (posedge Clk or posedge Reset)
117
begin
118
  if(Reset)
119
    begin
120
      ShiftReg[7:0] <= #Tp 8'h0;
121
      Prsd[15:0] <= #Tp 16'h0;
122
      LinkFail <= #Tp 1'b0;
123
    end
124
  else
125
    begin
126
      if(MdcEn_n)
127
        begin
128
          if(|ByteSelect)
129
            begin
130
              case (ByteSelect[3:0])
131
                4'h1 :    ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
132
                4'h2 :    ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
133
                4'h4 :    ShiftReg[7:0] <= #Tp CtrlData[15:8];
134
                4'h8 :    ShiftReg[7:0] <= #Tp CtrlData[7:0];
135
                default : ShiftReg[7:0] <= #Tp 8'h0;
136
              endcase
137
            end
138
          else
139
            begin
140
              ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
141
              if(LatchByte[0])
142
                begin
143
                  Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
144
                  if(Rgad == 5'h01)
145
                    LinkFail <= #Tp ~ShiftReg[1];  // this is bit [2], because it is not shifted yet
146
                end
147
              else
148
                begin
149
                  if(LatchByte[1])
150
                    Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
151
                end
152
            end
153
        end
154
    end
155
end
156
 
157
 
158
assign ShiftedBit = ShiftReg[7];
159
 
160
 
161
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.