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[/] [ethernet_tri_mode/] [trunk/] [start.tcl] - Blame information for rev 33

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Line No. Rev Author Line
1 7 maverickis 
variable MAC_SOURCE_REPLACE_EN
2 
variable MAC_TARGET_CHECK_EN
3 
variable MAC_BROADCAST_FILTER_EN
4 
variable MAC_TX_FF_DEPTH
5 
variable MAC_RX_FF_DEPTH
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variable header_data
7 
 
8 
source sim/rtl_sim/ncsim_sim/script/run_proc.tcl
9 
 
10 
frame .f1
11 
frame .f2
12 16 maverickis 
text .f1.t1 -width 60 -height 20
13 
button .f2.b1 -text "Quit" -width 5 -command {exit}
14 
button .f2.b2 -text "Next" -width 5 -command {module_conf}
15 7 maverickis 
 
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pack .f1 .f2
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pack .f1.t1
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pack .f2.b1 .f2.b2 -side left
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set strings \
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{Hi guys,
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    Thanks for your interest about this tri-speed ethernet MAC controller.
23 17 maverickis 
Since this project was created at 25-Nov-2005,I put almost all my free time
24 7 maverickis 
on this project.I am exhausted for this two month's extra work.If you think
25 
this project is useful,let me know that and i will feel much better.
26 
 
27 
    To increase the flexibility, some optional modules can be removed from
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the design to reduce area.
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30 
    Any problem or bug report please contact me by email:
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    gaojon@yahoo.com
32 
 
33 
 
34 
 
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37 
 
38 
                                                                jon
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                                                                18-Jan-2006
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}
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.f1.t1 insert end $strings
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proc module_conf {} {
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    global MAC_SOURCE_REPLACE_EN
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    global MAC_TARGET_CHECK_EN
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    global MAC_BROADCAST_FILTER_EN
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    global MAC_TX_FF_DEPTH
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    global MAC_RX_FF_DEPTH
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    global header_data
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52 
    if {[catch {open ./rtl/verilog/header.v r} fileid]} {
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        puts "Failed open ./rtl/verilog/header.v file\n"
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    } else {
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        gets $fileid line
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        if {[lindex $line 0]=="//"} {
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            set line [lreplace $line 0 0]
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            set MAC_SOURCE_REPLACE_EN 0
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        } else {
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            set MAC_SOURCE_REPLACE_EN 1
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        }
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        lappend header_data $line
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        gets $fileid line
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        if {[lindex $line 0]=="//"} {
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            set line [lreplace $line 0 0]
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            set MAC_TARGET_CHECK_EN 0
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        } else {
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            set MAC_TARGET_CHECK_EN 1
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        }
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        lappend header_data $line
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        gets $fileid line
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        if {[lindex $line 0]=="//"} {
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            set line [lreplace $line 0 0]
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            set MAC_BROADCAST_FILTER_EN 0
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        } else {
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            set MAC_BROADCAST_FILTER_EN 1
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        }
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        lappend header_data $line
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        gets $fileid line
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        set MAC_TX_FF_DEPTH [lindex $line 2]
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        lappend header_data $line
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        gets $fileid line
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        set MAC_RX_FF_DEPTH [lindex $line 2]
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        lappend header_data $line
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        close $fileid
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     }
87 
 
88 
    destroy .f1 .f2
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    frame .f1
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    frame .f2
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    frame .f1.f1
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    frame .f1.f2
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    frame .f1.f3
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    frame .f1.f4
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    frame .f1.f5
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    frame .f1.f6
97 
 
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    pack .f1 .f2
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    pack .f1.f1 .f1.f2 .f1.f3 .f1.f4 .f1.f5 .f1.f6
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    label       .f1.f1.lb -text "enable source MAC replace module" -width 30
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    checkbutton .f1.f1.cb -variable MAC_SOURCE_REPLACE_EN
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    label       .f1.f2.lb -text "enable target MAC check module " -width 30
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    checkbutton .f1.f2.cb -variable MAC_TARGET_CHECK_EN
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    label       .f1.f3.lb -text "enable broadcast packet filter module" -width 30
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    checkbutton .f1.f3.cb -variable MAC_BROADCAST_FILTER_EN
106 
 
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    label       .f1.f4.lb -text "MAC_TX_FF_DEPTH" -width 30
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    entry       .f1.f4.en -textvariable MAC_TX_FF_DEPTH -width 5
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    label       .f1.f5.lb -text "MAC_RX_FF_DEPTH" -width 30
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    entry       .f1.f5.en -textvariable MAC_RX_FF_DEPTH -width 5
111 
 
112 16 maverickis 
    button .f2.b1 -width 10 -text "Save"            -command {save_header}
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    button .f2.b2 -width 10 -text "Verify"          -command {run_sim}
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    button .f2.b4 -width 10 -text "Exit"            -command {exit}
115 7 maverickis 
 
116 
    pack .f1.f1.cb .f1.f1.lb -side right
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    pack .f1.f2.cb .f1.f2.lb -side right
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    pack .f1.f3.cb .f1.f3.lb -side right
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    pack .f1.f4.en .f1.f4.lb -side right
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    pack .f1.f5.en .f1.f5.lb -side right
121 
 
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    pack .f2.b1 .f2.b2 .f2.b4 -side left
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124 
}
125 
 
126 
proc save_header {} {
127 
    global MAC_SOURCE_REPLACE_EN
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    global MAC_TARGET_CHECK_EN
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    global MAC_BROADCAST_FILTER_EN
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    global MAC_TX_FF_DEPTH
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    global MAC_RX_FF_DEPTH
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    global header_data
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    if {[catch {open ./rtl/verilog/header.v w} fileid]} {
134 
        puts "Failed open ./rtl/verilog/header.v file\n"
135 
    } else {
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        set line [lindex $header_data 0]
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        if {$MAC_SOURCE_REPLACE_EN==0} {
138 
            set line [linsert $line 0 "//"]
139 
        }
140 
        puts $fileid $line
141 
 
142 
        set line [lindex $header_data 1]
143 
        if {$MAC_TARGET_CHECK_EN==0} {
144 
            set line [linsert $line 0 "//"]
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        }
146 
        puts $fileid $line
147 
 
148 
        set line [lindex $header_data 2]
149 
        if {$MAC_BROADCAST_FILTER_EN==0} {
150 
            set line [linsert $line 0 "//"]
151 
        }
152 
        puts $fileid $line
153 
 
154 
        set line [lindex $header_data 3]
155 
        set line [lreplace $line 2 2 $MAC_TX_FF_DEPTH]
156 
        puts $fileid $line
157 
 
158 
        set line [lindex $header_data 4]
159 
        set line [lreplace $line 2 2 $MAC_RX_FF_DEPTH]
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        puts $fileid $line
161 
 
162 
        close $fileid
163 
     }
164 
 
165 
}
166 
 
167 
proc start_verify {} {
168 24 maverickis 
    cd sim/rtl_sim/modsim_sim/script
169 7 maverickis 
    vish run.tcl
170 
}
171 
 
172 
proc start_syn {} {
173 
    cd syn
174 
    synplify_pro syn.prj
175 
}
176 
 
177 
proc run_sim {} {
178 24 maverickis 
    cd sim/rtl_sim/modsim_sim/script/
179 7 maverickis 
    run_proc
180 
}

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