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mohor |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// eth_memory.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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`include "tb_eth_defines.v"
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`include "timescale.v"
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module eth_memory
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(
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wb_clk_i, wb_rst_i, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_stb_i, wb_ack_o, wb_err_o, wb_dat_o, wb_dat_i
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);
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parameter Tp=1;
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input wb_clk_i, wb_rst_i;
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input [31:0] wb_adr_i, wb_dat_i;
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input [3:0] wb_sel_i;
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input wb_we_i, wb_cyc_i, wb_stb_i;
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output wb_ack_o, wb_err_o;
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output [31:0] wb_dat_o;
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reg wb_ack_o, wb_err_o;
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reg [31:0] wb_dat_o;
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reg [7:0] memory0 [0:65535];
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reg [7:0] memory1 [0:65535];
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reg [7:0] memory2 [0:65535];
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reg [7:0] memory3 [0:65535];
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integer memory_log;
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// Reset pulse
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initial
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begin
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memory_log = $fopen("eth_memory.log");
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wb_ack_o = 0;
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wb_err_o = 0;
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end
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always @ (posedge wb_clk_i)
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begin
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if(wb_cyc_i & wb_stb_i)
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begin
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repeat(1) @ (posedge wb_clk_i); // Waiting 3 clock cycles before ack is set
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begin // (you can add some random function here)
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#1;
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wb_ack_o = 1'b1;
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if(~wb_we_i)
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begin
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if(wb_adr_i[1:0] == 2'b00) // word access
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begin
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wb_dat_o[31:24] = memory3[wb_adr_i[17:2]];
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wb_dat_o[23:16] = memory2[wb_adr_i[17:2]];
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wb_dat_o[15:08] = memory1[wb_adr_i[17:2]];
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wb_dat_o[07:00] = memory0[wb_adr_i[17:2]];
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end
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else if(wb_adr_i[1:0] == 2'b10) // half access
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begin
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wb_dat_o[31:24] = 0;
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wb_dat_o[23:16] = 0;
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wb_dat_o[15:08] = memory1[wb_adr_i[17:2]];
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wb_dat_o[07:00] = memory0[wb_adr_i[17:2]];
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end
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else if(wb_adr_i[1:0] == 2'b01) // byte access
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begin
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wb_dat_o[31:24] = 0;
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wb_dat_o[23:16] = memory2[wb_adr_i[17:2]];
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wb_dat_o[15:08] = 0;
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wb_dat_o[07:00] = 0;
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end
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else if(wb_adr_i[1:0] == 2'b11) // byte access
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begin
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wb_dat_o[31:24] = 0;
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wb_dat_o[23:16] = 0;
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wb_dat_o[15:08] = 0;
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wb_dat_o[07:00] = memory0[wb_adr_i[17:2]];
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end
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$fdisplay(memory_log, "(%0t)(%m)wb_read (0x%0x) = 0x%0x", $time, wb_adr_i, wb_dat_o);
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end
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else
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begin
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$fdisplay(memory_log, "(%0t)(%m)wb_write (0x%0x) = 0x%0x", $time, wb_adr_i, wb_dat_i);
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if(wb_sel_i[0])
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memory0[wb_adr_i[17:2]] = wb_dat_i[7:0];
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if(wb_sel_i[1])
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memory1[wb_adr_i[17:2]] = wb_dat_i[15:8];
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if(wb_sel_i[2])
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memory2[wb_adr_i[17:2]] = wb_dat_i[23:16];
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if(wb_sel_i[3])
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memory3[wb_adr_i[17:2]] = wb_dat_i[31:24];
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end
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end
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@ (posedge wb_clk_i);
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wb_ack_o <=#Tp 1'b0;
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end
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end
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endmodule
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