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1 116 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  tb_ethernet.v                                               ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9 169 mohor
////      - Tadej Markovic, tadej@opencores.org                   ////
10 243 tadejm
////      - Igor Mohor,     igorM@opencores.org                  ////
11 116 mohor
////                                                              ////
12 169 mohor
////  All additional information is available in the Readme.txt   ////
13 116 mohor
////  file.                                                       ////
14
////                                                              ////
15
//////////////////////////////////////////////////////////////////////
16
////                                                              ////
17
//// Copyright (C) 2001, 2002 Authors                             ////
18
////                                                              ////
19
//// This source file may be used and distributed without         ////
20
//// restriction provided that this copyright statement is not    ////
21
//// removed from the file and that any derivative work contains  ////
22
//// the original copyright notice and the associated disclaimer. ////
23
////                                                              ////
24
//// This source file is free software; you can redistribute it   ////
25
//// and/or modify it under the terms of the GNU Lesser General   ////
26
//// Public License as published by the Free Software Foundation; ////
27
//// either version 2.1 of the License, or (at your option) any   ////
28
//// later version.                                               ////
29
////                                                              ////
30
//// This source is distributed in the hope that it will be       ////
31
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
32
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
33
//// PURPOSE.  See the GNU Lesser General Public License for more ////
34
//// details.                                                     ////
35
////                                                              ////
36
//// You should have received a copy of the GNU Lesser General    ////
37
//// Public License along with this source; if not, download it   ////
38
//// from http://www.opencores.org/lgpl.shtml                     ////
39
////                                                              ////
40
//////////////////////////////////////////////////////////////////////
41
//
42
// CVS Revision History
43
//
44
// $Log: not supported by cvs2svn $
45 263 mohor
// Revision 1.22  2002/11/21 13:56:50  mohor
46
// test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
47
// finished.
48
//
49 260 mohor
// Revision 1.21  2002/11/19 20:27:45  mohor
50
// Temp version.
51
//
52 254 mohor
// Revision 1.20  2002/11/19 17:41:19  tadejm
53
// Just some updates.
54
//
55 252 tadejm
// Revision 1.19  2002/11/14 13:12:47  tadejm
56
// Late collision is not reported any more.
57
//
58 243 tadejm
// Revision 1.18  2002/10/18 17:03:34  tadejm
59
// Changed BIST scan signals.
60
//
61 227 tadejm
// Revision 1.17  2002/10/18 13:58:22  tadejm
62
// Some code changed due to bug fixes.
63
//
64 223 tadejm
// Revision 1.16  2002/10/09 13:16:51  tadejm
65
// Just back-up; not completed testbench and some testcases are not
66
// wotking properly yet.
67
//
68 209 tadejm
// Revision 1.15  2002/09/20 14:29:12  tadej
69
// Full duplex tests modified and testbench bug repaired.
70
//
71 194 tadej
// Revision 1.14  2002/09/18 17:56:38  tadej
72
// Some additional reports added
73
//
74 192 tadej
// Revision 1.13  2002/09/16 17:53:49  tadej
75
// Full duplex test improved.
76
//
77 182 tadej
// Revision 1.12  2002/09/16 15:10:42  mohor
78
// MIIM test look better.
79
//
80 181 mohor
// Revision 1.11  2002/09/13 19:18:04  mohor
81
// Bench outputs data to display every 128 bytes.
82
//
83 180 mohor
// Revision 1.10  2002/09/13 18:44:29  mohor
84
// Beautiful tests merget together
85
//
86 179 mohor
// Revision 1.9  2002/09/13 18:41:45  mohor
87
// Rearanged testcases
88
//
89 178 mohor
// Revision 1.8  2002/09/13 14:50:15  mohor
90
// Bug in MIIM fixed.
91
//
92 177 mohor
// Revision 1.7  2002/09/13 12:29:14  mohor
93
// Headers changed.
94
//
95 170 mohor
// Revision 1.6  2002/09/13 11:57:20  mohor
96
// New testbench. Thanks to Tadej M - "The Spammer".
97
//
98 121 mohor
// Revision 1.2  2002/07/19 14:02:47  mohor
99
// Clock mrx_clk set to 2.5 MHz.
100
//
101 117 mohor
// Revision 1.1  2002/07/19 13:57:53  mohor
102
// Testing environment also includes traffic cop, memory interface and host
103
// interface.
104 116 mohor
//
105
//
106
//
107
//
108 117 mohor
//
109 116 mohor
 
110
 
111 169 mohor
`include "eth_phy_defines.v"
112
`include "wb_model_defines.v"
113 116 mohor
`include "tb_eth_defines.v"
114
`include "eth_defines.v"
115
`include "timescale.v"
116
 
117
module tb_ethernet();
118
 
119
 
120 169 mohor
reg           wb_clk;
121
reg           wb_rst;
122
wire          wb_int;
123 116 mohor
 
124 169 mohor
wire          mtx_clk;  // This goes to PHY
125
wire          mrx_clk;  // This goes to PHY
126 116 mohor
 
127
wire   [3:0]  MTxD;
128
wire          MTxEn;
129
wire          MTxErr;
130
 
131 169 mohor
wire   [3:0]  MRxD;     // This goes to PHY
132
wire          MRxDV;    // This goes to PHY
133
wire          MRxErr;   // This goes to PHY
134
wire          MColl;    // This goes to PHY
135
wire          MCrs;     // This goes to PHY
136 116 mohor
 
137
wire          Mdi_I;
138
wire          Mdo_O;
139
wire          Mdo_OE;
140 169 mohor
tri           Mdio_IO;
141 116 mohor
wire          Mdc_O;
142
 
143
 
144 169 mohor
parameter Tp = 1;
145 116 mohor
 
146 121 mohor
 
147 116 mohor
// Ethernet Slave Interface signals
148 169 mohor
wire [31:0] eth_sl_wb_adr;
149 116 mohor
wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
150
wire  [3:0] eth_sl_wb_sel_i;
151
wire        eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
152
 
153
// Ethernet Master Interface signals
154
wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
155
wire  [3:0] eth_ma_wb_sel_o;
156
wire        eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
157
 
158
 
159
 
160
 
161
// Connecting Ethernet top module
162 169 mohor
eth_top eth_top
163 116 mohor
(
164
  // WISHBONE common
165 169 mohor
  .wb_clk_i(wb_clk),              .wb_rst_i(wb_rst),
166 116 mohor
 
167
  // WISHBONE slave
168 169 mohor
  .wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i),   .wb_we_i(eth_sl_wb_we_i),
169
  .wb_cyc_i(eth_sl_wb_cyc_i),       .wb_stb_i(eth_sl_wb_stb_i),   .wb_ack_o(eth_sl_wb_ack_o),
170
  .wb_err_o(eth_sl_wb_err_o),       .wb_dat_i(eth_sl_wb_dat_i),   .wb_dat_o(eth_sl_wb_dat_o),
171 116 mohor
 
172
  // WISHBONE master
173
  .m_wb_adr_o(eth_ma_wb_adr_o),     .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
174
  .m_wb_dat_i(eth_ma_wb_dat_i),     .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
175
  .m_wb_stb_o(eth_ma_wb_stb_o),     .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
176
 
177
  //TX
178
  .mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
179
 
180
  //RX
181
  .mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
182
  .mcoll_pad_i(MColl),    .mcrs_pad_i(MCrs),
183
 
184
  // MIIM
185
  .mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
186
 
187 169 mohor
  .int_o(wb_int)
188 227 tadejm
 
189
  // Bist
190
`ifdef ETH_BIST
191
  ,
192
  .scanb_rst      (1'b0),
193
  .scanb_clk      (1'b0),
194
  .scanb_si       (1'b0),
195
  .scanb_so       (),
196
  .scanb_en       (1'b0)
197
`endif
198 116 mohor
);
199
 
200
 
201
 
202 169 mohor
// Connecting Ethernet PHY Module
203
assign Mdio_IO = Mdo_OE ? Mdo_O : 1'bz ;
204
assign Mdi_I   = Mdio_IO;
205
integer phy_log_file_desc;
206
 
207
eth_phy eth_phy
208 116 mohor
(
209 169 mohor
  // WISHBONE reset
210
  .m_rst_n_i(!wb_rst),
211 116 mohor
 
212 169 mohor
  // MAC TX
213
  .mtx_clk_o(mtx_clk),    .mtxd_i(MTxD),    .mtxen_i(MTxEn),    .mtxerr_i(MTxErr),
214
 
215
  // MAC RX
216
  .mrx_clk_o(mrx_clk),    .mrxd_o(MRxD),    .mrxdv_o(MRxDV),    .mrxerr_o(MRxErr),
217
  .mcoll_o(MColl),        .mcrs_o(MCrs),
218
 
219
  // MIIM
220
  .mdc_i(Mdc_O),          .md_io(Mdio_IO),
221
 
222
  // SYSTEM
223
  .phy_log(phy_log_file_desc)
224 116 mohor
);
225
 
226
 
227 169 mohor
 
228
// Connecting WB Master as Host Interface
229
integer host_log_file_desc;
230
 
231
WB_MASTER_BEHAVIORAL wb_master
232 116 mohor
(
233 169 mohor
    .CLK_I(wb_clk),
234
    .RST_I(wb_rst),
235
    .TAG_I({`WB_TAG_WIDTH{1'b0}}),
236
    .TAG_O(),
237
    .ACK_I(eth_sl_wb_ack_o),
238
    .ADR_O(eth_sl_wb_adr), // only eth_sl_wb_adr_i[11:2] used
239
    .CYC_O(eth_sl_wb_cyc_i),
240
    .DAT_I(eth_sl_wb_dat_o),
241
    .DAT_O(eth_sl_wb_dat_i),
242
    .ERR_I(eth_sl_wb_err_o),
243
    .RTY_I(1'b0),  // inactive (1'b0)
244
    .SEL_O(eth_sl_wb_sel_i),
245
    .STB_O(eth_sl_wb_stb_i),
246
    .WE_O (eth_sl_wb_we_i),
247
    .CAB_O()       // NOT USED for now!
248
);
249
 
250
assign eth_sl_wb_adr_i = {20'h0, eth_sl_wb_adr[11:2], 2'h0};
251
 
252
 
253
 
254
// Connecting WB Slave as Memory Interface Module
255
integer memory_log_file_desc;
256
 
257
WB_SLAVE_BEHAVIORAL wb_slave
258
(
259
    .CLK_I(wb_clk),
260
    .RST_I(wb_rst),
261
    .ACK_O(eth_ma_wb_ack_i),
262
    .ADR_I(eth_ma_wb_adr_o),
263
    .CYC_I(eth_ma_wb_cyc_o),
264
    .DAT_O(eth_ma_wb_dat_i),
265
    .DAT_I(eth_ma_wb_dat_o),
266
    .ERR_O(eth_ma_wb_err_i),
267
    .RTY_O(),      // NOT USED for now!
268
    .SEL_I(eth_ma_wb_sel_o),
269
    .STB_I(eth_ma_wb_stb_o),
270
    .WE_I (eth_ma_wb_we_o),
271
    .CAB_I(1'b0)   // inactive (1'b0)
272
);
273
 
274
 
275
 
276
// Connecting WISHBONE Bus Monitors to ethernet master and slave interfaces
277
integer wb_s_mon_log_file_desc ;
278
integer wb_m_mon_log_file_desc ;
279
 
280
WB_BUS_MON wb_eth_slave_bus_mon
281
(
282 116 mohor
  // WISHBONE common
283 169 mohor
  .CLK_I(wb_clk),
284
  .RST_I(wb_rst),
285 116 mohor
 
286 169 mohor
  // WISHBONE slave
287
  .ACK_I(eth_sl_wb_ack_o),
288
  .ADDR_O({20'h0, eth_sl_wb_adr_i[11:2], 2'b0}),
289
  .CYC_O(eth_sl_wb_cyc_i),
290
  .DAT_I(eth_sl_wb_dat_o),
291
  .DAT_O(eth_sl_wb_dat_i),
292
  .ERR_I(eth_sl_wb_err_o),
293
  .RTY_I(1'b0),
294
  .SEL_O(eth_sl_wb_sel_i),
295
  .STB_O(eth_sl_wb_stb_i),
296
  .WE_O (eth_sl_wb_we_i),
297
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
298
  .TAG_O(),
299
  .CAB_O(1'b0),
300
  .log_file_desc (wb_s_mon_log_file_desc)
301
);
302
 
303
WB_BUS_MON wb_eth_master_bus_mon
304
(
305
  // WISHBONE common
306
  .CLK_I(wb_clk),
307
  .RST_I(wb_rst),
308
 
309 116 mohor
  // WISHBONE master
310 169 mohor
  .ACK_I(eth_ma_wb_ack_i),
311
  .ADDR_O(eth_ma_wb_adr_o),
312
  .CYC_O(eth_ma_wb_cyc_o),
313
  .DAT_I(eth_ma_wb_dat_i),
314
  .DAT_O(eth_ma_wb_dat_o),
315
  .ERR_I(eth_ma_wb_err_i),
316
  .RTY_I(1'b0),
317
  .SEL_O(eth_ma_wb_sel_o),
318
  .STB_O(eth_ma_wb_stb_o),
319
  .WE_O (eth_ma_wb_we_o),
320
  .TAG_I({`WB_TAG_WIDTH{1'b0}}),
321
  .TAG_O(),
322
  .CAB_O(1'b0),
323
  .log_file_desc(wb_m_mon_log_file_desc)
324 116 mohor
);
325
 
326
 
327
 
328 169 mohor
reg         StartTB;
329
integer     tb_log_file;
330 116 mohor
 
331 169 mohor
initial
332
begin
333
  tb_log_file = $fopen("../log/eth_tb.log");
334
  if (tb_log_file < 2)
335
  begin
336
    $display("*E Could not open/create testbench log file in ../log/ directory!");
337
    $finish;
338
  end
339
  $fdisplay(tb_log_file, "========================== ETHERNET IP Core Testbench results ===========================");
340
  $fdisplay(tb_log_file, " ");
341 116 mohor
 
342 169 mohor
  phy_log_file_desc = $fopen("../log/eth_tb_phy.log");
343
  if (phy_log_file_desc < 2)
344
  begin
345
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_phy.log file in ../log/ directory!");
346
    $finish;
347
  end
348
  $fdisplay(phy_log_file_desc, "================ PHY Module  Testbench access log ================");
349
  $fdisplay(phy_log_file_desc, " ");
350
 
351
  memory_log_file_desc = $fopen("../log/eth_tb_memory.log");
352
  if (memory_log_file_desc < 2)
353
  begin
354
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_memory.log file in ../log/ directory!");
355
    $finish;
356
  end
357
  $fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ===============");
358
  $fdisplay(memory_log_file_desc, " ");
359
 
360
  host_log_file_desc = $fopen("../log/eth_tb_host.log");
361
  if (host_log_file_desc < 2)
362
  begin
363
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!");
364
    $finish;
365
  end
366
  $fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================");
367
  $fdisplay(host_log_file_desc, " ");
368
 
369
  wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log");
370
  if (wb_s_mon_log_file_desc < 2)
371
  begin
372
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!");
373
    $finish;
374
  end
375
  $fdisplay(wb_s_mon_log_file_desc, "============== WISHBONE Slave Bus Monitor error log ==============");
376
  $fdisplay(wb_s_mon_log_file_desc, " ");
377
  $fdisplay(wb_s_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
378
  $fdisplay(wb_s_mon_log_file_desc, " ");
379
 
380
  wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log");
381
  if (wb_m_mon_log_file_desc < 2)
382
  begin
383
    $fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!");
384
    $finish;
385
  end
386
  $fdisplay(wb_m_mon_log_file_desc, "============= WISHBONE Master Bus Monitor  error log =============");
387
  $fdisplay(wb_m_mon_log_file_desc, " ");
388
  $fdisplay(wb_m_mon_log_file_desc, "   Only ERRONEOUS conditions are logged !");
389
  $fdisplay(wb_m_mon_log_file_desc, " ");
390
 
391 243 tadejm
  // Reset pulse
392
  wb_rst =  1'b1;
393
  #423 wb_rst =  1'b0;
394
 
395 169 mohor
  // Clear memories
396
  clear_memories;
397 243 tadejm
  clear_buffer_descriptors;
398 169 mohor
 
399
  #423 StartTB  =  1'b1;
400
end
401
 
402
 
403
 
404
// Generating wb_clk clock
405 116 mohor
initial
406
begin
407 169 mohor
  wb_clk=0;
408
//  forever #2.5 wb_clk = ~wb_clk;  // 2*2.5 ns -> 200.0 MHz    
409 209 tadejm
  forever #5 wb_clk = ~wb_clk;  // 2*5 ns -> 100.0 MHz    
410 169 mohor
//  forever #10 wb_clk = ~wb_clk;  // 2*10 ns -> 50.0 MHz    
411
//  forever #12.5 wb_clk = ~wb_clk;  // 2*12.5 ns -> 40 MHz    
412
//  forever #15 wb_clk = ~wb_clk;  // 2*10 ns -> 33.3 MHz    
413 209 tadejm
//  forever #20 wb_clk = ~wb_clk;  // 2*20 ns -> 25 MHz    
414 169 mohor
//  forever #25 wb_clk = ~wb_clk;  // 2*25 ns -> 20.0 MHz
415
//  forever #31.25 wb_clk = ~wb_clk;  // 2*31.25 ns -> 16.0 MHz    
416
//  forever #50 wb_clk = ~wb_clk;  // 2*50 ns -> 10.0 MHz
417
//  forever #55 wb_clk = ~wb_clk;  // 2*55 ns ->  9.1 MHz    
418 116 mohor
end
419
 
420
 
421
 
422 169 mohor
integer      tests_successfull;
423
integer      tests_failed;
424
reg [799:0]  test_name; // used for tb_log_file
425 121 mohor
 
426 169 mohor
reg   [3:0]  wbm_init_waits; // initial wait cycles between CYC_O and STB_O of WB Master
427
reg   [3:0]  wbm_subseq_waits; // subsequent wait cycles between STB_Os of WB Master
428
reg   [2:0]  wbs_waits; // wait cycles befor WB Slave responds
429
reg   [7:0]  wbs_retries; // if RTY response, then this is the number of retries before ACK
430
 
431 116 mohor
initial
432
begin
433 169 mohor
  wait(StartTB);  // Start of testbench
434
 
435
  // Initial global values
436
  tests_successfull = 0;
437
  tests_failed = 0;
438
 
439
  wbm_init_waits = 4'h1;
440
  wbm_subseq_waits = 4'h3;
441
  wbs_waits = 4'h1;
442
  wbs_retries = 8'h2;
443
  wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
444
 
445
 
446
  //  Call tests
447
  //  ----------
448 194 tadej
//    test_access_to_mac_reg(0, 3);           // 0 - 3
449
//    test_mii(0, 17);                        // 0 - 17
450 169 mohor
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
451
  eth_phy.carrier_sense_real_delay(0);
452 243 tadejm
//    test_mac_full_duplex_transmit(8, 9);    // 0 - (21)
453 254 mohor
//    test_mac_full_duplex_receive(8, 9);
454 263 mohor
    test_mac_full_duplex_flow_control(0, 2);
455 169 mohor
 
456 243 tadejm
  test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
457 169 mohor
  eth_phy.carrier_sense_real_delay(1);
458
 
459
 
460
  // Finish test's logs
461
  test_summary;
462
  $display("\n\n END of SIMULATION");
463
  $fclose(tb_log_file | phy_log_file_desc | memory_log_file_desc | host_log_file_desc);
464
  $fclose(wb_s_mon_log_file_desc | wb_m_mon_log_file_desc);
465
 
466
  $stop;
467 116 mohor
end
468 169 mohor
 
469 116 mohor
 
470 169 mohor
 
471
//////////////////////////////////////////////////////////////
472
// Test tasks
473
//////////////////////////////////////////////////////////////
474
 
475
task test_access_to_mac_reg;
476
  input  [31:0]  start_task;
477
  input  [31:0]  end_task;
478
  integer        bit_start_1;
479
  integer        bit_end_1;
480
  integer        bit_start_2;
481
  integer        bit_end_2;
482
  integer        num_of_reg;
483
  integer        i_addr;
484
  integer        i_data;
485
  integer        i_length;
486
  integer        tmp_data;
487
  reg    [31:0]  tx_bd_num;
488
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
489
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
490
  integer        i;
491
  integer        i1;
492
  integer        i2;
493
  integer        i3;
494
  integer        fail;
495 178 mohor
  integer        test_num;
496 169 mohor
  reg    [31:0]  addr;
497
  reg    [31:0]  data;
498
  reg    [31:0]  data_max;
499 116 mohor
begin
500 169 mohor
// ACCESS TO MAC REGISTERS TEST
501
test_heading("ACCESS TO MAC REGISTERS TEST");
502
$display(" ");
503
$display("ACCESS TO MAC REGISTERS TEST");
504
fail = 0;
505
 
506 192 tadej
// reset MAC registers
507
hard_reset;
508
// reset MAC and MII LOGIC with soft reset
509
reset_mac;
510
reset_mii;
511 169 mohor
 
512 192 tadej
 
513 178 mohor
//////////////////////////////////////////////////////////////////////
514
////                                                              ////
515
////  test_access_to_mac_reg:                                     ////
516
////                                                              ////
517
////  0: Walking 1 with single cycles across MAC regs.            ////
518
////  1: Walking 1 with single cycles across MAC buffer descript. ////
519
////  2: Test max reg. values and reg. values after writing       ////
520
////     inverse reset values and hard reset of the MAC           ////
521
////  3: Test buffer desc. RAM preserving values after hard reset ////
522
////     of the MAC and resetting the logic                       ////
523
////                                                              ////
524
//////////////////////////////////////////////////////////////////////
525 194 tadej
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
526 169 mohor
begin
527
 
528 178 mohor
  ////////////////////////////////////////////////////////////////////
529
  ////                                                            ////
530
  ////  Walking 1 with single cycles across MAC regs.             ////
531
  ////                                                            ////
532
  ////////////////////////////////////////////////////////////////////
533
  if (test_num == 0) // Walking 1 with single cycles across MAC regs.
534 194 tadej
  begin
535
    // TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
536
    test_name   = "TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
537
    `TIME; $display("  TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
538 178 mohor
 
539 194 tadej
    data = 0;
540
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
541
      begin
542
        wbm_init_waits = i;
543
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
544
        for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
545
          begin
546
            addr = `ETH_BASE + i_addr;
547
            // set ranges of R/W bits
548
            case (addr)
549
              `ETH_MODER:
550
                begin
551
                  bit_start_1 = 0;
552
                  bit_end_1   = 16;
553
                  bit_start_2 = 32; // not used
554
                  bit_end_2   = 32; // not used
555
                end
556
              `ETH_INT: // READONLY - tested within INT test
557
                begin
558
                  bit_start_1 = 32; // not used
559
                  bit_end_1   = 32; // not used
560
                  bit_start_2 = 32; // not used
561
                  bit_end_2   = 32; // not used
562
                end
563
              `ETH_INT_MASK:
564
                begin
565
                  bit_start_1 = 0;
566
                  bit_end_1   = 6;
567
                  bit_start_2 = 32; // not used
568
                  bit_end_2   = 32; // not used
569
                end
570
              `ETH_IPGT:
571
                begin
572
                  bit_start_1 = 0;
573
                  bit_end_1   = 6;
574
                  bit_start_2 = 32; // not used
575
                  bit_end_2   = 32; // not used
576
                end
577
              `ETH_IPGR1:
578
                begin
579
                  bit_start_1 = 0;
580
                  bit_end_1   = 6;
581
                  bit_start_2 = 32; // not used
582
                  bit_end_2   = 32; // not used
583
                end
584
              `ETH_IPGR2:
585
                begin
586
                  bit_start_1 = 0;
587
                  bit_end_1   = 6;
588
                  bit_start_2 = 32; // not used
589
                  bit_end_2   = 32; // not used
590
                end
591
              `ETH_PACKETLEN:
592
                begin
593
                  bit_start_1 = 0;
594
                  bit_end_1   = 31;
595
                  bit_start_2 = 32; // not used
596
                  bit_end_2   = 32; // not used
597
                end
598
              `ETH_COLLCONF:
599
                begin
600
                  bit_start_1 = 0;
601
                  bit_end_1   = 5;
602
                  bit_start_2 = 16;
603
                  bit_end_2   = 19;
604
                end
605
              `ETH_TX_BD_NUM:
606
                begin
607
                  bit_start_1 = 0;
608
                  bit_end_1   = 7;
609
                  bit_start_2 = 32; // not used
610
                  bit_end_2   = 32; // not used
611
                end
612
              `ETH_CTRLMODER:
613
                begin
614
                  bit_start_1 = 0;
615
                  bit_end_1   = 2;
616
                  bit_start_2 = 32; // not used
617
                  bit_end_2   = 32; // not used
618
                end
619
              `ETH_MIIMODER:
620
                begin
621
                  bit_start_1 = 0;
622
                  bit_end_1   = 9;
623
                  bit_start_2 = 32; // not used
624
                  bit_end_2   = 32; // not used
625
                end
626
              `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
627
                begin
628
                  bit_start_1 = 32; // not used
629
                  bit_end_1   = 32; // not used
630
                  bit_start_2 = 32; // not used
631
                  bit_end_2   = 32; // not used
632
                end
633
              `ETH_MIIADDRESS:
634
                begin
635
                  bit_start_1 = 0;
636
                  bit_end_1   = 4;
637
                  bit_start_2 = 8;
638
                  bit_end_2   = 12;
639
                end
640
              `ETH_MIITX_DATA:
641
                begin
642
                  bit_start_1 = 0;
643
                  bit_end_1   = 15;
644
                  bit_start_2 = 32; // not used
645
                  bit_end_2   = 32; // not used
646
                end
647
              `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
648
                begin
649
                  bit_start_1 = 32; // not used
650
                  bit_end_1   = 32; // not used
651
                  bit_start_2 = 32; // not used
652
                  bit_end_2   = 32; // not used
653
                end
654
              `ETH_MIISTATUS: // READONLY - tested within MIIM test
655
                begin
656
                  bit_start_1 = 32; // not used
657
                  bit_end_1   = 32; // not used
658
                  bit_start_2 = 32; // not used
659
                  bit_end_2   = 32; // not used
660
                end
661
              `ETH_MAC_ADDR0:
662
                begin
663
                  bit_start_1 = 0;
664
                  bit_end_1   = 31;
665
                  bit_start_2 = 32; // not used
666
                  bit_end_2   = 32; // not used
667 178 mohor
                  end
668 194 tadej
              `ETH_MAC_ADDR1:
669
                begin
670
                  bit_start_1 = 0;
671
                  bit_end_1   = 15;
672
                  bit_start_2 = 32; // not used
673
                  bit_end_2   = 32; // not used
674
                end
675
              `ETH_HASH_ADDR0:
676
                begin
677
                  bit_start_1 = 0;
678
                  bit_end_1   = 31;
679
                  bit_start_2 = 32; // not used
680
                  bit_end_2   = 32; // not used
681
                end
682
              default: // `ETH_HASH_ADDR1:
683
                begin
684
                  bit_start_1 = 0;
685
                  bit_end_1   = 31;
686
                  bit_start_2 = 32; // not used
687
                  bit_end_2   = 32; // not used
688
                end
689
            endcase
690
 
691
            for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
692
              begin
693
                data = 1'b1 << i_data;
694
                if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
695
                  ;
696
                else
697 178 mohor
                  begin
698 194 tadej
                    wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
699
                    wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
700
                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
701
                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
702
                      begin
703
                        if (tmp_data !== data)
704 178 mohor
                        begin
705 194 tadej
                          fail = fail + 1;
706
                          test_fail("RW bit of the MAC register was not written or not read");
707
                          `TIME;
708
                          $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
709
                                    wbm_init_waits, addr, data, tmp_data);
710
                        end
711
                      end
712
                    else // data should not be equal to tmp_data
713
                      begin
714
                        if (tmp_data === data)
715 178 mohor
                          begin
716
                            fail = fail + 1;
717 194 tadej
                            test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
718 178 mohor
                            `TIME;
719 194 tadej
                            $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
720 178 mohor
                                      wbm_init_waits, addr, data, tmp_data);
721
                          end
722 194 tadej
                      end
723
                  end
724
              end
725
          end
726
      end
727 209 tadejm
    // INTERMEDIATE DISPLAYS (The only one)
728
    $display("    ->buffer descriptors tested with 0, 1, 2, 3 and 4 bus delay cycles");
729 194 tadej
    if(fail == 0)
730
      test_ok;
731
    else
732
      fail = 0;    // Errors were reported previously
733
  end
734 178 mohor
 
735
 
736
  ////////////////////////////////////////////////////////////////////
737
  ////                                                            ////
738
  ////  Walking 1 with single cycles across MAC buffer descript.  ////
739
  ////                                                            ////
740
  ////////////////////////////////////////////////////////////////////
741
  if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
742 169 mohor
  begin
743 194 tadej
    // TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
744
    test_name   = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
745
    `TIME; $display("  TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
746 178 mohor
 
747
    data = 0;
748
    // set TX and RX buffer descriptors
749
    tx_bd_num = 32'h40;
750
    wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
751
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
752
    begin
753 169 mohor
      wbm_init_waits = i;
754
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
755 178 mohor
      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
756 169 mohor
      begin
757
        addr = `ETH_BASE + i_addr;
758 178 mohor
        if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
759
        begin
760
          // set ranges of R/W bits
761
          case (addr[3])
762
            1'b0: // buffer control bits
763
            begin
764
              bit_start_1 = 0;
765
              bit_end_1   = 31; // 8;
766
              bit_start_2 = 11;
767
              bit_end_2   = 31;
768
            end
769
            default: // 1'b1: // buffer pointer
770
            begin
771
              bit_start_1 = 0;
772
              bit_end_1   = 31;
773
              bit_start_2 = 32; // not used
774
              bit_end_2   = 32; // not used
775
            end
776
          endcase
777
        end
778
        else // RX buffer descriptors
779
        begin
780
          // set ranges of R/W bits
781
          case (addr[3])
782
            1'b0: // buffer control bits
783
            begin
784
              bit_start_1 = 0;
785
              bit_end_1   = 31; // 7;
786
              bit_start_2 = 13;
787
              bit_end_2   = 31;
788
            end
789
            default: // 1'b1: // buffer pointer
790
            begin
791
              bit_start_1 = 0;
792
              bit_end_1   = 31;
793
              bit_start_2 = 32; // not used
794
              bit_end_2   = 32; // not used
795
            end
796
          endcase
797
        end
798
 
799 169 mohor
        for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
800
        begin
801
          data = 1'b1 << i_data;
802 178 mohor
          if ( (addr[3] == 0) && (i_data == 15) ) // DO NOT WRITE to this bit !!!
803
            ;
804 169 mohor
          else
805
          begin
806
            wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
807
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
808
            if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
809
                 ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
810
            begin
811
              if (tmp_data !== data)
812
              begin
813
                fail = fail + 1;
814 178 mohor
                test_fail("RW bit of the MAC buffer descriptors was not written or not read");
815 169 mohor
                `TIME;
816
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
817
                          wbm_init_waits, addr, data, tmp_data);
818
              end
819
            end
820
            else // data should not be equal to tmp_data
821
            begin
822
              if (tmp_data === data)
823
              begin
824
                fail = fail + 1;
825 178 mohor
                test_fail("NON RW bit of the MAC buffer descriptors was written, but it shouldn't be");
826 169 mohor
                `TIME;
827
                $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
828
                          wbm_init_waits, addr, data, tmp_data);
829
              end
830
            end
831
          end
832
        end
833
      end
834 178 mohor
      // INTERMEDIATE DISPLAYS
835
      case (i)
836 209 tadejm
        0:       $display("    ->buffer descriptors tested with 0 bus delay");
837
        1:       $display("    ->buffer descriptors tested with 1 bus delay cycle");
838
        2:       $display("    ->buffer descriptors tested with 2 bus delay cycles");
839
        3:       $display("    ->buffer descriptors tested with 3 bus delay cycles");
840
        default: $display("    ->buffer descriptors tested with 4 bus delay cycles");
841 178 mohor
      endcase
842
    end
843
    if(fail == 0)
844
      test_ok;
845
    else
846
      fail = 0;
847 169 mohor
  end
848 178 mohor
 
849
 
850
  ////////////////////////////////////////////////////////////////////
851
  ////                                                            ////
852
  ////  Test max reg. values and reg. values after writing        ////
853
  ////  inverse reset values and hard reset of the MAC            ////
854
  ////                                                            ////
855
  ////////////////////////////////////////////////////////////////////
856
  if (test_num == 2) // Start this task
857 169 mohor
  begin
858 194 tadej
    // TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
859 178 mohor
    test_name   =
860 194 tadej
      "TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC";
861 178 mohor
    `TIME; $display(
862 194 tadej
      "  TEST 2: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC");
863 178 mohor
 
864
    // reset MAC registers
865
    hard_reset;
866
    for (i = 0; i <= 4; i = i + 1) // 0, 2 - WRITE; 1, 3, 4 - READ
867 169 mohor
    begin
868 178 mohor
      for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
869 169 mohor
      begin
870 178 mohor
        addr = `ETH_BASE + i_addr;
871
        // set ranges of R/W bits
872
        case (addr)
873
          `ETH_MODER:
874 169 mohor
          begin
875 178 mohor
            data = 32'h0000_A800;
876
            data_max = 32'h0001_FFFF;
877 169 mohor
          end
878 178 mohor
          `ETH_INT: // READONLY - tested within INT test
879 169 mohor
          begin
880 178 mohor
            data = 32'h0000_0000;
881
            data_max = 32'h0000_0000;
882 169 mohor
          end
883
          `ETH_INT_MASK:
884 178 mohor
          begin
885
            data = 32'h0000_0000;
886
            data_max = 32'h0000_007F;
887
          end
888 169 mohor
          `ETH_IPGT:
889 178 mohor
          begin
890
            data = 32'h0000_0012;
891
            data_max = 32'h0000_007F;
892
          end
893 169 mohor
          `ETH_IPGR1:
894 178 mohor
          begin
895
            data = 32'h0000_000C;
896
            data_max = 32'h0000_007F;
897
          end
898 169 mohor
          `ETH_IPGR2:
899 178 mohor
          begin
900
            data = 32'h0000_0012;
901
            data_max = 32'h0000_007F;
902
          end
903 169 mohor
          `ETH_PACKETLEN:
904 178 mohor
          begin
905
            data = 32'h0040_0600;
906
            data_max = 32'hFFFF_FFFF;
907
          end
908 169 mohor
          `ETH_COLLCONF:
909 178 mohor
          begin
910
            data = 32'h000F_003F;
911
            data_max = 32'h000F_003F;
912
          end
913 169 mohor
          `ETH_TX_BD_NUM:
914 178 mohor
          begin
915
            data = 32'h0000_0040;
916
            data_max = 32'h0000_0080;
917
          end
918 169 mohor
          `ETH_CTRLMODER:
919 178 mohor
          begin
920
            data = 32'h0000_0000;
921
            data_max = 32'h0000_0007;
922
          end
923 169 mohor
          `ETH_MIIMODER:
924 178 mohor
          begin
925
            data = 32'h0000_0064;
926
            data_max = 32'h0000_03FF;
927
          end
928 169 mohor
          `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
929 178 mohor
          begin
930
            data = 32'h0000_0000;
931
            data_max = 32'h0000_0007;
932
          end
933 169 mohor
          `ETH_MIIADDRESS:
934 178 mohor
          begin
935
            data = 32'h0000_0000;
936
            data_max = 32'h0000_1F1F;
937
          end
938 169 mohor
          `ETH_MIITX_DATA:
939 178 mohor
          begin
940
            data = 32'h0000_0000;
941
            data_max = 32'h0000_FFFF;
942
          end
943 169 mohor
          `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
944
          begin
945 178 mohor
            data = 32'h0000_0000;
946
            data_max = 32'h0000_0000;
947 169 mohor
          end
948 178 mohor
          `ETH_MIISTATUS: // READONLY - tested within MIIM test
949 169 mohor
          begin
950 178 mohor
            data = 32'h0000_0000;
951
            data_max = 32'h0000_0000;
952 169 mohor
          end
953 178 mohor
          `ETH_MAC_ADDR0:
954 169 mohor
          begin
955 178 mohor
            data = 32'h0000_0000;
956
            data_max = 32'hFFFF_FFFF;
957 169 mohor
          end
958 178 mohor
          `ETH_MAC_ADDR1:
959 169 mohor
          begin
960 178 mohor
            data = 32'h0000_0000;
961
            data_max = 32'h0000_FFFF;
962 169 mohor
          end
963 178 mohor
          `ETH_HASH_ADDR0:
964 169 mohor
          begin
965 178 mohor
            data = 32'h0000_0000;
966
            data_max = 32'hFFFF_FFFF;
967 169 mohor
          end
968 178 mohor
          default: // `ETH_HASH_ADDR1:
969 169 mohor
          begin
970 178 mohor
            data = 32'h0000_0000;
971
            data_max = 32'hFFFF_FFFF;
972 169 mohor
          end
973
        endcase
974 178 mohor
 
975
        wbm_init_waits = {$random} % 3;
976
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
977
        if (i == 0)
978
          wbm_write(addr, ~data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
979
        else if (i == 2)
980
          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
981
        else if ((i == 1) || (i == 4))
982 169 mohor
        begin
983 178 mohor
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
984
          if (tmp_data !== data)
985
          begin
986
            fail = fail + 1;
987
            test_fail("RESET value of the MAC register is not correct");
988
            `TIME;
989
            $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
990
          end
991 169 mohor
        end
992 178 mohor
        else // check maximum values
993 169 mohor
        begin
994
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
995 178 mohor
          if (addr == `ETH_TX_BD_NUM) // previous data should remain in this register
996 169 mohor
          begin
997
            if (tmp_data !== data)
998
            begin
999
              fail = fail + 1;
1000 178 mohor
              test_fail("Previous value of the TX_BD_NUM register did not remain");
1001 169 mohor
              `TIME;
1002 178 mohor
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1003 169 mohor
            end
1004 178 mohor
            // try maximum (80)
1005
            wbm_write(addr, data_max, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1006
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1007
            if (tmp_data !== data_max)
1008
            begin
1009
              fail = fail + 1;
1010
              test_fail("MAX value of the TX_BD_NUM register is not correct");
1011
              `TIME;
1012
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1013
            end
1014
            // try one less than maximum (80)
1015
            wbm_write(addr, (data_max - 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1016
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1017
            if (tmp_data !== (data_max - 1))
1018
            begin
1019
              fail = fail + 1;
1020
              test_fail("ONE less than MAX value of the TX_BD_NUM register is not correct");
1021
              `TIME;
1022
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1023
            end
1024
            // try one more than maximum (80)
1025
            wbm_write(addr, (data_max + 1), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1026
            wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1027
            if (tmp_data !== (data_max - 1)) // previous data should remain in this register
1028
            begin
1029
              fail = fail + 1;
1030
              test_fail("Previous value of the TX_BD_NUM register did not remain");
1031
              `TIME;
1032
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1033
            end
1034 169 mohor
          end
1035 178 mohor
          else
1036 169 mohor
          begin
1037 178 mohor
            if (tmp_data !== data_max)
1038 169 mohor
            begin
1039
              fail = fail + 1;
1040 178 mohor
              test_fail("MAX value of the MAC register is not correct");
1041 169 mohor
              `TIME;
1042 178 mohor
              $display("  addr %h, data_max %h, tmp_data %h", addr, data_max, tmp_data);
1043 169 mohor
            end
1044
          end
1045
        end
1046
      end
1047 178 mohor
      // reset MAC registers
1048
      if ((i == 0) || (i == 3))
1049
        hard_reset;
1050 169 mohor
    end
1051 178 mohor
    if(fail == 0)
1052
      test_ok;
1053
    else
1054
      fail = 0;
1055 169 mohor
  end
1056 116 mohor
 
1057 156 mohor
 
1058 181 mohor
  ////////////////////////////////////////////////////////////////////
1059
  ////                                                            ////
1060
  ////  Test buffer desc. ram preserving values after hard reset  ////
1061
  ////  of the mac and reseting the logic                         ////
1062
  ////                                                            ////
1063
  ////////////////////////////////////////////////////////////////////
1064 178 mohor
  if (test_num == 3) // Start this task
1065 169 mohor
  begin
1066 194 tadej
    // TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
1067
    test_name   = "TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC";
1068 178 mohor
    `TIME;
1069 194 tadej
    $display("  TEST 3: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC");
1070 178 mohor
 
1071
    // reset MAC registers
1072
    hard_reset;
1073
    // reset LOGIC with soft reset
1074
    reset_mac;
1075
    reset_mii;
1076
    for (i = 0; i <= 3; i = i + 1) // 0, 2 - WRITE; 1, 3 - READ
1077 169 mohor
    begin
1078 178 mohor
      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
1079 169 mohor
      begin
1080 178 mohor
        addr = `ETH_BASE + i_addr;
1081
 
1082
        wbm_init_waits = {$random} % 3;
1083
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
1084
        if (i == 0)
1085 169 mohor
        begin
1086 178 mohor
          data = 32'hFFFFFFFF;
1087
          wbm_write(addr, 32'hFFFFFFFF, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1088 169 mohor
        end
1089 178 mohor
        else if (i == 2)
1090 169 mohor
        begin
1091 178 mohor
          data = 32'h00000000;
1092
          wbm_write(addr, 32'h00000000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1093 169 mohor
        end
1094
        else
1095
        begin
1096 178 mohor
          wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1097
          if (tmp_data !== data)
1098 169 mohor
          begin
1099
            fail = fail + 1;
1100 178 mohor
            test_fail("PRESERVED value of the MAC buffer descriptors is not correct");
1101 169 mohor
            `TIME;
1102 178 mohor
            $display("  addr %h, data %h, tmp_data %h", addr, data, tmp_data);
1103 169 mohor
          end
1104
        end
1105
      end
1106 178 mohor
      if ((i == 0) || (i == 2))
1107
      begin
1108
        // reset MAC registers
1109
        hard_reset;
1110
        // reset LOGIC with soft reset
1111
        reset_mac;
1112
        reset_mii;
1113
      end
1114 169 mohor
    end
1115 178 mohor
    if(fail == 0)
1116
      test_ok;
1117
    else
1118
    fail = 0;
1119 169 mohor
  end
1120 116 mohor
 
1121
 
1122 178 mohor
  if (test_num == 4) // Start this task
1123 169 mohor
  begin
1124 194 tadej
        /*  // TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
1125
          test_name   = "TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
1126
          `TIME; $display("  TEST 4: 'WALKING ONE' WITH BURST CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
1127 178 mohor
 
1128
          data = 0;
1129
          burst_data = 0;
1130
          burst_tmp_data = 0;
1131
          i_length = 10; // two bursts for length 20
1132
          for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
1133
          begin
1134
            for (i1 = 0; i1 <= 4; i1 = i1 + 1) // for initial wait cycles on WB bus
1135
            begin
1136
              wbm_init_waits = i;
1137
              wbm_subseq_waits = i1;
1138
              #1;
1139
              for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
1140
              begin
1141
                data = 1'b1 << i_data;
1142
                #1;
1143
                for (i2 = 32'h4C; i2 >= 0; i2 = i2 - 4)
1144
                begin
1145
                  burst_data = burst_data << 32;
1146
                  // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
1147
                  if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
1148
                  begin
1149
                    #1 burst_data[31:0] = 0;
1150
                  end
1151
                  else
1152
                  begin
1153
                    #1 burst_data[31:0] = data;
1154
                  end
1155
                end
1156
                #1;
1157
                // 2 burst writes
1158
                addr = `ETH_BASE; // address of a first burst
1159
                wbm_write(addr, burst_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
1160
                burst_tmp_data = burst_data >> (32 * i_length);
1161
                addr = addr + 32'h28; // address of a second burst
1162
                wbm_write(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length, wbm_init_waits, wbm_subseq_waits);
1163
                #1;
1164
                // 2 burst reads
1165
                addr = `ETH_BASE; // address of a first burst
1166
                wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
1167
                         wbm_init_waits, wbm_subseq_waits); // first burst
1168
                burst_tmp_data = burst_tmp_data << (32 * i_length);
1169
                addr = addr + 32'h28; // address of a second burst
1170
                wbm_read(addr, burst_tmp_data[(32 * 10 - 1):0], 4'hF, i_length,
1171
                         wbm_init_waits, wbm_subseq_waits); // second burst
1172
                #1;
1173
                for (i2 = 0; i2 <= 32'h4C; i2 = i2 + 4)
1174
                begin
1175
                  // set ranges of R/W bits
1176
                  case (`ETH_BASE + i2)
1177
                  `ETH_MODER:
1178
                    begin
1179
                      bit_start_1 = 0;
1180
                      bit_end_1   = 16;
1181
                      bit_start_2 = 32; // not used
1182
                      bit_end_2   = 32; // not used
1183
                    end
1184
                  `ETH_INT: // READONLY - tested within INT test
1185
                    begin
1186
                      bit_start_1 = 32; // not used
1187
                      bit_end_1   = 32; // not used
1188
                      bit_start_2 = 32; // not used
1189
                      bit_end_2   = 32; // not used
1190
                    end
1191
                  `ETH_INT_MASK:
1192
                    begin
1193
                      bit_start_1 = 0;
1194
                      bit_end_1   = 6;
1195
                      bit_start_2 = 32; // not used
1196
                      bit_end_2   = 32; // not used
1197
                    end
1198
                  `ETH_IPGT:
1199
                    begin
1200
                      bit_start_1 = 0;
1201
                      bit_end_1   = 6;
1202
                      bit_start_2 = 32; // not used
1203
                      bit_end_2   = 32; // not used
1204
                    end
1205
                  `ETH_IPGR1:
1206
                    begin
1207
                      bit_start_1 = 0;
1208
                      bit_end_1   = 6;
1209
                      bit_start_2 = 32; // not used
1210
                      bit_end_2   = 32; // not used
1211
                    end
1212
                  `ETH_IPGR2:
1213
                    begin
1214
                      bit_start_1 = 0;
1215
                      bit_end_1   = 6;
1216
                      bit_start_2 = 32; // not used
1217
                      bit_end_2   = 32; // not used
1218
                    end
1219
                  `ETH_PACKETLEN:
1220
                    begin
1221
                      bit_start_1 = 0;
1222
                      bit_end_1   = 31;
1223
                      bit_start_2 = 32; // not used
1224
                      bit_end_2   = 32; // not used
1225
                    end
1226
                  `ETH_COLLCONF:
1227
                    begin
1228
                      bit_start_1 = 0;
1229
                      bit_end_1   = 5;
1230
                      bit_start_2 = 16;
1231
                      bit_end_2   = 19;
1232
                    end
1233
                  `ETH_TX_BD_NUM:
1234
                    begin
1235
                      bit_start_1 = 0;
1236
                      bit_end_1   = 7;
1237
                      bit_start_2 = 32; // not used
1238
                      bit_end_2   = 32; // not used
1239
                    end
1240
                  `ETH_CTRLMODER:
1241
                    begin
1242
                      bit_start_1 = 0;
1243
                      bit_end_1   = 2;
1244
                      bit_start_2 = 32; // not used
1245
                      bit_end_2   = 32; // not used
1246
                    end
1247
                  `ETH_MIIMODER:
1248
                    begin
1249
                      bit_start_1 = 0;
1250
                      bit_end_1   = 9;
1251
                      bit_start_2 = 32; // not used
1252
                      bit_end_2   = 32; // not used
1253
                    end
1254
                  `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
1255
                    begin
1256
                      bit_start_1 = 32; // not used
1257
                      bit_end_1   = 32; // not used
1258
                      bit_start_2 = 32; // not used
1259
                      bit_end_2   = 32; // not used
1260
                    end
1261
                  `ETH_MIIADDRESS:
1262
                    begin
1263
                      bit_start_1 = 0;
1264
                      bit_end_1   = 4;
1265
                      bit_start_2 = 8;
1266
                      bit_end_2   = 12;
1267
                    end
1268
                  `ETH_MIITX_DATA:
1269
                    begin
1270
                      bit_start_1 = 0;
1271
                      bit_end_1   = 15;
1272
                      bit_start_2 = 32; // not used
1273
                      bit_end_2   = 32; // not used
1274
                    end
1275
                  `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
1276
                    begin
1277
                      bit_start_1 = 32; // not used
1278
                      bit_end_1   = 32; // not used
1279
                      bit_start_2 = 32; // not used
1280
                      bit_end_2   = 32; // not used
1281
                    end
1282
                  `ETH_MIISTATUS: // READONLY - tested within MIIM test
1283
                    begin
1284
                      bit_start_1 = 32; // not used
1285
                      bit_end_1   = 32; // not used
1286
                      bit_start_2 = 32; // not used
1287
                      bit_end_2   = 32; // not used
1288
                    end
1289
                  `ETH_MAC_ADDR0:
1290
                    begin
1291
                      bit_start_1 = 0;
1292
                      bit_end_1   = 31;
1293
                      bit_start_2 = 32; // not used
1294
                      bit_end_2   = 32; // not used
1295
                    end
1296
                  `ETH_MAC_ADDR1:
1297
                    begin
1298
                      bit_start_1 = 0;
1299
                      bit_end_1   = 15;
1300
                      bit_start_2 = 32; // not used
1301
                      bit_end_2   = 32; // not used
1302
                    end
1303
                  `ETH_HASH_ADDR0:
1304
                    begin
1305
                      bit_start_1 = 0;
1306
                      bit_end_1   = 31;
1307
                      bit_start_2 = 32; // not used
1308
                      bit_end_2   = 32; // not used
1309
                    end
1310
                  default: // `ETH_HASH_ADDR1:
1311
                    begin
1312
                      bit_start_1 = 0;
1313
                      bit_end_1   = 31;
1314
                      bit_start_2 = 32; // not used
1315
                      bit_end_2   = 32; // not used
1316
                    end
1317
                  endcase
1318
                  #1;
1319
                  // 3 LSBits of MIICOMMAND are NOT written !!!
1320
                  if ( ((`ETH_BASE + i2) == `ETH_MIICOMMAND) && (i_data <= 2) )
1321
                  begin
1322
                    if (burst_tmp_data[31:0] !== burst_data[31:0])
1323
                    begin
1324
                      fail = fail + 1;
1325
                      test_fail("NON WR bit of the MAC MIICOMMAND register was wrong written or read");
1326
                      `TIME;
1327
                      $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1328
                                wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1329
                    end
1330
                  end
1331
                  else
1332
                  begin
1333
                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
1334
                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
1335
                    begin
1336
                      if (burst_tmp_data[31:0] !== burst_data[31:0])
1337
                      begin
1338
                        fail = fail + 1;
1339
                        test_fail("RW bit of the MAC register was not written or not read");
1340
                        `TIME;
1341
                        $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1342
                                  wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1343
                      end
1344
                    end
1345
                    else // data should not be equal to tmp_data
1346
                    begin
1347
                      if (burst_tmp_data[31:0] === burst_data[31:0])
1348
                      begin
1349
                        fail = fail + 1;
1350
                        test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
1351
                        `TIME;
1352
                        $display("wbm_init_waits %d, wbm_subseq_waits %d, addr %h, data %h, tmp_data %h",
1353
                                  wbm_init_waits, wbm_subseq_waits, i2, burst_data[31:0], burst_tmp_data[31:0]);
1354
                      end
1355
                    end
1356
                  end
1357
                  burst_tmp_data = burst_tmp_data >> 32;
1358
                  burst_data = burst_data >> 32;
1359
                end
1360
              end
1361
            end
1362
          end
1363
          if(fail == 0)
1364
            test_ok;
1365
          else
1366
            fail = 0;*/
1367
  end
1368 116 mohor
 
1369 169 mohor
end
1370 156 mohor
 
1371 169 mohor
end
1372
endtask // test_access_to_mac_reg
1373 156 mohor
 
1374
 
1375 169 mohor
task test_mii;
1376
  input  [31:0]  start_task;
1377
  input  [31:0]  end_task;
1378
  integer        i;
1379
  integer        i1;
1380
  integer        i2;
1381
  integer        i3;
1382
  integer        cnt;
1383
  integer        fail;
1384 181 mohor
  integer        test_num;
1385 169 mohor
  reg     [8:0]  clk_div; // only 8 bits are valid!
1386
  reg     [4:0]  phy_addr;
1387
  reg     [4:0]  reg_addr;
1388
  reg     [15:0] phy_data;
1389
  reg     [15:0] tmp_data;
1390
begin
1391
// MIIM MODULE TEST
1392
test_heading("MIIM MODULE TEST");
1393
$display(" ");
1394
$display("MIIM MODULE TEST");
1395
fail = 0;
1396 156 mohor
 
1397 192 tadej
// reset MAC registers
1398
hard_reset;
1399
// reset MAC and MII LOGIC with soft reset
1400
reset_mac;
1401 169 mohor
reset_mii;
1402 116 mohor
 
1403 194 tadej
 
1404 181 mohor
//////////////////////////////////////////////////////////////////////
1405
////                                                              ////
1406
////  test_mii:                                                   ////
1407
////                                                              ////
1408
////  0:  Test clock divider of mii management module with all    ////
1409
////      possible frequences.                                    ////
1410
////  1:  Test various readings from 'real' phy registers.        ////
1411
////  2:  Test various writings to 'real' phy registers (control  ////
1412
////      and non writable registers)                             ////
1413
////  3:  Test reset phy through mii management module            ////
1414
////  4:  Test 'walking one' across phy address (with and without ////
1415
////      preamble)                                               ////
1416
////  5:  Test 'walking one' across phy's register address (with  ////
1417
////      and without preamble)                                   ////
1418
////  6:  Test 'walking one' across phy's data (with and without  ////
1419
////      preamble)                                               ////
1420
////  7:  Test reading from phy with wrong phy address (host      ////
1421
////      reading high 'z' data)                                  ////
1422
////  8:  Test writing to phy with wrong phy address and reading  ////
1423
////      from correct one                                        ////
1424
////  9:  Test sliding stop scan command immediately after read   ////
1425
////      request (with and without preamble)                     ////
1426
//// 10:  Test sliding stop scan command immediately after write  ////
1427
////      request (with and without preamble)                     ////
1428
//// 11:  Test busy and nvalid status durations during write      ////
1429
////      (with and without preamble)                             ////
1430
//// 12:  Test busy and nvalid status durations during write      ////
1431
////      (with and without preamble)                             ////
1432
//// 13:  Test busy and nvalid status durations during scan (with ////
1433
////      and without preamble)                                   ////
1434
//// 14:  Test scan status from phy with detecting link-fail bit  ////
1435
////      (with and without preamble)                             ////
1436
//// 15:  Test scan status from phy with sliding link-fail bit    ////
1437
////      (with and without preamble)                             ////
1438
//// 16:  Test sliding stop scan command immediately after scan   ////
1439
////      request (with and without preamble)                     ////
1440
//// 17:  Test sliding stop scan command after 2. scan (with and  ////
1441
////      without preamble)                                       ////
1442
////                                                              ////
1443
//////////////////////////////////////////////////////////////////////
1444 194 tadej
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
1445 169 mohor
begin
1446 194 tadej
 
1447 181 mohor
  ////////////////////////////////////////////////////////////////////
1448
  ////                                                            ////
1449
  ////  Test clock divider of mii management module with all      ////
1450
  ////  possible frequences.                                      ////
1451
  ////                                                            ////
1452
  ////////////////////////////////////////////////////////////////////
1453
  if (test_num == 0) // Test clock divider of mii management module with all possible frequences.
1454 169 mohor
  begin
1455 194 tadej
    // TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
1456
    test_name   = "TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES";
1457
    `TIME; $display("  TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES");
1458 181 mohor
 
1459
    wait(Mdc_O); // wait for MII clock to be 1
1460
    for(clk_div = 0; clk_div <= 255; clk_div = clk_div + 1)
1461
    begin
1462
      i1 = 0;
1463
      i2 = 0;
1464
      #Tp mii_set_clk_div(clk_div[7:0]);
1465
      @(posedge Mdc_O);
1466
      #Tp;
1467
      fork
1468 169 mohor
        begin
1469 181 mohor
          @(posedge Mdc_O);
1470 169 mohor
          #Tp;
1471 181 mohor
          disable count_i1;
1472
          disable count_i2;
1473 169 mohor
        end
1474 181 mohor
        begin: count_i1
1475
          forever
1476
          begin
1477
            @(posedge wb_clk);
1478
            i1 = i1 + 1;
1479
            #Tp;
1480
          end
1481
        end
1482
        begin: count_i2
1483
          forever
1484
          begin
1485
            @(negedge wb_clk);
1486
            i2 = i2 + 1;
1487
            #Tp;
1488
          end
1489
        end
1490
      join
1491
      if((clk_div[7:0] == 0) || (clk_div[7:0] == 1) || (clk_div[7:0] == 2) || (clk_div[7:0] == 3))
1492
      begin
1493
        if((i1 == i2) && (i1 == 2))
1494 169 mohor
        begin
1495
        end
1496 181 mohor
        else
1497
        begin
1498
          fail = fail + 1;
1499 209 tadejm
          test_fail("Clock divider of MII module did'nt divide frequency corectly (it should divide by 2)");
1500 181 mohor
        end
1501 169 mohor
      end
1502
      else
1503
      begin
1504 181 mohor
        if((i1 == i2) && (i1 == {clk_div[7:1], 1'b0}))
1505
        begin
1506
        end
1507
        else
1508
        begin
1509
          fail = fail + 1;
1510
          test_fail("Clock divider of MII module did'nt divide frequency corectly");
1511
        end
1512 169 mohor
      end
1513
    end
1514 181 mohor
    if(fail == 0)
1515
      test_ok;
1516 169 mohor
    else
1517 181 mohor
      fail = 0;
1518
  end
1519
 
1520
 
1521
  ////////////////////////////////////////////////////////////////////
1522
  ////                                                            ////
1523
  ////  Test various readings from 'real' phy registers.          ////
1524
  ////                                                            ////
1525
  ////////////////////////////////////////////////////////////////////
1526
  if (test_num == 1) // Test various readings from 'real' phy registers.
1527
  begin
1528 194 tadej
    // TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS
1529
    test_name   = "TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS";
1530
    `TIME; $display("  TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS");
1531 181 mohor
 
1532
    // set the fastest possible MII
1533
    clk_div = 0;
1534
    mii_set_clk_div(clk_div[7:0]);
1535
    // set address
1536
    reg_addr = 5'h1F;
1537
    phy_addr = 5'h1;
1538
    while(reg_addr >= 5'h4)
1539 169 mohor
    begin
1540 181 mohor
      // read request
1541
      #Tp mii_read_req(phy_addr, reg_addr);
1542
      check_mii_busy; // wait for read to finish
1543
      // read data
1544
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1545
      if (phy_data !== 16'hDEAD)
1546 169 mohor
      begin
1547 181 mohor
        test_fail("Wrong data was read from PHY from 'not used' address space");
1548
        fail = fail + 1;
1549 169 mohor
      end
1550 181 mohor
      if (reg_addr == 5'h4) // go out of for loop
1551
        reg_addr = 5'h3;
1552 169 mohor
      else
1553 181 mohor
        reg_addr = reg_addr - 5'h9;
1554 169 mohor
    end
1555 181 mohor
 
1556
    // set address
1557
    reg_addr = 5'h3;
1558
    // read request
1559
    #Tp mii_read_req(phy_addr, reg_addr);
1560
    check_mii_busy; // wait for read to finish
1561
    // read data
1562
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1563
    if (phy_data !== {`PHY_ID2, `MAN_MODEL_NUM, `MAN_REVISION_NUM})
1564
    begin
1565
      test_fail("Wrong data was read from PHY from ID register 2");
1566
      fail = fail + 1;
1567
    end
1568
    if(fail == 0)
1569
      test_ok;
1570
    else
1571
      fail = 0;
1572 169 mohor
  end
1573 116 mohor
 
1574
 
1575 181 mohor
  ////////////////////////////////////////////////////////////////////
1576
  ////                                                            ////
1577
  ////  Test various writings to 'real' phy registers (control    ////
1578
  ////  and non writable registers)                               ////
1579
  ////                                                            ////
1580
  ////////////////////////////////////////////////////////////////////
1581
  if (test_num == 2) // 
1582 169 mohor
  begin
1583 194 tadej
    // TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
1584
    test_name   = "TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )";
1585
    `TIME; $display("  TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )");
1586 181 mohor
 
1587
    // negate data and try to write into unwritable register
1588
    tmp_data = ~phy_data;
1589
    // write request
1590
    #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1591
    check_mii_busy; // wait for write to finish
1592 169 mohor
    // read request
1593
    #Tp mii_read_req(phy_addr, reg_addr);
1594
    check_mii_busy; // wait for read to finish
1595
    // read data
1596 181 mohor
    #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1597
    if (tmp_data !== phy_data)
1598
    begin
1599
      test_fail("Data was written into unwritable PHY register - ID register 2");
1600
      fail = fail + 1;
1601
    end
1602
 
1603
    // set address
1604
    reg_addr = 5'h0; // control register
1605
    // read request
1606
    #Tp mii_read_req(phy_addr, reg_addr);
1607
    check_mii_busy; // wait for read to finish
1608
    // read data
1609
    #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1610
    // write request
1611
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1612
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1613
    check_mii_busy; // wait for write to finish
1614
    // read request
1615
    #Tp mii_read_req(phy_addr, reg_addr);
1616
    check_mii_busy; // wait for read to finish
1617
    // read data
1618 169 mohor
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1619 181 mohor
    if (phy_data !== 16'h7DFF)
1620 169 mohor
    begin
1621 181 mohor
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1622 169 mohor
      fail = fail + 1;
1623
    end
1624 181 mohor
    // write request
1625
    #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1626
    check_mii_busy; // wait for write to finish
1627
    // read request
1628
    #Tp mii_read_req(phy_addr, reg_addr);
1629
    check_mii_busy; // wait for read to finish
1630
    // read data
1631
    #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1632
    if (phy_data !== tmp_data)
1633
    begin
1634
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1635
      fail = fail + 1;
1636
    end
1637
    if(fail == 0)
1638
      test_ok;
1639 116 mohor
    else
1640 181 mohor
      fail = 0;
1641 169 mohor
  end
1642 116 mohor
 
1643
 
1644 181 mohor
  ////////////////////////////////////////////////////////////////////
1645
  ////                                                            ////
1646
  ////  Test reset phy through mii management module              ////
1647
  ////                                                            ////
1648
  ////////////////////////////////////////////////////////////////////
1649
  if (test_num == 3) // 
1650 169 mohor
  begin
1651 194 tadej
    // TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE
1652
    test_name   = "TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE";
1653
    `TIME; $display("  TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE");
1654 181 mohor
 
1655
    // set address
1656
    reg_addr = 5'h0; // control register
1657
    // write request
1658
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1659
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1660
    check_mii_busy; // wait for write to finish
1661
    // read request
1662
    #Tp mii_read_req(phy_addr, reg_addr);
1663
    check_mii_busy; // wait for read to finish
1664
    // read data
1665
    #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1666
    if (phy_data !== tmp_data)
1667
    begin
1668
      test_fail("Data was not correctly written into OR read from writable PHY register - control register");
1669
      fail = fail + 1;
1670
    end
1671
    // set reset bit - selfclearing bit in PHY
1672
    phy_data = phy_data | 16'h8000;
1673
    // write request
1674
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1675
    check_mii_busy; // wait for write to finish
1676
    // read request
1677
    #Tp mii_read_req(phy_addr, reg_addr);
1678
    check_mii_busy; // wait for read to finish
1679
    // read data
1680
    #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1681
    // check self clearing of reset bit
1682
    if (tmp_data[15] !== 1'b0)
1683
    begin
1684
      test_fail("Reset bit should be self cleared - control register");
1685
      fail = fail + 1;
1686
    end
1687
    // check reset value of control register
1688
    if (tmp_data !== {2'h0, (`LED_CFG1 || `LED_CFG2), `LED_CFG1, 3'h0, `LED_CFG3, 8'h0})
1689
    begin
1690
      test_fail("PHY was not reset correctly AND/OR reset bit not self cleared");
1691
      fail = fail + 1;
1692
    end
1693
    if(fail == 0)
1694
      test_ok;
1695
    else
1696
      fail = 0;
1697 169 mohor
  end
1698
 
1699
 
1700 181 mohor
  ////////////////////////////////////////////////////////////////////
1701
  ////                                                            ////
1702
  ////  Test 'walking one' across phy address (with and without   ////
1703
  ////  preamble)                                                 ////
1704
  ////                                                            ////
1705
  ////////////////////////////////////////////////////////////////////
1706
  if (test_num == 4) // 
1707 169 mohor
  begin
1708 194 tadej
    // TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
1709
    test_name   = "TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1710
    `TIME; $display("  TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1711 181 mohor
 
1712
    // set PHY to test mode
1713
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1714
    for (i = 0; i <= 1; i = i + 1)
1715 169 mohor
    begin
1716 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1717
      #Tp eth_phy.clear_test_regs;
1718
      // MII mode register
1719
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1720
                wbm_subseq_waits);
1721
      // walk one across phy address
1722
      for (phy_addr = 5'h1; phy_addr > 5'h0; phy_addr = phy_addr << 1)
1723 169 mohor
      begin
1724 181 mohor
        reg_addr = $random;
1725
        tmp_data = $random;
1726
        // write request
1727
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1728
        check_mii_busy; // wait for write to finish
1729
        // read request
1730
        #Tp mii_read_req(phy_addr, reg_addr);
1731
        check_mii_busy; // wait for read to finish
1732
        // read data
1733
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1734
        #Tp;
1735
        if (phy_data !== tmp_data)
1736
        begin
1737
          if (i)
1738
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1739
          else
1740
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1741
          fail = fail + 1;
1742
        end
1743
        @(posedge wb_clk);
1744
        #Tp;
1745 169 mohor
      end
1746
    end
1747 181 mohor
    // set PHY to normal mode
1748
    #Tp eth_phy.test_regs(0);
1749
    #Tp eth_phy.preamble_suppresed(0);
1750
    // MII mode register
1751
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1752
    if(fail == 0)
1753
      test_ok;
1754
    else
1755
      fail = 0;
1756 169 mohor
  end
1757
 
1758
 
1759 181 mohor
  ////////////////////////////////////////////////////////////////////
1760
  ////                                                            ////
1761
  ////  Test 'walking one' across phy's register address (with    ////
1762
  ////  and without preamble)                                     ////
1763
  ////                                                            ////
1764
  ////////////////////////////////////////////////////////////////////
1765
  if (test_num == 5) // 
1766 169 mohor
  begin
1767 194 tadej
    // TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
1768
    test_name   = "TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )";
1769
    `TIME; $display("  TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )");
1770 181 mohor
 
1771
    // set PHY to test mode
1772
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1773
    for (i = 0; i <= 1; i = i + 1)
1774 169 mohor
    begin
1775 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1776
      #Tp eth_phy.clear_test_regs;
1777
      // MII mode register
1778
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1779
                wbm_subseq_waits);
1780
      // walk one across reg address
1781
      for (reg_addr = 5'h1; reg_addr > 5'h0; reg_addr = reg_addr << 1)
1782 169 mohor
      begin
1783 181 mohor
        phy_addr = $random;
1784
        tmp_data = $random;
1785
        // write request
1786
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1787
        check_mii_busy; // wait for write to finish
1788
        // read request
1789
        #Tp mii_read_req(phy_addr, reg_addr);
1790
        check_mii_busy; // wait for read to finish
1791
        // read data
1792
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1793
        #Tp;
1794
        if (phy_data !== tmp_data)
1795
        begin
1796
          if (i)
1797
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1798
          else
1799
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1800
          fail = fail + 1;
1801
        end
1802
        @(posedge wb_clk);
1803
        #Tp;
1804 169 mohor
      end
1805
    end
1806 181 mohor
    // set PHY to normal mode
1807
    #Tp eth_phy.test_regs(0);
1808
    #Tp eth_phy.preamble_suppresed(0);
1809
    // MII mode register
1810
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1811
    if(fail == 0)
1812
      test_ok;
1813
    else
1814
      fail = 0;
1815 169 mohor
  end
1816
 
1817
 
1818 181 mohor
  ////////////////////////////////////////////////////////////////////
1819
  ////                                                            ////
1820
  ////  Test 'walking one' across phy's data (with and without    ////
1821
  ////  preamble)                                                 ////
1822
  ////                                                            ////
1823
  ////////////////////////////////////////////////////////////////////
1824
  if (test_num == 6) // 
1825 169 mohor
  begin
1826 194 tadej
    // TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
1827
    test_name   = "TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )";
1828
    `TIME; $display("  TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )");
1829 181 mohor
 
1830
    // set PHY to test mode
1831
    #Tp eth_phy.test_regs(1); // set test registers (wholy writable registers) and respond to all PHY addresses
1832
    for (i = 0; i <= 1; i = i + 1)
1833 169 mohor
    begin
1834 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
1835
      #Tp eth_phy.clear_test_regs;
1836
      // MII mode register
1837
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}), 4'hF, 1, wbm_init_waits,
1838
                wbm_subseq_waits);
1839
      // walk one across data
1840
      for (tmp_data = 16'h1; tmp_data > 16'h0; tmp_data = tmp_data << 1)
1841 169 mohor
      begin
1842 181 mohor
        phy_addr = $random;
1843
        reg_addr = $random;
1844
        // write request
1845
        #Tp mii_write_req(phy_addr, reg_addr, tmp_data);
1846
        check_mii_busy; // wait for write to finish
1847
        // read request
1848
        #Tp mii_read_req(phy_addr, reg_addr);
1849
        check_mii_busy; // wait for read to finish
1850
        // read data
1851
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1852
        #Tp;
1853
        if (phy_data !== tmp_data)
1854
        begin
1855
          if (i)
1856
            test_fail("Data was not correctly written into OR read from test registers (without preamble)");
1857
          else
1858
            test_fail("Data was not correctly written into OR read from test registers (with preamble)");
1859
          fail = fail + 1;
1860
        end
1861
        @(posedge wb_clk);
1862
        #Tp;
1863 169 mohor
      end
1864
    end
1865 181 mohor
    // set PHY to normal mode
1866
    #Tp eth_phy.test_regs(0);
1867
    #Tp eth_phy.preamble_suppresed(0);
1868
    // MII mode register
1869
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1870
    if(fail == 0)
1871
      test_ok;
1872
    else
1873
      fail = 0;
1874 169 mohor
  end
1875
 
1876
 
1877 181 mohor
  ////////////////////////////////////////////////////////////////////
1878
  ////                                                            ////
1879
  ////  Test reading from phy with wrong phy address (host        ////
1880
  ////  reading high 'z' data)                                    ////
1881
  ////                                                            ////
1882
  ////////////////////////////////////////////////////////////////////
1883
  if (test_num == 7) // 
1884 169 mohor
  begin
1885 194 tadej
    // TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
1886
    test_name   = "TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )";
1887
    `TIME; $display("  TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )");
1888 181 mohor
 
1889
    phy_addr = 5'h2; // wrong PHY address
1890
    // read request
1891
    #Tp mii_read_req(phy_addr, reg_addr);
1892
    check_mii_busy; // wait for read to finish
1893
    // read data
1894
    $display("  => Two errors will be displayed from WB Bus Monitor, because correct HIGH Z data was read");
1895
    #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1896
    if (tmp_data !== 16'hzzzz)
1897
    begin
1898
      test_fail("Data was read from PHY register with wrong PHY address - control register");
1899
      fail = fail + 1;
1900
    end
1901
    if(fail == 0)
1902
      test_ok;
1903
    else
1904
      fail = 0;
1905 169 mohor
  end
1906
 
1907
 
1908 181 mohor
  ////////////////////////////////////////////////////////////////////
1909
  ////                                                            ////
1910
  ////  Test writing to phy with wrong phy address and reading    ////
1911
  ////  from correct one                                          ////
1912
  ////                                                            ////
1913
  ////////////////////////////////////////////////////////////////////
1914
  if (test_num == 8) // 
1915 169 mohor
  begin
1916 194 tadej
    // TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
1917
    test_name   = "TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE";
1918
    `TIME; $display("  TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE");
1919 181 mohor
 
1920
    // set address
1921
    reg_addr = 5'h0; // control register
1922
    phy_addr = 5'h2; // wrong PHY address
1923
    // write request
1924
    phy_data = 16'h7DFF; // bit 15 (RESET bit) and bit 9 are self clearing bits
1925
    #Tp mii_write_req(phy_addr, reg_addr, phy_data);
1926
    check_mii_busy; // wait for write to finish
1927
 
1928
    phy_addr = 5'h1; // correct PHY address
1929
    // read request
1930
    #Tp mii_read_req(phy_addr, reg_addr);
1931
    check_mii_busy; // wait for read to finish
1932
    // read data
1933
    #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1934
    if (phy_data === tmp_data)
1935
    begin
1936
      test_fail("Data was written into PHY register with wrong PHY address - control register");
1937
      fail = fail + 1;
1938
    end
1939
    if(fail == 0)
1940
      test_ok;
1941
    else
1942
      fail = 0;
1943 169 mohor
  end
1944
 
1945
 
1946 181 mohor
  ////////////////////////////////////////////////////////////////////
1947
  ////                                                            ////
1948
  ////  Test sliding stop scan command immediately after read     ////
1949
  ////  request (with and without preamble)                       ////
1950
  ////                                                            ////
1951
  ////////////////////////////////////////////////////////////////////
1952
  if (test_num == 9) // 
1953 169 mohor
  begin
1954 194 tadej
    // TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
1955
    test_name = "TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )";
1956 181 mohor
    `TIME;
1957 194 tadej
    $display("  TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )");
1958 181 mohor
 
1959
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
1960 169 mohor
    begin
1961 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
1962
      // MII mode register
1963
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
1964
               wbm_subseq_waits);
1965
      i = 0;
1966
      cnt = 0;
1967
      while (i < 80) // delay for sliding of writing a STOP SCAN command
1968 169 mohor
      begin
1969 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after read will be finished
1970
        begin
1971
          // set address
1972
          reg_addr = 5'h0; // control register
1973
          phy_addr = 5'h1; // correct PHY address
1974
          cnt = 0;
1975
          // read request
1976
          #Tp mii_read_req(phy_addr, reg_addr);
1977
          fork
1978
            begin
1979
              repeat(i) @(posedge Mdc_O);
1980
              // write command 0x0 into MII command register
1981
              // MII command written while read in progress
1982
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
1983
              @(posedge wb_clk);
1984
              #Tp check_mii_busy; // wait for read to finish
1985
            end
1986
            begin
1987
              // wait for serial bus to become active
1988
              wait(Mdio_IO !== 1'bz);
1989
              // count transfer length
1990
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
1991
              begin
1992
                @(posedge Mdc_O);
1993
                #Tp cnt = cnt + 1;
1994
              end
1995
            end
1996
          join
1997
          // check transfer length
1998
          if (i2) // without preamble
1999 169 mohor
          begin
2000 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2001
            begin
2002
              test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
2003
              fail = fail + 1;
2004
            end
2005 169 mohor
          end
2006 181 mohor
          else // with preamble
2007 169 mohor
          begin
2008 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2009
            begin
2010
              test_fail("Read request did not proceed correctly, while SCAN STOP command was written");
2011
              fail = fail + 1;
2012
            end
2013
          end
2014
          // check the BUSY signal to see if the bus is still IDLE
2015
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
2016
            check_mii_busy; // wait for bus to become idle
2017
 
2018
          // try normal write or read after read was finished
2019
          #Tp phy_data = {8'h7D, (i[7:0] + 1)};
2020
          #Tp cnt = 0;
2021
          if (i3 == 0) // write after read
2022
          begin
2023
            // write request
2024
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2025 169 mohor
            // wait for serial bus to become active
2026
            wait(Mdio_IO !== 1'bz);
2027
            // count transfer length
2028 181 mohor
            while(Mdio_IO !== 1'bz)
2029 169 mohor
            begin
2030
              @(posedge Mdc_O);
2031
              #Tp cnt = cnt + 1;
2032
            end
2033 181 mohor
            @(posedge Mdc_O);
2034
            // read request
2035
            #Tp mii_read_req(phy_addr, reg_addr);
2036
            check_mii_busy; // wait for read to finish
2037
            // read and check data
2038
            #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2039
            if (phy_data !== tmp_data)
2040
            begin
2041
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2042
              fail = fail + 1;
2043
            end
2044 169 mohor
          end
2045 181 mohor
          else // read after read
2046 169 mohor
          begin
2047 181 mohor
            // read request
2048
            #Tp mii_read_req(phy_addr, reg_addr);
2049
            // wait for serial bus to become active
2050
            wait(Mdio_IO !== 1'bz);
2051
            // count transfer length
2052
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2053
            begin
2054
              @(posedge Mdc_O);
2055
              #Tp cnt = cnt + 1;
2056
            end
2057 169 mohor
            @(posedge Mdc_O);
2058 181 mohor
            check_mii_busy; // wait for read to finish
2059
            // read and check data
2060
            #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2061
            if (phy_data !== tmp_data)
2062
            begin
2063
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2064
              fail = fail + 1;
2065
            end
2066 169 mohor
          end
2067 181 mohor
          // check if transfer was a proper length
2068
          if (i2) // without preamble
2069 169 mohor
          begin
2070 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2071
            begin
2072
              test_fail("New request did not proceed correctly, after read request");
2073
              fail = fail + 1;
2074
            end
2075 169 mohor
          end
2076 181 mohor
          else // with preamble
2077 169 mohor
          begin
2078 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2079
            begin
2080
              test_fail("New request did not proceed correctly, after read request");
2081
              fail = fail + 1;
2082
            end
2083 169 mohor
          end
2084
        end
2085 181 mohor
        #Tp;
2086
        // set delay of writing the command
2087 169 mohor
        if (i2) // without preamble
2088
        begin
2089 181 mohor
          case(i)
2090
            0, 1:               i = i + 1;
2091
            18, 19, 20, 21, 22,
2092
            23, 24, 25, 26, 27,
2093
            28, 29, 30, 31, 32,
2094
            33, 34, 35:         i = i + 1;
2095
            36:                 i = 80;
2096
            default:            i = 18;
2097
          endcase
2098 169 mohor
        end
2099
        else // with preamble
2100
        begin
2101 181 mohor
          case(i)
2102
            0, 1:               i = i + 1;
2103
            50, 51, 52, 53, 54,
2104
            55, 56, 57, 58, 59,
2105
            60, 61, 62, 63, 64,
2106
            65, 66, 67:         i = i + 1;
2107
            68:                 i = 80;
2108
            default:            i = 50;
2109
          endcase
2110 169 mohor
        end
2111 181 mohor
        @(posedge wb_clk);
2112 169 mohor
      end
2113
    end
2114 181 mohor
    // set PHY to normal mode
2115
    #Tp eth_phy.preamble_suppresed(0);
2116
    // MII mode register
2117
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2118
    if(fail == 0)
2119
      test_ok;
2120
    else
2121
      fail = 0;
2122 169 mohor
  end
2123
 
2124
 
2125 181 mohor
  ////////////////////////////////////////////////////////////////////
2126
  ////                                                            ////
2127
  ////  Test sliding stop scan command immediately after write    ////
2128
  ////  request (with and without preamble)                       ////
2129
  ////                                                            ////
2130
  ////////////////////////////////////////////////////////////////////
2131
  if (test_num == 10) // 
2132 169 mohor
  begin
2133 194 tadej
    // TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
2134
    test_name = "TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )";
2135 181 mohor
    `TIME;
2136 194 tadej
    $display("  TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )");
2137 181 mohor
 
2138
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
2139 169 mohor
    begin
2140 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
2141
      // MII mode register
2142
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
2143
                wbm_subseq_waits);
2144
      i = 0;
2145
      cnt = 0;
2146
      while (i < 80) // delay for sliding of writing a STOP SCAN command
2147 169 mohor
      begin
2148 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after write will be finished
2149
        begin
2150
          // set address
2151
          reg_addr = 5'h0; // control register
2152
          phy_addr = 5'h1; // correct PHY address
2153
          cnt = 0;
2154
          // write request
2155
          phy_data = {8'h75, (i[7:0] + 1)};
2156
          #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2157
          fork
2158
            begin
2159
              repeat(i) @(posedge Mdc_O);
2160
              // write command 0x0 into MII command register
2161
              // MII command written while read in progress
2162
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2163
              @(posedge wb_clk);
2164
              #Tp check_mii_busy; // wait for write to finish
2165
            end
2166
            begin
2167
              // wait for serial bus to become active
2168
              wait(Mdio_IO !== 1'bz);
2169
              // count transfer length
2170
              while(Mdio_IO !== 1'bz)
2171
              begin
2172
                @(posedge Mdc_O);
2173
                #Tp cnt = cnt + 1;
2174
              end
2175
            end
2176
          join
2177
          // check transfer length
2178
          if (i2) // without preamble
2179 169 mohor
          begin
2180 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2181
            begin
2182
              test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2183
              fail = fail + 1;
2184
            end
2185 169 mohor
          end
2186 181 mohor
          else // with preamble
2187 169 mohor
          begin
2188 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2189
            begin
2190
              test_fail("Write request did not proceed correctly, while SCAN STOP command was written");
2191
              fail = fail + 1;
2192
            end
2193
          end
2194
          // check the BUSY signal to see if the bus is still IDLE
2195
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
2196
            check_mii_busy; // wait for bus to become idle
2197
 
2198
          // try normal write or read after write was finished
2199
          #Tp cnt = 0;
2200
          if (i3 == 0) // write after write
2201
          begin
2202
            phy_data = {8'h7A, (i[7:0] + 1)};
2203
            // write request
2204
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
2205 169 mohor
            // wait for serial bus to become active
2206
            wait(Mdio_IO !== 1'bz);
2207
            // count transfer length
2208
            while(Mdio_IO !== 1'bz)
2209
            begin
2210
              @(posedge Mdc_O);
2211
              #Tp cnt = cnt + 1;
2212
            end
2213 181 mohor
            @(posedge Mdc_O);
2214
            // read request
2215
            #Tp mii_read_req(phy_addr, reg_addr);
2216
            check_mii_busy; // wait for read to finish
2217
            // read and check data
2218
            #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2219
            if (phy_data !== tmp_data)
2220
            begin
2221
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2222
              fail = fail + 1;
2223
            end
2224 169 mohor
          end
2225 181 mohor
          else // read after write
2226 169 mohor
          begin
2227 181 mohor
            // read request
2228
            #Tp mii_read_req(phy_addr, reg_addr);
2229
            // wait for serial bus to become active
2230
            wait(Mdio_IO !== 1'bz);
2231
            // count transfer length
2232
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
2233
            begin
2234
              @(posedge Mdc_O);
2235
              #Tp cnt = cnt + 1;
2236
            end
2237 169 mohor
            @(posedge Mdc_O);
2238 181 mohor
            check_mii_busy; // wait for read to finish
2239
            // read and check data
2240
            #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data , 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2241
            if (phy_data !== tmp_data)
2242
            begin
2243
              test_fail("Data was not correctly written into OR read from PHY register - control register");
2244
              fail = fail + 1;
2245
            end
2246 169 mohor
          end
2247 181 mohor
          // check if transfer was a proper length
2248
          if (i2) // without preamble
2249 169 mohor
          begin
2250 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
2251
            begin
2252
              test_fail("New request did not proceed correctly, after write request");
2253
              fail = fail + 1;
2254
            end
2255 169 mohor
          end
2256 181 mohor
          else // with preamble
2257 169 mohor
          begin
2258 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
2259
            begin
2260
              test_fail("New request did not proceed correctly, after write request");
2261
              fail = fail + 1;
2262
            end
2263 169 mohor
          end
2264
        end
2265 181 mohor
        #Tp;
2266
        // set delay of writing the command
2267 169 mohor
        if (i2) // without preamble
2268
        begin
2269 181 mohor
          case(i)
2270
            0, 1:               i = i + 1;
2271
            18, 19, 20, 21, 22,
2272
            23, 24, 25, 26, 27,
2273
            28, 29, 30, 31, 32,
2274
            33, 34, 35:         i = i + 1;
2275
            36:                 i = 80;
2276
            default:            i = 18;
2277
          endcase
2278 169 mohor
        end
2279
        else // with preamble
2280
        begin
2281 181 mohor
          case(i)
2282
            0, 1:               i = i + 1;
2283
            50, 51, 52, 53, 54,
2284
            55, 56, 57, 58, 59,
2285
            60, 61, 62, 63, 64,
2286
            65, 66, 67:         i = i + 1;
2287
            68:                 i = 80;
2288
            default:            i = 50;
2289
          endcase
2290 169 mohor
        end
2291 181 mohor
        @(posedge wb_clk);
2292 169 mohor
      end
2293
    end
2294 181 mohor
    // set PHY to normal mode
2295
    #Tp eth_phy.preamble_suppresed(0);
2296
    // MII mode register
2297
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2298
    if(fail == 0)
2299
      test_ok;
2300
    else
2301
      fail = 0;
2302 169 mohor
  end
2303
 
2304
 
2305 181 mohor
  ////////////////////////////////////////////////////////////////////
2306
  ////                                                            ////
2307
  ////  Test busy and nvalid status durations during write (with  ////
2308
  ////  and without preamble)                                     ////
2309
  ////                                                            ////
2310
  ////////////////////////////////////////////////////////////////////
2311
  if (test_num == 11) // 
2312 169 mohor
  begin
2313 194 tadej
    // TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
2314
    test_name   = "TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )";
2315
    `TIME; $display("  TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )");
2316 181 mohor
 
2317
    reset_mii; // reset MII
2318
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2319
    #Tp eth_phy.link_up_down(1);
2320
    // set the MII
2321
    clk_div = 64;
2322
    mii_set_clk_div(clk_div[7:0]);
2323
    // set address
2324
    reg_addr = 5'h1; // status register
2325
    phy_addr = 5'h1; // correct PHY address
2326
 
2327
    for (i = 0; i <= 1; i = i + 1)
2328 169 mohor
    begin
2329 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2330
      // MII mode register
2331
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2332
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2333
      @(posedge Mdc_O);
2334
      // write request
2335
      #Tp mii_write_req(phy_addr, reg_addr, 16'h5A5A);
2336
      // read data from MII status register - Busy and Nvalid bits
2337
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2338
 
2339
      // check MII IO signal and Busy and Nvalid bits
2340
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2341 169 mohor
      begin
2342 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2343
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2344
        begin
2345
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2346
          fail = fail + 1;
2347
        end
2348
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2349
        begin
2350
          test_fail("Nvalid signal was set during write");
2351
          fail = fail + 1;
2352
        end
2353 169 mohor
      end
2354 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2355 169 mohor
      begin
2356 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2357
        begin
2358
          test_fail("Busy signal should be set after write, due to reads from MII status register");
2359
          fail = fail + 1;
2360
        end
2361
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2362
        begin
2363
          test_fail("Nvalid signal was set during write");
2364
          fail = fail + 1;
2365
        end
2366 169 mohor
      end
2367 181 mohor
 
2368
      // wait for serial bus to become active
2369
      wait(Mdio_IO !== 1'bz);
2370
      // count transfer bits
2371
      if (i)
2372 169 mohor
      begin
2373 181 mohor
        repeat(32) @(posedge Mdc_O);
2374 169 mohor
      end
2375 181 mohor
      else
2376 169 mohor
      begin
2377 181 mohor
        repeat(64) @(posedge Mdc_O);
2378 169 mohor
      end
2379 181 mohor
      // read data from MII status register - Busy and Nvalid bits
2380
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2381
 
2382
      // check MII IO signal and Busy and Nvalid bits
2383
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2384 169 mohor
      begin
2385 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2386
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2387
        begin
2388
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2389
          fail = fail + 1;
2390
        end
2391
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2392
        begin
2393
          test_fail("Nvalid signal was set during write");
2394
          fail = fail + 1;
2395
        end
2396 169 mohor
      end
2397 181 mohor
      else // Busy bit should still be set to '1'
2398 169 mohor
      begin
2399 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2400
        begin
2401
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2402
          fail = fail + 1;
2403
        end
2404
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2405
        begin
2406
          test_fail("Nvalid signal was set during write");
2407
          fail = fail + 1;
2408
        end
2409 169 mohor
      end
2410 181 mohor
 
2411
      // wait for next negative clock edge
2412
      @(negedge Mdc_O);
2413 169 mohor
      // read data from MII status register - Busy and Nvalid bits
2414
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2415 181 mohor
 
2416 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2417
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2418
      begin
2419
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2420
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2421
        begin
2422
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2423
          fail = fail + 1;
2424
        end
2425
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2426
        begin
2427
          test_fail("Nvalid signal was set during write");
2428
          fail = fail + 1;
2429
        end
2430
      end
2431 181 mohor
      else // Busy bit should still be set to '1'
2432 169 mohor
      begin
2433
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2434
        begin
2435 181 mohor
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2436
          fail = fail + 1;
2437 169 mohor
        end
2438 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2439 169 mohor
        begin
2440 181 mohor
          test_fail("Nvalid signal was set during write");
2441
          fail = fail + 1;
2442
        end
2443
      end
2444
 
2445
      // wait for Busy to become inactive
2446
      i1 = 0;
2447
      while (i1 <= 2)
2448
      begin
2449
        // wait for next positive clock edge
2450
        @(posedge Mdc_O);
2451
        // read data from MII status register - Busy and Nvalid bits
2452
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2453
 
2454
        // check MII IO signal and Busy and Nvalid bits
2455
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2456
        begin
2457
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2458
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2459 169 mohor
          begin
2460 181 mohor
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2461 169 mohor
            fail = fail + 1;
2462
          end
2463 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2464
          begin
2465
            test_fail("Nvalid signal was set during write");
2466
            fail = fail + 1;
2467
          end
2468 169 mohor
        end
2469 181 mohor
        else // wait for Busy bit to be set to '0'
2470 169 mohor
        begin
2471 181 mohor
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2472
          begin
2473
            i1 = 3; // end of Busy checking
2474
          end
2475
          else
2476
          begin
2477
            if (i1 == 2)
2478
            begin
2479
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2480
              fail = fail + 1;
2481
            end
2482
            #Tp i1 = i1 + 1;
2483
          end
2484
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2485
          begin
2486
            test_fail("Nvalid signal was set after write");
2487
            fail = fail + 1;
2488
          end
2489 169 mohor
        end
2490
      end
2491
    end
2492 181 mohor
    // set PHY to normal mode
2493
    #Tp eth_phy.preamble_suppresed(0);
2494
    // MII mode register
2495
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2496
    if(fail == 0)
2497
      test_ok;
2498
    else
2499
      fail = 0;
2500 116 mohor
  end
2501
 
2502
 
2503 181 mohor
  ////////////////////////////////////////////////////////////////////
2504
  ////                                                            ////
2505
  ////  Test busy and nvalid status durations during write (with  ////
2506
  ////  and without preamble)                                     ////
2507
  ////                                                            ////
2508
  ////////////////////////////////////////////////////////////////////
2509
  if (test_num == 12) // 
2510 169 mohor
  begin
2511 194 tadej
    // TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
2512
    test_name   = "TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )";
2513
    `TIME; $display("  TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )");
2514 181 mohor
 
2515
    reset_mii; // reset MII
2516
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2517
    #Tp eth_phy.link_up_down(1);
2518
    // set the MII
2519
    clk_div = 64;
2520
    mii_set_clk_div(clk_div[7:0]);
2521
    // set address
2522
    reg_addr = 5'h1; // status register
2523
    phy_addr = 5'h1; // correct PHY address
2524
 
2525
    for (i = 0; i <= 1; i = i + 1)
2526 169 mohor
    begin
2527 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2528
      // MII mode register
2529
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2530
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2531 169 mohor
      @(posedge Mdc_O);
2532 181 mohor
      // read request
2533
      #Tp mii_read_req(phy_addr, reg_addr);
2534 169 mohor
      // read data from MII status register - Busy and Nvalid bits
2535
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2536 181 mohor
 
2537 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2538
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2539
      begin
2540 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2541 169 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2542
        begin
2543 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2544 169 mohor
          fail = fail + 1;
2545
        end
2546
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2547
        begin
2548
          test_fail("Nvalid signal was set during read");
2549
          fail = fail + 1;
2550
        end
2551
      end
2552 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2553 169 mohor
      begin
2554
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2555
        begin
2556 181 mohor
          test_fail("Busy signal should be set after read, due to reads from MII status register");
2557
          fail = fail + 1;
2558 169 mohor
        end
2559
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2560
        begin
2561 181 mohor
          test_fail("Nvalid signal was set during read");
2562 169 mohor
          fail = fail + 1;
2563
        end
2564
      end
2565 181 mohor
 
2566
      // wait for serial bus to become active
2567
      wait(Mdio_IO !== 1'bz);
2568
      // count transfer bits
2569
      if (i)
2570 169 mohor
      begin
2571 181 mohor
        repeat(31) @(posedge Mdc_O);
2572 169 mohor
      end
2573 181 mohor
      else
2574 169 mohor
      begin
2575 181 mohor
        repeat(63) @(posedge Mdc_O);
2576 169 mohor
      end
2577 181 mohor
      // wait for next negative clock edge
2578
      @(negedge Mdc_O);
2579
      // read data from MII status register - Busy and Nvalid bits
2580
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2581
 
2582
      // check MII IO signal and Busy and Nvalid bits
2583
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2584 169 mohor
      begin
2585 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2586
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2587
        begin
2588
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2589
          fail = fail + 1;
2590
        end
2591
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2592
        begin
2593
          test_fail("Nvalid signal was set during read");
2594
          fail = fail + 1;
2595
        end
2596 169 mohor
      end
2597 181 mohor
      else // Busy bit should still be set to '1'
2598 169 mohor
      begin
2599 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2600
        begin
2601
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2602
          fail = fail + 1;
2603
        end
2604
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2605
        begin
2606
          test_fail("Nvalid signal was set during read");
2607
          fail = fail + 1;
2608
        end
2609 169 mohor
      end
2610 181 mohor
 
2611 169 mohor
      // wait for next positive clock edge
2612
      @(posedge Mdc_O);
2613
      // read data from MII status register - Busy and Nvalid bits
2614
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2615 181 mohor
 
2616 169 mohor
      // check MII IO signal and Busy and Nvalid bits
2617
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2618
      begin
2619
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2620 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2621 169 mohor
        begin
2622 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2623
          fail = fail + 1;
2624
        end
2625
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2626
        begin
2627
          test_fail("Nvalid signal was set during read");
2628
          fail = fail + 1;
2629
        end
2630
      end
2631
      else // Busy bit should still be set to '1'
2632
      begin
2633
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2634
        begin
2635
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2636
          fail = fail + 1;
2637
        end
2638
        if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2639
        begin
2640
          test_fail("Nvalid signal was set during read");
2641
          fail = fail + 1;
2642
        end
2643
      end
2644
 
2645
      // wait for Busy to become inactive
2646
      i1 = 0;
2647
      while (i1 <= 2)
2648
      begin
2649
        // wait for next positive clock edge
2650
        @(posedge Mdc_O);
2651
        // read data from MII status register - Busy and Nvalid bits
2652
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2653
 
2654
        // check MII IO signal and Busy and Nvalid bits
2655
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2656
        begin
2657
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2658 169 mohor
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2659
          begin
2660
            test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2661
            fail = fail + 1;
2662
          end
2663 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2664 169 mohor
          begin
2665 181 mohor
            test_fail("Nvalid signal was set during read");
2666 169 mohor
            fail = fail + 1;
2667
          end
2668
        end
2669 181 mohor
        else // wait for Busy bit to be set to '0'
2670 169 mohor
        begin
2671
          if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2672
          begin
2673
            i1 = 3; // end of Busy checking
2674
          end
2675
          else
2676
          begin
2677
            if (i1 == 2)
2678
            begin
2679
              test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2680
              fail = fail + 1;
2681
            end
2682
            #Tp i1 = i1 + 1;
2683
          end
2684 181 mohor
          if (phy_data[`ETH_MIISTATUS_NVALID] !== 1'b0)
2685 169 mohor
          begin
2686 181 mohor
            test_fail("Nvalid signal was set after read");
2687 169 mohor
            fail = fail + 1;
2688
          end
2689
        end
2690
      end
2691
    end
2692 181 mohor
    // set PHY to normal mode
2693
    #Tp eth_phy.preamble_suppresed(0);
2694
    // MII mode register
2695
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2696
    if(fail == 0)
2697
      test_ok;
2698
    else
2699
      fail = 0;
2700 169 mohor
  end
2701
 
2702
 
2703 181 mohor
  ////////////////////////////////////////////////////////////////////
2704
  ////                                                            ////
2705
  ////  Test busy and nvalid status durations during scan (with   ////
2706
  ////  and without preamble)                                     ////
2707
  ////                                                            ////
2708
  ////////////////////////////////////////////////////////////////////
2709
  if (test_num == 13) // 
2710 169 mohor
  begin
2711 194 tadej
    // TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
2712
    test_name   = "TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )";
2713
    `TIME; $display("  TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )");
2714 181 mohor
 
2715
    reset_mii; // reset MII
2716
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2717
    #Tp eth_phy.link_up_down(1);
2718
    // set the MII
2719
    clk_div = 64;
2720
    mii_set_clk_div(clk_div[7:0]);
2721
    // set address
2722
    reg_addr = 5'h1; // status register
2723
    phy_addr = 5'h1; // correct PHY address
2724
 
2725
    for (i = 0; i <= 1; i = i + 1)
2726 169 mohor
    begin
2727 181 mohor
      #Tp eth_phy.preamble_suppresed(i);
2728
      // MII mode register
2729
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2730
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2731
      @(posedge Mdc_O);
2732
      // scan request
2733
      #Tp mii_scan_req(phy_addr, reg_addr);
2734
      // read data from MII status register - Busy and Nvalid bits
2735
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2736
 
2737
      // check MII IO signal and Busy and Nvalid bits
2738
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2739 169 mohor
      begin
2740 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is not HIGH Z - set higher clock divider");
2741
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2742
        begin
2743
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2744
          fail = fail + 1;
2745
        end
2746
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2747
        begin
2748
          test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z anymore - 1. read");
2749
          fail = fail + 1;
2750
        end
2751 169 mohor
      end
2752 181 mohor
      else // Busy bit should already be set to '1', due to reads from MII status register
2753 169 mohor
      begin
2754 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2755
        begin
2756
          test_fail("Busy signal should be set after scan, due to reads from MII status register");
2757
          fail = fail + 1;
2758
        end
2759
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2760
        begin
2761
          test_fail("Nvalid signal should be set after scan, due to reads from MII status register");
2762
          fail = fail + 1;
2763
        end
2764 169 mohor
      end
2765 181 mohor
 
2766
      // wait for serial bus to become active
2767 169 mohor
      wait(Mdio_IO !== 1'bz);
2768 181 mohor
      // count transfer bits
2769
      if (i)
2770 169 mohor
      begin
2771 181 mohor
        repeat(21) @(posedge Mdc_O);
2772 169 mohor
      end
2773 181 mohor
      else
2774 169 mohor
      begin
2775 181 mohor
        repeat(53) @(posedge Mdc_O);
2776 169 mohor
      end
2777 181 mohor
      // stop scan
2778
      #Tp mii_scan_finish; // finish scan operation
2779
 
2780
      // wait for next positive clock edge
2781
      repeat(10) @(posedge Mdc_O);
2782
      // read data from MII status register - Busy and Nvalid bits
2783
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2784
 
2785
      // check MII IO signal and Busy and Nvalid bits
2786
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2787 169 mohor
      begin
2788 181 mohor
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2789
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2790 169 mohor
        begin
2791 181 mohor
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2792 169 mohor
          fail = fail + 1;
2793
        end
2794 181 mohor
        // Nvalid signal can be cleared here - it is still Testbench error
2795 169 mohor
      end
2796 181 mohor
      else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2797 169 mohor
      begin
2798 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2799 169 mohor
        begin
2800 181 mohor
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2801 169 mohor
          fail = fail + 1;
2802
        end
2803 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2804 169 mohor
        begin
2805 181 mohor
          test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2806 169 mohor
          fail = fail + 1;
2807
        end
2808 181 mohor
      end
2809
 
2810
      // wait for next negative clock edge
2811
      @(negedge Mdc_O);
2812
      // read data from MII status register - Busy and Nvalid bits
2813
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2814
 
2815
      // check MII IO signal and Busy and Nvalid bits
2816
      if (Mdio_IO === 1'bz) // Mdio_IO should not be HIGH Z here - testbench selfcheck
2817
      begin
2818
        test_fail("Testbench error - read was to late, Mdio_IO is HIGH Z - set higher clock divider");
2819
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2820 169 mohor
        begin
2821 181 mohor
          test_fail("Busy signal should be set while MII IO signal is not active anymore");
2822
          fail = fail + 1;
2823 169 mohor
        end
2824 181 mohor
        // Nvalid signal can be cleared here - it is still Testbench error
2825 169 mohor
      end
2826 181 mohor
      else // Busy bit should still be set to '1', Nvalid bit should still be set to '1'
2827 169 mohor
      begin
2828 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2829 169 mohor
        begin
2830 181 mohor
          test_fail("Busy signal should be set while MII IO signal not HIGH Z");
2831
          fail = fail + 1;
2832 169 mohor
        end
2833 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2834 169 mohor
        begin
2835 181 mohor
          test_fail("Nvalid signal should be set while MII IO signal not HIGH Z");
2836
          fail = fail + 1;
2837 169 mohor
        end
2838
      end
2839 181 mohor
 
2840
      // wait for next negative clock edge
2841
      @(posedge Mdc_O);
2842
      // read data from MII status register - Busy and Nvalid bits
2843 169 mohor
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2844 181 mohor
 
2845
      // check MII IO signal and Busy and Nvalid bits
2846
      if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2847 169 mohor
      begin
2848 181 mohor
        test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2849
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2850 169 mohor
        begin
2851 181 mohor
          test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2852 169 mohor
          fail = fail + 1;
2853
        end
2854 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2855 169 mohor
        begin
2856 181 mohor
          test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2857 169 mohor
          fail = fail + 1;
2858
        end
2859
      end
2860 181 mohor
      else // Busy bit should still be set to '1', Nvalid bit can be set to '0'
2861 169 mohor
      begin
2862 181 mohor
        if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2863 169 mohor
        begin
2864 181 mohor
          test_fail("Busy signal should be set after MII IO signal become HIGH Z");
2865
          fail = fail + 1;
2866 169 mohor
        end
2867 181 mohor
        if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2868 169 mohor
        begin
2869 181 mohor
          i2 = 1; // check finished
2870 169 mohor
        end
2871 181 mohor
        else
2872 169 mohor
        begin
2873 181 mohor
          i2 = 0; // check must continue
2874 169 mohor
        end
2875
      end
2876 181 mohor
 
2877
      // wait for Busy to become inactive
2878
      i1 = 0;
2879
      while ((i1 <= 2) || (i2 == 0))
2880
      begin
2881
        // wait for next positive clock edge
2882
        @(posedge Mdc_O);
2883
        // read data from MII status register - Busy and Nvalid bits
2884
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2885
 
2886
        // check MII IO signal and Busy and Nvalid bits
2887
        if (Mdio_IO !== 1'bz) // Mdio_IO should be HIGH Z here - testbench selfcheck
2888 169 mohor
        begin
2889 181 mohor
          test_fail("Testbench error - read was to early, Mdio_IO is not HIGH Z - set higher clock divider");
2890
          if (i1 <= 2)
2891 169 mohor
          begin
2892 181 mohor
            if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2893 169 mohor
            begin
2894 181 mohor
              test_fail("Busy signal was not set while MII IO signal is not HIGH Z");
2895 169 mohor
              fail = fail + 1;
2896
            end
2897
          end
2898 181 mohor
          if (i2 == 0)
2899 169 mohor
          begin
2900 181 mohor
            if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2901 169 mohor
            begin
2902 181 mohor
              test_fail("Nvalid signal was not set while MII IO signal is not HIGH Z");
2903 169 mohor
              fail = fail + 1;
2904
            end
2905
          end
2906
        end
2907 181 mohor
        else // wait for Busy bit to be set to '0'
2908 169 mohor
        begin
2909 181 mohor
          if (i1 <= 2)
2910 169 mohor
          begin
2911 181 mohor
            if (phy_data[`ETH_MIISTATUS_BUSY] === 1'b0)
2912 169 mohor
            begin
2913 181 mohor
              i1 = 3; // end of Busy checking
2914 169 mohor
            end
2915 181 mohor
            else
2916 169 mohor
            begin
2917 181 mohor
              if (i1 == 2)
2918 169 mohor
              begin
2919 181 mohor
                test_fail("Busy signal should be cleared after 2 periods after MII IO signal become HIGH Z");
2920 169 mohor
                fail = fail + 1;
2921
              end
2922 181 mohor
              #Tp i1 = i1 + 1;
2923 169 mohor
            end
2924 181 mohor
          end
2925
          if (i2 == 0)
2926
          begin
2927
            if (phy_data[`ETH_MIISTATUS_NVALID] === 1'b0)
2928 169 mohor
            begin
2929 181 mohor
              i2 = 1;
2930 169 mohor
            end
2931 181 mohor
            else
2932
            begin
2933
              test_fail("Nvalid signal should be cleared after MII IO signal become HIGH Z");
2934
              fail = fail + 1;
2935
            end
2936 169 mohor
          end
2937
        end
2938 181 mohor
      end
2939
    end
2940
    // set PHY to normal mode
2941
    #Tp eth_phy.preamble_suppresed(0);
2942
    // MII mode register
2943
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2944
    if(fail == 0)
2945
      test_ok;
2946
    else
2947
      fail = 0;
2948
  end
2949
 
2950
 
2951
  ////////////////////////////////////////////////////////////////////
2952
  ////                                                            ////
2953
  ////  Test scan status from phy with detecting link-fail bit    ////
2954
  ////  (with and without preamble)                               ////
2955
  ////                                                            ////
2956
  ////////////////////////////////////////////////////////////////////
2957
  if (test_num == 14) // 
2958
  begin
2959 194 tadej
    // TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
2960
    test_name   = "TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
2961
    `TIME; $display("  TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
2962 181 mohor
 
2963
    reset_mii; // reset MII
2964
    // set link up, if it wasn't due to previous tests, since there weren't PHY registers
2965
    #Tp eth_phy.link_up_down(1);
2966
    // set MII speed
2967
    clk_div = 6;
2968
    mii_set_clk_div(clk_div[7:0]);
2969
    // set address
2970
    reg_addr = 5'h1; // status register
2971
    phy_addr = 5'h1; // correct PHY address
2972
 
2973
    // read request
2974
    #Tp mii_read_req(phy_addr, reg_addr);
2975
    check_mii_busy; // wait for read to finish
2976
    // read data from PHY status register - remember LINK-UP status
2977
    #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2978
 
2979
    for (i = 0; i <= 1; i = i + 1)
2980
    begin
2981
      #Tp eth_phy.preamble_suppresed(i);
2982
      // MII mode register
2983
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i, 8'h0}) | (`ETH_MIIMODER_CLKDIV & clk_div),
2984
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
2985
      if (i)
2986
      begin
2987
        // change saved data when preamble is suppressed
2988
        #Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
2989
      end
2990
 
2991
      // scan request
2992
      #Tp mii_scan_req(phy_addr, reg_addr);
2993
      check_mii_scan_valid; // wait for scan to make first data valid
2994
 
2995 169 mohor
      fork
2996 181 mohor
      begin
2997 169 mohor
        repeat(2) @(posedge Mdc_O);
2998
        // read data from PHY status register
2999
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3000 181 mohor
        if (phy_data !== tmp_data)
3001 169 mohor
        begin
3002 181 mohor
          test_fail("Data was not correctly scaned from status register");
3003 169 mohor
          fail = fail + 1;
3004
        end
3005
        // read data from MII status register
3006
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3007 181 mohor
        if (phy_data[0] !== 1'b0)
3008 169 mohor
        begin
3009 181 mohor
          test_fail("Link FAIL bit was set in the MII status register");
3010 169 mohor
          fail = fail + 1;
3011
        end
3012
      end
3013
      begin
3014 181 mohor
      // Completely check second scan
3015 169 mohor
        #Tp cnt = 0;
3016
        // wait for serial bus to become active - second scan
3017
        wait(Mdio_IO !== 1'bz);
3018
        // count transfer length
3019 181 mohor
        while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
3020 169 mohor
        begin
3021
          @(posedge Mdc_O);
3022
          #Tp cnt = cnt + 1;
3023
        end
3024
        // check transfer length
3025 181 mohor
        if (i) // without preamble
3026 169 mohor
        begin
3027
          if (cnt != 33) // at this value Mdio_IO is HIGH Z
3028
          begin
3029 181 mohor
            test_fail("Second scan request did not proceed correctly");
3030 169 mohor
            fail = fail + 1;
3031
          end
3032
        end
3033
        else // with preamble
3034
        begin
3035
          if (cnt != 65) // at this value Mdio_IO is HIGH Z
3036
          begin
3037 181 mohor
            test_fail("Second scan request did not proceed correctly");
3038 169 mohor
            fail = fail + 1;
3039
          end
3040
        end
3041
      end
3042
      join
3043 181 mohor
      // check third to fifth scans
3044
      for (i3 = 0; i3 <= 2; i3 = i3 + 1)
3045
      begin
3046
        fork
3047 169 mohor
        begin
3048
          repeat(2) @(posedge Mdc_O);
3049
          // read data from PHY status register
3050
          #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3051 181 mohor
          if (phy_data !== tmp_data)
3052 169 mohor
          begin
3053 181 mohor
            test_fail("Data was not correctly scaned from status register");
3054
            fail = fail + 1;
3055 169 mohor
          end
3056
          // read data from MII status register
3057
          #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3058 181 mohor
          if (phy_data[0] !== 1'b0)
3059 169 mohor
          begin
3060 181 mohor
            test_fail("Link FAIL bit was set in the MII status register");
3061
            fail = fail + 1;
3062 169 mohor
          end
3063 181 mohor
          if (i3 == 2) // after fourth scan read
3064 169 mohor
          begin
3065 181 mohor
            @(posedge Mdc_O);
3066
            // change saved data
3067
            #Tp tmp_data = tmp_data & 16'hFFFB; // put bit 3 to ZERO
3068
            // set link down
3069
            #Tp eth_phy.link_up_down(0);
3070 169 mohor
          end
3071
        end
3072
        begin
3073 181 mohor
        // Completely check scans
3074
          #Tp cnt = 0;
3075
          // wait for serial bus to become active - second scan
3076
          wait(Mdio_IO !== 1'bz);
3077
          // count transfer length
3078
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i == 0)) || ((cnt == 15) && (i == 1)) )
3079 169 mohor
          begin
3080 181 mohor
            @(posedge Mdc_O);
3081
            #Tp cnt = cnt + 1;
3082
          end
3083
          // check transfer length
3084
          if (i) // without preamble
3085
          begin
3086
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3087 169 mohor
            begin
3088 181 mohor
              test_fail("Fifth scan request did not proceed correctly");
3089
              fail = fail + 1;
3090 169 mohor
            end
3091 181 mohor
          end
3092
          else // with preamble
3093
          begin
3094
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3095 169 mohor
            begin
3096 181 mohor
              test_fail("Fifth scan request did not proceed correctly");
3097
              fail = fail + 1;
3098 169 mohor
            end
3099
          end
3100
        end
3101 181 mohor
        join
3102
      end
3103
 
3104
      fork
3105
      begin
3106
        repeat(2) @(posedge Mdc_O);
3107
        // read data from PHY status register
3108
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3109
        if (phy_data !== tmp_data)
3110
        begin
3111
          test_fail("Data was not correctly scaned from status register");
3112
          fail = fail + 1;
3113
        end
3114
        // read data from MII status register
3115
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3116
        if (phy_data[0] === 1'b0)
3117
        begin
3118
          test_fail("Link FAIL bit was not set in the MII status register");
3119
          fail = fail + 1;
3120
        end
3121
        // wait to see if data stayed latched
3122
        repeat(4) @(posedge Mdc_O);
3123
        // read data from PHY status register
3124
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3125
        if (phy_data !== tmp_data)
3126
        begin
3127
          test_fail("Data was not latched correctly in status register");
3128
          fail = fail + 1;
3129
        end
3130
        // read data from MII status register
3131
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3132
        if (phy_data[0] === 1'b0)
3133
        begin
3134
          test_fail("Link FAIL bit was not set in the MII status register");
3135
          fail = fail + 1;
3136
        end
3137
        // change saved data
3138
        #Tp tmp_data = tmp_data | 16'h0004; // put bit 2 to ONE
3139
        // set link up
3140
        #Tp eth_phy.link_up_down(1);
3141
      end
3142
      begin
3143
      // Wait for sixth scan
3144
        // wait for serial bus to become active - sixth scan
3145
        wait(Mdio_IO !== 1'bz);
3146
        // wait for serial bus to become inactive - turn-around cycle in sixth scan
3147
        wait(Mdio_IO === 1'bz);
3148
        // wait for serial bus to become active - end of turn-around cycle in sixth scan
3149
        wait(Mdio_IO !== 1'bz);
3150
        // wait for serial bus to become inactive - end of sixth scan
3151
        wait(Mdio_IO === 1'bz);
3152
      end
3153 169 mohor
      join
3154 181 mohor
 
3155
      @(posedge Mdc_O);
3156 169 mohor
      // read data from PHY status register
3157
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3158
      if (phy_data !== tmp_data)
3159
      begin
3160 181 mohor
        test_fail("Data was not correctly scaned from status register");
3161 169 mohor
        fail = fail + 1;
3162
      end
3163
      // read data from MII status register
3164
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3165
      if (phy_data[0] !== 1'b0)
3166
      begin
3167
        test_fail("Link FAIL bit was set in the MII status register");
3168
        fail = fail + 1;
3169
      end
3170 181 mohor
      // wait to see if data stayed latched
3171
      repeat(4) @(posedge Mdc_O);
3172
      // read data from PHY status register
3173
      #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3174
      if (phy_data !== tmp_data)
3175 169 mohor
      begin
3176 181 mohor
        test_fail("Data was not correctly scaned from status register");
3177
        fail = fail + 1;
3178 169 mohor
      end
3179 181 mohor
      // read data from MII status register
3180
      #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3181
      if (phy_data[0] !== 1'b0)
3182 169 mohor
      begin
3183 181 mohor
        test_fail("Link FAIL bit was set in the MII status register");
3184
        fail = fail + 1;
3185 169 mohor
      end
3186 181 mohor
 
3187
      // STOP SCAN
3188
      #Tp mii_scan_finish; // finish scan operation
3189
      #Tp check_mii_busy; // wait for scan to finish
3190 169 mohor
    end
3191 181 mohor
    // set PHY to normal mode
3192
    #Tp eth_phy.preamble_suppresed(0);
3193
    // MII mode register
3194
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3195
    if(fail == 0)
3196
      test_ok;
3197
    else
3198
      fail = 0;
3199 169 mohor
  end
3200
 
3201
 
3202 181 mohor
  ////////////////////////////////////////////////////////////////////
3203
  ////                                                            ////
3204
  ////  Test scan status from phy with sliding link-fail bit      ////
3205
  ////  (with and without preamble)                               ////
3206
  ////                                                            ////
3207
  ////////////////////////////////////////////////////////////////////
3208
  if (test_num == 15) // 
3209 169 mohor
  begin
3210 194 tadej
    // TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
3211
    test_name   = "TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )";
3212
    `TIME; $display("  TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )");
3213 181 mohor
 
3214
    // set address
3215
    reg_addr = 5'h1; // status register
3216
    phy_addr = 5'h1; // correct PHY address
3217
 
3218
    // read request
3219
    #Tp mii_read_req(phy_addr, reg_addr);
3220
    check_mii_busy; // wait for read to finish
3221
    // read data from PHY status register - remember LINK-UP status
3222
    #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3223
 
3224
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
3225 169 mohor
    begin
3226 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
3227
      // MII mode register
3228
      #Tp wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
3229
                    wbm_subseq_waits);
3230
      if (i2)
3231 169 mohor
      begin
3232 181 mohor
        // change saved data when preamble is suppressed
3233
        #Tp tmp_data = tmp_data | 16'h0040; // put bit 6 to ONE
3234
      end
3235
 
3236
      i = 0;
3237
      while (i < 80) // delay for sliding of LinkFail bit
3238
      begin
3239
        // first there are two scans
3240
        #Tp cnt = 0;
3241 169 mohor
        // scan request
3242
        #Tp mii_scan_req(phy_addr, reg_addr);
3243 181 mohor
        #Tp check_mii_scan_valid; // wait for scan to make first data valid
3244
 
3245
        // check second scan
3246 169 mohor
        fork
3247 181 mohor
        begin
3248
          repeat(4) @(posedge Mdc_O);
3249
          // read data from PHY status register
3250
          #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3251
          if (phy_data !== tmp_data)
3252 169 mohor
          begin
3253 181 mohor
            test_fail("Second data was not correctly scaned from status register");
3254
            fail = fail + 1;
3255 169 mohor
          end
3256 181 mohor
          // read data from MII status register
3257
          #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3258
          if (phy_data[0] !== 1'b0)
3259
          begin
3260
            test_fail("Link FAIL bit was set in the MII status register");
3261
            fail = fail + 1;
3262
          end
3263
        end
3264
        begin
3265
        // Completely check scan
3266
          #Tp cnt = 0;
3267
          // wait for serial bus to become active - second scan
3268
          wait(Mdio_IO !== 1'bz);
3269
          // count transfer length
3270
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3271
          begin
3272
            @(posedge Mdc_O);
3273
            #Tp cnt = cnt + 1;
3274
          end
3275
          // check transfer length
3276
          if (i2) // without preamble
3277
          begin
3278
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3279 169 mohor
            begin
3280 181 mohor
              test_fail("Second scan request did not proceed correctly");
3281
              fail = fail + 1;
3282 169 mohor
            end
3283 181 mohor
          end
3284
          else // with preamble
3285
          begin
3286
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3287
            begin
3288
              test_fail("Second scan request did not proceed correctly");
3289
              fail = fail + 1;
3290
            end
3291
          end
3292
        end
3293
        join
3294
        // reset counter 
3295
        #Tp cnt = 0;
3296
        // SLIDING LINK DOWN and CHECK
3297
        fork
3298
          begin
3299
          // set link down
3300
            repeat(i) @(posedge Mdc_O);
3301
            // set link down
3302
            #Tp eth_phy.link_up_down(0);
3303
          end
3304
          begin
3305
          // check data in MII registers after each scan in this fork statement
3306 169 mohor
            if (i2) // without preamble
3307 181 mohor
              wait (cnt == 32);
3308
            else // with preamble
3309
              wait (cnt == 64);
3310
            repeat(3) @(posedge Mdc_O);
3311
            // read data from PHY status register
3312
            #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3313
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3314 169 mohor
            begin
3315 181 mohor
              if (phy_data !== (tmp_data & 16'hFFFB)) // bit 3 is ZERO
3316 169 mohor
              begin
3317 181 mohor
                test_fail("Third data was not correctly scaned from status register");
3318 169 mohor
                fail = fail + 1;
3319
              end
3320
            end
3321 181 mohor
            else
3322 169 mohor
            begin
3323 181 mohor
              if (phy_data !== tmp_data)
3324 169 mohor
              begin
3325 181 mohor
                test_fail("Third data was not correctly scaned from status register");
3326 169 mohor
                fail = fail + 1;
3327
              end
3328
            end
3329 181 mohor
            // read data from MII status register
3330
            #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3331
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3332 169 mohor
            begin
3333 181 mohor
              if (phy_data[0] === 1'b0)
3334
              begin
3335
                test_fail("Link FAIL bit was not set in the MII status register");
3336
                fail = fail + 1;
3337
              end
3338 169 mohor
            end
3339 181 mohor
            else
3340 169 mohor
            begin
3341 181 mohor
              if (phy_data[0] !== 1'b0)
3342 169 mohor
              begin
3343 181 mohor
                test_fail("Link FAIL bit was set in the MII status register");
3344 169 mohor
                fail = fail + 1;
3345
              end
3346
            end
3347 181 mohor
          end
3348
          begin
3349
          // check length
3350
            for (i3 = 0; i3 <= 1; i3 = i3 + 1) // two scans
3351 169 mohor
            begin
3352 181 mohor
              #Tp cnt = 0;
3353
              // wait for serial bus to become active if there is more than one scan
3354
              wait(Mdio_IO !== 1'bz);
3355
              // count transfer length
3356
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3357 169 mohor
              begin
3358 181 mohor
                @(posedge Mdc_O);
3359
                #Tp cnt = cnt + 1;
3360 169 mohor
              end
3361 181 mohor
              // check transfer length
3362
              if (i2) // without preamble
3363
              begin
3364
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3365
                begin
3366
                  test_fail("3. or 4. scan request did not proceed correctly, while SCAN STOP was written");
3367
                  fail = fail + 1;
3368
                end
3369
              end
3370
              else // with preamble
3371
              begin
3372
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3373
                begin
3374
                  test_fail("3. or 4. scan request did not proceed correctly, while SCAN STOP was written");
3375
                  fail = fail + 1;
3376
                end
3377
              end
3378 169 mohor
            end
3379
          end
3380
        join
3381 181 mohor
        // reset counter
3382
        #Tp cnt = 0;
3383
        // check fifth scan and data from fourth scan
3384
        fork
3385 169 mohor
        begin
3386 181 mohor
          repeat(2) @(posedge Mdc_O);
3387
          // read data from PHY status register
3388
          #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3389
          if (phy_data !== (tmp_data & 16'hFFFB)) // bit 3 is ZERO
3390 169 mohor
          begin
3391 181 mohor
            test_fail("4. data was not correctly scaned from status register");
3392
            fail = fail + 1;
3393 169 mohor
          end
3394 181 mohor
          // read data from MII status register
3395
          #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3396
          if (phy_data[0] === 1'b0)
3397 169 mohor
          begin
3398 181 mohor
            test_fail("Link FAIL bit was not set in the MII status register");
3399 169 mohor
            fail = fail + 1;
3400
          end
3401
        end
3402
        begin
3403 181 mohor
        // Completely check intermediate scan
3404
          #Tp cnt = 0;
3405
          // wait for serial bus to become active - second scan
3406 169 mohor
          wait(Mdio_IO !== 1'bz);
3407
          // count transfer length
3408
          while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3409
          begin
3410
            @(posedge Mdc_O);
3411
            #Tp cnt = cnt + 1;
3412
          end
3413 181 mohor
          // check transfer length
3414
          if (i2) // without preamble
3415 169 mohor
          begin
3416 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3417
            begin
3418
              test_fail("Fifth scan request did not proceed correctly");
3419
              fail = fail + 1;
3420
            end
3421 169 mohor
          end
3422 181 mohor
          else // with preamble
3423
          begin
3424
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3425
            begin
3426
              test_fail("Fifth scan request did not proceed correctly");
3427
              fail = fail + 1;
3428
            end
3429
          end
3430 169 mohor
        end
3431 181 mohor
        join
3432
        // reset counter 
3433
        #Tp cnt = 0;
3434
        // SLIDING LINK UP and CHECK
3435
        fork
3436 169 mohor
          begin
3437 181 mohor
          // set link up
3438
            repeat(i) @(posedge Mdc_O);
3439
            // set link up
3440
            #Tp eth_phy.link_up_down(1);
3441 169 mohor
          end
3442 181 mohor
          begin
3443
          // check data in MII registers after each scan in this fork statement
3444
            repeat(2) @(posedge Mdc_O);
3445
            if (i2) // without preamble
3446
              wait (cnt == 32);
3447
            else // with preamble
3448
              wait (cnt == 64);
3449
            repeat(3) @(posedge Mdc_O);
3450
            // read data from PHY status register
3451
            #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3452
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3453
            begin
3454
              if (phy_data !== tmp_data)
3455
              begin
3456
                test_fail("6. data was not correctly scaned from status register");
3457
                fail = fail + 1;
3458
              end
3459
            end
3460
            else
3461
            begin
3462
              if (phy_data !== (tmp_data & 16'hFFFB)) // bit 3 is ZERO
3463
              begin
3464
                test_fail("6. data was not correctly scaned from status register");
3465
                fail = fail + 1;
3466
              end
3467
            end
3468
            // read data from MII status register
3469
            #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3470
            if ( ((i < 49) && !i2) || ((i < 17) && i2) )
3471
            begin
3472
              if (phy_data[0] !== 1'b0)
3473
              begin
3474
                test_fail("Link FAIL bit was set in the MII status register");
3475
                fail = fail + 1;
3476
              end
3477
            end
3478
            else
3479
            begin
3480
              if (phy_data[0] === 1'b0)
3481
              begin
3482
                test_fail("Link FAIL bit was not set in the MII status register");
3483
                fail = fail + 1;
3484
              end
3485
            end
3486
          end
3487
          begin
3488
          // check length
3489
            for (i3 = 0; i3 <= 1; i3 = i3 + 1) // two scans
3490
            begin
3491
              #Tp cnt = 0;
3492
              // wait for serial bus to become active if there is more than one scan
3493
              wait(Mdio_IO !== 1'bz);
3494
              // count transfer length
3495
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3496
              begin
3497
                @(posedge Mdc_O);
3498
                #Tp cnt = cnt + 1;
3499
              end
3500
              // check transfer length
3501
              if (i2) // without preamble
3502
              begin
3503
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3504
                begin
3505
                  test_fail("Scan request did not proceed correctly, while SCAN STOP was written");
3506
                  fail = fail + 1;
3507
                end
3508
              end
3509
              else // with preamble
3510
              begin
3511
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3512
                begin
3513
                  test_fail("Scan request did not proceed correctly, while SCAN STOP was written");
3514
                  fail = fail + 1;
3515
                end
3516
              end
3517
            end
3518
          end
3519
        join
3520
        // check last scan 
3521
        repeat(4) @(posedge Mdc_O);
3522
        // read data from PHY status register
3523
        #Tp wbm_read(`ETH_MIIRX_DATA, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3524
        if (phy_data !== tmp_data)
3525
        begin
3526
          test_fail("7. data was not correctly scaned from status register");
3527
          fail = fail + 1;
3528 169 mohor
        end
3529 181 mohor
        // read data from MII status register
3530
        #Tp wbm_read(`ETH_MIISTATUS, phy_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3531
        if (phy_data[0] !== 1'b0)
3532
        begin
3533
          test_fail("Link FAIL bit was set in the MII status register");
3534
          fail = fail + 1;
3535
        end
3536
 
3537
        #Tp mii_scan_finish; // finish scan operation
3538
        #Tp check_mii_busy; // wait for scan to finish
3539
        #Tp;
3540
        // set delay of writing the command
3541
        if (i2) // without preamble
3542
        begin
3543
          case(i)
3544
            0,  1,  2,  3,  4:  i = i + 1;
3545
            13, 14, 15, 16, 17,
3546
            18, 19, 20, 21, 22,
3547
            23, 24, 25, 26, 27,
3548
            28, 29, 30, 31, 32,
3549
            33, 34, 35:         i = i + 1;
3550
            36:                 i = 80;
3551
            default:            i = 13;
3552
          endcase
3553
        end
3554 169 mohor
        else // with preamble
3555
        begin
3556 181 mohor
          case(i)
3557
            0,  1,  2,  3,  4:  i = i + 1;
3558
            45, 46, 47, 48, 49,
3559
            50, 51, 52, 53, 54,
3560
            55, 56, 57, 58, 59,
3561
            60, 61, 62, 63, 64,
3562
            65, 66, 67:         i = i + 1;
3563
            68:                 i = 80;
3564
            default:            i = 45;
3565
          endcase
3566 169 mohor
        end
3567 181 mohor
        @(posedge wb_clk);
3568
        #Tp;
3569 169 mohor
      end
3570
    end
3571 181 mohor
    // set PHY to normal mode
3572
    #Tp eth_phy.preamble_suppresed(0);
3573
    // MII mode register
3574
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3575
    if(fail == 0)
3576
      test_ok;
3577
    else
3578
      fail = 0;
3579 169 mohor
  end
3580
 
3581
 
3582 181 mohor
  ////////////////////////////////////////////////////////////////////
3583
  ////                                                            ////
3584
  ////  Test sliding stop scan command immediately after scan     ////
3585
  ////  request (with and without preamble)                       ////
3586
  ////                                                            ////
3587
  ////////////////////////////////////////////////////////////////////
3588
  if (test_num == 16) // 
3589 116 mohor
  begin
3590 194 tadej
    // TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )
3591
    test_name = "TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )";
3592 181 mohor
    `TIME;
3593 194 tadej
    $display("  TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )");
3594 181 mohor
 
3595
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
3596 169 mohor
    begin
3597 181 mohor
      #Tp eth_phy.preamble_suppresed(i2);
3598
      // MII mode register
3599
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
3600
                wbm_subseq_waits);
3601
      i = 0;
3602
      cnt = 0;
3603
      while (i < 80) // delay for sliding of writing a STOP SCAN command
3604 169 mohor
      begin
3605 181 mohor
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after scan will be finished
3606 169 mohor
        begin
3607 181 mohor
          // set address
3608
          reg_addr = 5'h0; // control register
3609
          phy_addr = 5'h1; // correct PHY address
3610
          cnt = 0;
3611
          // scan request
3612
          #Tp mii_scan_req(phy_addr, reg_addr);
3613
          fork
3614
            begin
3615
              repeat(i) @(posedge Mdc_O);
3616
              // write command 0x0 into MII command register
3617
              // MII command written while scan in progress
3618
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3619
              @(posedge wb_clk);
3620
              #Tp check_mii_busy; // wait for scan to finish
3621
              @(posedge wb_clk);
3622
              disable check;
3623
            end
3624
            begin: check
3625
              // wait for serial bus to become active
3626
              wait(Mdio_IO !== 1'bz);
3627
              // count transfer length
3628
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3629
              begin
3630
                @(posedge Mdc_O);
3631
                #Tp cnt = cnt + 1;
3632
              end
3633
              // check transfer length
3634
              if (i2) // without preamble
3635
              begin
3636
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3637
                begin
3638
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3639
                  fail = fail + 1;
3640
                end
3641
              end
3642
              else // with preamble
3643
              begin
3644
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3645
                begin
3646
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3647
                  fail = fail + 1;
3648
                end
3649
              end
3650
              cnt = 0;
3651
              // wait for serial bus to become active if there is more than one scan
3652
              wait(Mdio_IO !== 1'bz);
3653
              // count transfer length
3654
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3655
              begin
3656
                @(posedge Mdc_O);
3657
                #Tp cnt = cnt + 1;
3658
              end
3659
              // check transfer length
3660
              if (i2) // without preamble
3661
              begin
3662
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3663
                begin
3664
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3665
                  fail = fail + 1;
3666
                end
3667
              end
3668
              else // with preamble
3669
              begin
3670
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3671
                begin
3672
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3673
                  fail = fail + 1;
3674
                end
3675
              end
3676
            end
3677
          join
3678
          // check the BUSY signal to see if the bus is still IDLE
3679
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
3680
            check_mii_busy; // wait for bus to become idle
3681
 
3682
          // try normal write or read after scan was finished
3683
          phy_data = {8'h7D, (i[7:0] + 1)};
3684
          cnt = 0;
3685
          if (i3 == 0) // write after scan
3686 169 mohor
          begin
3687 181 mohor
            // write request
3688
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
3689
            // wait for serial bus to become active
3690
            wait(Mdio_IO !== 1'bz);
3691
            // count transfer length
3692
            while(Mdio_IO !== 1'bz)
3693
            begin
3694
              @(posedge Mdc_O);
3695
              #Tp cnt = cnt + 1;
3696
            end
3697 169 mohor
            @(posedge Mdc_O);
3698 181 mohor
            // read request
3699
            #Tp mii_read_req(phy_addr, reg_addr);
3700
            check_mii_busy; // wait for read to finish
3701
            // read and check data
3702
            #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3703
            if (phy_data !== tmp_data)
3704 169 mohor
            begin
3705 181 mohor
              test_fail("Data was not correctly written into OR read from PHY register - control register");
3706 169 mohor
              fail = fail + 1;
3707
            end
3708
          end
3709 181 mohor
          else // read after scan
3710 169 mohor
          begin
3711 181 mohor
            // read request
3712
            #Tp mii_read_req(phy_addr, reg_addr);
3713
            // wait for serial bus to become active
3714
            wait(Mdio_IO !== 1'bz);
3715
            // count transfer length
3716
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3717 169 mohor
            begin
3718 181 mohor
              @(posedge Mdc_O);
3719
              #Tp cnt = cnt + 1;
3720
            end
3721
            @(posedge Mdc_O);
3722
            check_mii_busy; // wait for read to finish
3723
            // read and check data
3724
            #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3725
            if (phy_data !== tmp_data)
3726
            begin
3727
              test_fail("Data was not correctly written into OR read from PHY register - control register");
3728 169 mohor
              fail = fail + 1;
3729
            end
3730
          end
3731 181 mohor
          // check if transfer was a proper length
3732 169 mohor
          if (i2) // without preamble
3733
          begin
3734
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
3735
            begin
3736 181 mohor
              test_fail("New request did not proceed correctly, after scan request");
3737 169 mohor
              fail = fail + 1;
3738
            end
3739
          end
3740
          else // with preamble
3741
          begin
3742
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
3743
            begin
3744 181 mohor
              test_fail("New request did not proceed correctly, after scan request");
3745 169 mohor
              fail = fail + 1;
3746
            end
3747
          end
3748
        end
3749 181 mohor
        #Tp;
3750
        // set delay of writing the command
3751
        if (i2) // without preamble
3752
        begin
3753
          case(i)
3754
            0, 1:               i = i + 1;
3755
            18, 19, 20, 21, 22,
3756
            23, 24, 25, 26, 27,
3757
            28, 29, 30, 31, 32,
3758
            33, 34, 35:         i = i + 1;
3759
            36:                 i = 80;
3760
            default:            i = 18;
3761
          endcase
3762
        end
3763
        else // with preamble
3764
        begin
3765
          case(i)
3766
            0, 1:               i = i + 1;
3767
            50, 51, 52, 53, 54,
3768
            55, 56, 57, 58, 59,
3769
            60, 61, 62, 63, 64,
3770
            65, 66, 67:         i = i + 1;
3771
            68:                 i = 80;
3772
            default:            i = 50;
3773
          endcase
3774
        end
3775
        @(posedge wb_clk);
3776
      end
3777
    end
3778
    // set PHY to normal mode
3779
    #Tp eth_phy.preamble_suppresed(0);
3780
    // MII mode register
3781
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3782
    if(fail == 0)
3783
      test_ok;
3784
    else
3785
      fail = 0;
3786
  end
3787 169 mohor
 
3788 181 mohor
 
3789
  ////////////////////////////////////////////////////////////////////
3790
  ////                                                            ////
3791
  ////  Test sliding stop scan command after 2. scan (with and    ////
3792
  ////  without preamble)                                         ////
3793
  ////                                                            ////
3794
  ////////////////////////////////////////////////////////////////////
3795
  if (test_num == 17) // 
3796
  begin
3797 194 tadej
    // TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )
3798
    test_name = "TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )";
3799
    `TIME; $display("  TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )");
3800 181 mohor
 
3801
    for (i2 = 0; i2 <= 1; i2 = i2 + 1) // choose preamble or not
3802
    begin
3803
      #Tp eth_phy.preamble_suppresed(i2);
3804
      // MII mode register
3805
      wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_NOPRE & {23'h0, i2, 8'h0}), 4'hF, 1, wbm_init_waits,
3806
                wbm_subseq_waits);
3807
 
3808
      i = 0;
3809
      cnt = 0;
3810
      while (i < 80) // delay for sliding of writing a STOP SCAN command
3811
      begin
3812
        for (i3 = 0; i3 <= 1; i3 = i3 + 1) // choose read or write after scan will be finished
3813
        begin
3814
          // first there are two scans
3815
          // set address
3816
          reg_addr = 5'h0; // control register
3817
          phy_addr = 5'h1; // correct PHY address
3818
          cnt = 0;
3819
          // scan request
3820
          #Tp mii_scan_req(phy_addr, reg_addr);
3821
          // wait and check first 2 scans
3822 169 mohor
          begin
3823
            // wait for serial bus to become active
3824
            wait(Mdio_IO !== 1'bz);
3825
            // count transfer length
3826
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3827
            begin
3828
              @(posedge Mdc_O);
3829
              #Tp cnt = cnt + 1;
3830
            end
3831
            // check transfer length
3832
            if (i2) // without preamble
3833
            begin
3834
              if (cnt != 33) // at this value Mdio_IO is HIGH Z
3835
              begin
3836
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3837
                fail = fail + 1;
3838
              end
3839
            end
3840
            else // with preamble
3841
            begin
3842
              if (cnt != 65) // at this value Mdio_IO is HIGH Z
3843
              begin
3844
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3845
                fail = fail + 1;
3846
              end
3847
            end
3848
            cnt = 0;
3849
            // wait for serial bus to become active if there is more than one scan
3850
            wait(Mdio_IO !== 1'bz);
3851
            // count transfer length
3852
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3853
            begin
3854
              @(posedge Mdc_O);
3855
              #Tp cnt = cnt + 1;
3856
            end
3857
            // check transfer length
3858
            if (i2) // without preamble
3859
            begin
3860
              if (cnt != 33) // at this value Mdio_IO is HIGH Z
3861
              begin
3862
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3863
                fail = fail + 1;
3864
              end
3865
            end
3866
            else // with preamble
3867
            begin
3868
              if (cnt != 65) // at this value Mdio_IO is HIGH Z
3869
              begin
3870
                test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3871
                fail = fail + 1;
3872
              end
3873
            end
3874
          end
3875
 
3876 181 mohor
          // reset counter 
3877
          cnt = 0;
3878
          fork
3879
            begin
3880
              repeat(i) @(posedge Mdc_O);
3881
              // write command 0x0 into MII command register
3882
              // MII command written while scan in progress
3883
              wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3884
              @(posedge wb_clk);
3885
              #Tp check_mii_busy; // wait for scan to finish
3886
              @(posedge wb_clk);
3887
              disable check_3;
3888
            end
3889
            begin: check_3
3890
              // wait for serial bus to become active
3891
              wait(Mdio_IO !== 1'bz);
3892
              // count transfer length
3893
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3894
              begin
3895
                @(posedge Mdc_O);
3896
                #Tp cnt = cnt + 1;
3897
              end
3898
              // check transfer length
3899
              if (i2) // without preamble
3900
              begin
3901
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3902
                begin
3903
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3904
                  fail = fail + 1;
3905
                end
3906
              end
3907
              else // with preamble
3908
              begin
3909
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3910
                begin
3911
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3912
                  fail = fail + 1;
3913
                end
3914
              end
3915
              cnt = 0;
3916
              // wait for serial bus to become active if there is more than one scan
3917
              wait(Mdio_IO !== 1'bz);
3918
              // count transfer length
3919
              while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3920
              begin
3921
                @(posedge Mdc_O);
3922
                #Tp cnt = cnt + 1;
3923
              end
3924
              // check transfer length
3925
              if (i2) // without preamble
3926
              begin
3927
                if (cnt != 33) // at this value Mdio_IO is HIGH Z
3928
                begin
3929
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3930
                  fail = fail + 1;
3931
                end
3932
              end
3933
              else // with preamble
3934
              begin
3935
                if (cnt != 65) // at this value Mdio_IO is HIGH Z
3936
                begin
3937
                  test_fail("First scan request did not proceed correctly, while SCAN STOP was written");
3938
                  fail = fail + 1;
3939
                end
3940
              end
3941
            end
3942
          join
3943
          // check the BUSY signal to see if the bus is still IDLE
3944
          for (i1 = 0; i1 < 8; i1 = i1 + 1)
3945
            check_mii_busy; // wait for bus to become idle
3946
 
3947
          // try normal write or read after scan was finished
3948
          phy_data = {8'h7D, (i[7:0] + 1)};
3949
          cnt = 0;
3950
          if (i3 == 0) // write after scan
3951 169 mohor
          begin
3952 181 mohor
            // write request
3953
            #Tp mii_write_req(phy_addr, reg_addr, phy_data);
3954
            // wait for serial bus to become active
3955
            wait(Mdio_IO !== 1'bz);
3956
            // count transfer length
3957
            while(Mdio_IO !== 1'bz)
3958
            begin
3959
              @(posedge Mdc_O);
3960
              #Tp cnt = cnt + 1;
3961
            end
3962 169 mohor
            @(posedge Mdc_O);
3963 181 mohor
            // read request
3964
            #Tp mii_read_req(phy_addr, reg_addr);
3965
            check_mii_busy; // wait for read to finish
3966
            // read and check data
3967
            #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3968
            if (phy_data !== tmp_data)
3969
            begin
3970
              test_fail("Data was not correctly written into OR read from PHY register - control register");
3971
              fail = fail + 1;
3972
            end
3973 169 mohor
          end
3974 181 mohor
          else // read after scan
3975 169 mohor
          begin
3976 181 mohor
            // read request
3977
            #Tp mii_read_req(phy_addr, reg_addr);
3978
            // wait for serial bus to become active
3979
            wait(Mdio_IO !== 1'bz);
3980
            // count transfer length
3981
            while( (Mdio_IO !== 1'bz) || ((cnt == 47) && (i2 == 0)) || ((cnt == 15) && (i2 == 1)) )
3982
            begin
3983
              @(posedge Mdc_O);
3984
              #Tp cnt = cnt + 1;
3985
            end
3986
            @(posedge Mdc_O);
3987
            check_mii_busy; // wait for read to finish
3988
            // read and check data
3989
            #Tp wbm_read(`ETH_MIIRX_DATA, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
3990
            if (phy_data !== tmp_data)
3991
            begin
3992
              test_fail("Data was not correctly written into OR read from PHY register - control register");
3993
              fail = fail + 1;
3994
            end
3995 169 mohor
          end
3996 181 mohor
          // check if transfer was a proper length
3997
          if (i2) // without preamble
3998 169 mohor
          begin
3999 181 mohor
            if (cnt != 33) // at this value Mdio_IO is HIGH Z
4000
            begin
4001
              test_fail("New request did not proceed correctly, after scan request");
4002
              fail = fail + 1;
4003
            end
4004 169 mohor
          end
4005 181 mohor
          else // with preamble
4006 169 mohor
          begin
4007 181 mohor
            if (cnt != 65) // at this value Mdio_IO is HIGH Z
4008
            begin
4009
              test_fail("New request did not proceed correctly, after scan request");
4010
              fail = fail + 1;
4011
            end
4012 169 mohor
          end
4013
        end
4014 181 mohor
        #Tp;
4015
        // set delay of writing the command
4016 169 mohor
        if (i2) // without preamble
4017
        begin
4018 181 mohor
          case(i)
4019
            0, 1:               i = i + 1;
4020
            18, 19, 20, 21, 22,
4021
            23, 24, 25, 26, 27,
4022
            28, 29, 30, 31, 32,
4023
            33, 34, 35:         i = i + 1;
4024
            36:                 i = 80;
4025
            default:            i = 18;
4026
          endcase
4027 169 mohor
        end
4028
        else // with preamble
4029
        begin
4030 181 mohor
          case(i)
4031
            0, 1:               i = i + 1;
4032
            50, 51, 52, 53, 54,
4033
            55, 56, 57, 58, 59,
4034
            60, 61, 62, 63, 64,
4035
            65, 66, 67:         i = i + 1;
4036
            68:                 i = 80;
4037
            default:            i = 50;
4038
          endcase
4039 169 mohor
        end
4040 181 mohor
        @(posedge wb_clk);
4041 116 mohor
      end
4042
    end
4043 181 mohor
    // set PHY to normal mode
4044
    #Tp eth_phy.preamble_suppresed(0);
4045
    // MII mode register
4046
    wbm_write(`ETH_MIIMODER, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4047
    if(fail == 0)
4048
      test_ok;
4049
    else
4050
      fail = 0;
4051 169 mohor
  end
4052 116 mohor
 
4053 181 mohor
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
4054
 
4055 169 mohor
end
4056
endtask // test_mii
4057
 
4058
 
4059
task test_mac_full_duplex_transmit;
4060
  input  [31:0]  start_task;
4061
  input  [31:0]  end_task;
4062
  integer        bit_start_1;
4063
  integer        bit_end_1;
4064
  integer        bit_start_2;
4065
  integer        bit_end_2;
4066
  integer        num_of_reg;
4067 209 tadejm
  integer        num_of_frames;
4068
  integer        num_of_bd;
4069 169 mohor
  integer        i_addr;
4070
  integer        i_data;
4071
  integer        i_length;
4072 209 tadejm
  integer        tmp_len;
4073
  integer        tmp_bd;
4074
  integer        tmp_bd_num;
4075 169 mohor
  integer        tmp_data;
4076 209 tadejm
  integer        tmp_ipgt;
4077 194 tadej
  integer        test_num;
4078 169 mohor
  reg    [31:0]  tx_bd_num;
4079
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
4080
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
4081
  integer        i;
4082
  integer        i1;
4083
  integer        i2;
4084
  integer        i3;
4085
  integer        fail;
4086
  integer        speed;
4087 209 tadejm
  reg            frame_started;
4088
  reg            frame_ended;
4089
  reg            wait_for_frame;
4090 169 mohor
  reg    [31:0]  addr;
4091
  reg    [31:0]  data;
4092
  reg    [31:0]  tmp;
4093
  reg    [ 7:0]  st_data;
4094
  reg    [15:0]  max_tmp;
4095
  reg    [15:0]  min_tmp;
4096
begin
4097
// MAC FULL DUPLEX TRANSMIT TEST
4098
test_heading("MAC FULL DUPLEX TRANSMIT TEST");
4099
$display(" ");
4100
$display("MAC FULL DUPLEX TRANSMIT TEST");
4101
fail = 0;
4102
 
4103
// reset MAC registers
4104
hard_reset;
4105
// reset MAC and MII LOGIC with soft reset
4106
reset_mac;
4107
reset_mii;
4108
// set wb slave response
4109
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
4110
 
4111
  /*
4112
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
4113
  -------------------------------------------------------------------------------------
4114
  set_tx_bd
4115
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
4116
  set_tx_bd_wrap
4117
    (tx_bd_num_end[6:0]);
4118
  set_tx_bd_ready
4119
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
4120
  check_tx_bd
4121
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
4122
  clear_tx_bd
4123
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
4124
 
4125
  TASKS for set and control RX buffer descriptors:
4126
  ------------------------------------------------
4127
  set_rx_bd
4128
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
4129
  set_rx_bd_wrap
4130
    (rx_bd_num_end[6:0]);
4131
  set_rx_bd_empty
4132
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
4133
  check_rx_bd
4134
    (rx_bd_num_end[6:0], rx_bd_status);
4135
  clear_rx_bd
4136
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
4137
 
4138
  TASKS for set and check TX packets:
4139
  -----------------------------------
4140
  set_tx_packet
4141
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
4142
  check_tx_packet
4143
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
4144
 
4145
  TASKS for set and check RX packets:
4146
  -----------------------------------
4147
  set_rx_packet
4148
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
4149
  check_rx_packet
4150
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
4151
 
4152
  TASKS for append and check CRC to/of TX packet:
4153
  -----------------------------------------------
4154
  append_tx_crc
4155
    (txpnt_wb[31:0], len[15:0], negated_crc);
4156
  check_tx_crc
4157
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
4158
 
4159
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
4160
  --------------------------------------------------------------------------------
4161
  append_rx_crc
4162
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
4163
  */
4164
 
4165 194 tadej
//////////////////////////////////////////////////////////////////////
4166
////                                                              ////
4167
////  test_mac_full_duplex_transmit:                              ////
4168
////                                                              ////
4169
////  0: Test no transmit when all buffers are RX ( 10Mbps ).     ////
4170
////  1: Test no transmit when all buffers are RX ( 100Mbps ).    ////
4171
////  2: Test transmit packets form MINFL to MAXFL sizes at       ////
4172
////     one TX buffer decriptor ( 10Mbps ).                      ////
4173
////  3: Test transmit packets form MINFL to MAXFL sizes at       ////
4174
////     one TX buffer decriptor ( 100Mbps ).                     ////
4175
////                                                              ////
4176
//////////////////////////////////////////////////////////////////////
4177
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
4178 169 mohor
begin
4179
 
4180 194 tadej
  ////////////////////////////////////////////////////////////////////
4181
  ////                                                            ////
4182
  ////  Test no transmit when all buffers are RX ( 10Mbps ).      ////
4183
  ////                                                            ////
4184
  ////////////////////////////////////////////////////////////////////
4185
  if (test_num == 0) // Test no transmit when all buffers are RX ( 10Mbps ).
4186 169 mohor
  begin
4187 194 tadej
    // TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )
4188
    test_name   = "TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )";
4189
    `TIME; $display("  TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )");
4190
 
4191
    // unmask interrupts
4192 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4193 194 tadej
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4194
    // set all buffer descriptors to RX - must be set before TX enable
4195
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4196
    // enable TX, set full-duplex mode, padding and CRC appending
4197
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4198
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4199
 
4200
    // write to phy's control register for 10Mbps
4201
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
4202
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
4203
    speed = 10;
4204
 
4205
    i = 0;
4206
    while (i < 128)
4207 169 mohor
    begin
4208 194 tadej
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
4209 169 mohor
      begin
4210 194 tadej
        set_tx_packet((`MEMORY_BASE + (i1 * 200)), 100, 0);
4211
        set_tx_bd(i1, i1, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + (i1 * 200)));
4212 169 mohor
      end
4213 194 tadej
      set_tx_bd_wrap(i);
4214
      fork
4215
        begin
4216
          set_tx_bd_ready(0, i);
4217
          repeat(20) @(negedge mtx_clk);
4218
          #1 disable check_tx_en10;
4219
        end
4220
        begin: check_tx_en10
4221
          wait (MTxEn === 1'b1);
4222
          test_fail("Tramsmit should not start at all");
4223
          fail = fail + 1;
4224
          `TIME; $display("*E Transmit of %d packets should not start at all - active MTxEn", i);
4225
        end
4226
      join
4227
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
4228 169 mohor
      begin
4229 194 tadej
        check_tx_bd(0, tmp);
4230
        #1;
4231
        if (tmp[15] === 1'b0)
4232
        begin
4233
          test_fail("Tramsmit should not start at all");
4234
          fail = fail + 1;
4235
          `TIME; $display("*E Transmit of %d packets should not start at all - ready is 0", i);
4236
        end
4237
        if (tmp[8:0] !== 0)
4238
        begin
4239
          test_fail("Tramsmit should not be finished since it should not start at all");
4240
          fail = fail + 1;
4241
          `TIME; $display("*E Transmit of should not be finished since it should not start at all");
4242
        end
4243
        @(posedge wb_clk);
4244 169 mohor
      end
4245 194 tadej
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4246
      if (tmp[6:0] !== 0)
4247 169 mohor
      begin
4248 194 tadej
        test_fail("Tramsmit should not get INT since it should not start at all");
4249 169 mohor
        fail = fail + 1;
4250 194 tadej
        `TIME; $display("*E Transmit of should not get INT since it should not start at all");
4251 169 mohor
      end
4252 194 tadej
      clear_tx_bd(0, i);
4253
      if ((i < 5) || (i > 124))
4254
        i = i + 1;
4255
      else
4256
        i = i + 120;
4257 116 mohor
    end
4258 194 tadej
    // disable TX
4259
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4260
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4261
    if(fail == 0)
4262
      test_ok;
4263 116 mohor
    else
4264 194 tadej
      fail = 0;
4265 169 mohor
  end
4266 116 mohor
 
4267
 
4268 194 tadej
  ////////////////////////////////////////////////////////////////////
4269
  ////                                                            ////
4270
  ////  Test no transmit when all buffers are RX ( 100Mbps ).     ////
4271
  ////                                                            ////
4272
  ////////////////////////////////////////////////////////////////////
4273
  if (test_num == 1) // Test no transmit when all buffers are RX ( 100Mbps ).
4274 169 mohor
  begin
4275 194 tadej
    // TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )
4276
    test_name   = "TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )";
4277
    `TIME; $display("  TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )");
4278
 
4279
    // unmask interrupts
4280 209 tadejm
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4281 194 tadej
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4282
    // set all buffer descriptors to RX - must be set before TX enable
4283
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4284
    // enable TX, set full-duplex mode, padding and CRC appending
4285
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4286
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4287
 
4288
    // write to phy's control register for 100Mbps
4289
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
4290
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
4291
    speed = 100;
4292
 
4293
    i = 0;
4294
    while (i < 128)
4295 169 mohor
    begin
4296 194 tadej
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
4297 169 mohor
      begin
4298 194 tadej
        set_tx_packet((`MEMORY_BASE + (i1 * 200)), 100, 0);
4299
        set_tx_bd(i1, i1, 100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + (i1 * 200)));
4300 169 mohor
      end
4301 194 tadej
      set_tx_bd_wrap(i);
4302
      fork
4303
        begin
4304
          set_tx_bd_ready(0, i);
4305
          repeat(20) @(negedge mtx_clk);
4306
          #1 disable check_tx_en100;
4307
        end
4308
        begin: check_tx_en100
4309
          wait (MTxEn === 1'b1);
4310
          test_fail("Tramsmit should not start at all");
4311
          fail = fail + 1;
4312
          `TIME; $display("*E Transmit of %d packets should not start at all - active MTxEn", i);
4313
        end
4314
      join
4315
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
4316 169 mohor
      begin
4317 194 tadej
        check_tx_bd(0, tmp);
4318
        #1;
4319
        if (tmp[15] === 1'b0)
4320
        begin
4321
          test_fail("Tramsmit should not start at all");
4322
          fail = fail + 1;
4323
          `TIME; $display("*E Transmit of %d packets should not start at all - ready is 0", i);
4324
        end
4325
        if (tmp[8:0] !== 0)
4326
        begin
4327
          test_fail("Tramsmit should not be finished since it should not start at all");
4328
          fail = fail + 1;
4329
          `TIME; $display("*E Transmit of should not be finished since it should not start at all");
4330
        end
4331
        @(posedge wb_clk);
4332 169 mohor
      end
4333 194 tadej
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4334
      if (tmp[6:0] !== 0)
4335 169 mohor
      begin
4336 194 tadej
        test_fail("Tramsmit should not get INT since it should not start at all");
4337 169 mohor
        fail = fail + 1;
4338 194 tadej
        `TIME; $display("*E Transmit of should not get INT since it should not start at all");
4339 169 mohor
      end
4340 194 tadej
      clear_tx_bd(0, i);
4341
      if ((i < 5) || (i > 124))
4342
        i = i + 1;
4343
      else
4344
        i = i + 120;
4345 169 mohor
    end
4346 194 tadej
    // disable TX
4347
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4348
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4349
    if(fail == 0)
4350
      test_ok;
4351 169 mohor
    else
4352 194 tadej
      fail = 0;
4353 169 mohor
  end
4354
 
4355
 
4356 194 tadej
  ////////////////////////////////////////////////////////////////////
4357
  ////                                                            ////
4358
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
4359
  ////  one TX buffer decriptor ( 10Mbps ).                       ////
4360
  ////                                                            ////
4361
  ////////////////////////////////////////////////////////////////////
4362 209 tadejm
  if (test_num == 2) // without and with padding
4363 169 mohor
  begin
4364 194 tadej
    // TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
4365
    test_name = "TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )";
4366
    `TIME; $display("  TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )");
4367
 
4368
    max_tmp = 0;
4369
    min_tmp = 0;
4370
    // set one TX buffer descriptor - must be set before TX enable
4371
    wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4372 209 tadejm
    // enable TX, set full-duplex mode, NO padding and CRC appending
4373
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4374 194 tadej
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4375
    // prepare two packets of MAXFL length
4376
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4377
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
4378
    min_tmp = tmp[31:16];
4379 209 tadejm
    st_data = 8'h01;
4380
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
4381 194 tadej
    st_data = 8'h10;
4382 209 tadejm
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
4383 194 tadej
    // check WB INT signal
4384
    if (wb_int !== 1'b0)
4385 169 mohor
    begin
4386 194 tadej
      test_fail("WB INT signal should not be set");
4387
      fail = fail + 1;
4388 169 mohor
    end
4389 194 tadej
 
4390
    // write to phy's control register for 10Mbps
4391
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
4392
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
4393
    speed = 10;
4394
 
4395
    i_length = (min_tmp - 4);
4396
    while (i_length <= (max_tmp - 4))
4397 169 mohor
    begin
4398 194 tadej
      // choose generating carrier sense and collision for first and last 64 lengths of frames
4399
      case (i_length[1:0])
4400
      2'h0: // Interrupt is generated
4401 169 mohor
      begin
4402 194 tadej
        // enable interrupt generation
4403 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4404 194 tadej
        // unmask interrupts
4405 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4406 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4407
        // not detect carrier sense in FD and no collision
4408
        eth_phy.carrier_sense_tx_fd_detect(0);
4409
        eth_phy.collision(0);
4410 169 mohor
      end
4411 194 tadej
      2'h1: // Interrupt is not generated
4412 169 mohor
      begin
4413 194 tadej
        // enable interrupt generation
4414 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4415 194 tadej
        // mask interrupts
4416
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4417
        // detect carrier sense in FD and no collision
4418
        eth_phy.carrier_sense_tx_fd_detect(1);
4419
        eth_phy.collision(0);
4420 169 mohor
      end
4421 194 tadej
      2'h2: // Interrupt is not generated
4422
      begin
4423
        // disable interrupt generation
4424 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4425 194 tadej
        // unmask interrupts
4426 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4427 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4428
        // not detect carrier sense in FD and set collision
4429
        eth_phy.carrier_sense_tx_fd_detect(0);
4430
        eth_phy.collision(1);
4431
      end
4432
      default: // 2'h3: // Interrupt is not generated
4433
      begin
4434
        // disable interrupt generation
4435 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4436 194 tadej
        // mask interrupts
4437
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4438
        // detect carrier sense in FD and set collision
4439
        eth_phy.carrier_sense_tx_fd_detect(1);
4440
        eth_phy.collision(1);
4441
      end
4442
      endcase
4443
      eth_phy.set_tx_mem_addr(max_tmp);
4444
      // set wrap bit
4445
      set_tx_bd_wrap(0);
4446
      set_tx_bd_ready(0, 0);
4447 169 mohor
      #1 check_tx_bd(0, data);
4448 194 tadej
      if (i_length < min_tmp) // just first four
4449 169 mohor
      begin
4450 194 tadej
        while (data[15] === 1)
4451
        begin
4452
          #1 check_tx_bd(0, data);
4453
          @(posedge wb_clk);
4454
        end
4455 209 tadejm
        repeat (1) @(posedge wb_clk);
4456 169 mohor
      end
4457 194 tadej
      else if (i_length > (max_tmp - 8)) // just last four
4458 192 tadej
      begin
4459 194 tadej
        tmp = 0;
4460
        wait (MTxEn === 1'b1); // start transmit
4461
        while (tmp < (i_length - 20))
4462
        begin
4463
          #1 tmp = tmp + 1;
4464
          @(posedge wb_clk);
4465
        end
4466
        #1 check_tx_bd(0, data);
4467
        while (data[15] === 1)
4468
        begin
4469
          #1 check_tx_bd(0, data);
4470
          @(posedge wb_clk);
4471
        end
4472 209 tadejm
        repeat (1) @(posedge wb_clk);
4473 192 tadej
      end
4474
      else
4475
      begin
4476 194 tadej
        wait (MTxEn === 1'b1); // start transmit
4477
        #1 check_tx_bd(0, data);
4478
        if (data[15] !== 1)
4479
        begin
4480
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
4481
          fail = fail + 1;
4482
        end
4483
        wait (MTxEn === 1'b0); // end transmit
4484
        while (data[15] === 1)
4485
        begin
4486
          #1 check_tx_bd(0, data);
4487
          @(posedge wb_clk);
4488
        end
4489
        repeat (1) @(posedge wb_clk);
4490 192 tadej
      end
4491 194 tadej
      // check length of a PACKET
4492
      if (eth_phy.tx_len != (i_length + 4))
4493 192 tadej
      begin
4494 194 tadej
        test_fail("Wrong length of the packet out from MAC");
4495 192 tadej
        fail = fail + 1;
4496
      end
4497 194 tadej
      // checking in the following if statement is performed only for first and last 64 lengths
4498
      if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
4499 192 tadej
      begin
4500 194 tadej
        // check transmitted TX packet data
4501
        if (i_length[0] == 0)
4502
        begin
4503 209 tadejm
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
4504 194 tadej
        end
4505
        else
4506
        begin
4507 209 tadejm
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
4508 194 tadej
        end
4509
        if (tmp > 0)
4510
        begin
4511
          test_fail("Wrong data of the transmitted packet");
4512
          fail = fail + 1;
4513
        end
4514
        // check transmited TX packet CRC
4515
        check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
4516
        if (tmp > 0)
4517
        begin
4518
          test_fail("Wrong CRC of the transmitted packet");
4519
          fail = fail + 1;
4520
        end
4521 192 tadej
      end
4522 194 tadej
      // check WB INT signal
4523
      if (i_length[1:0] == 2'h0)
4524 192 tadej
      begin
4525 194 tadej
        if (wb_int !== 1'b1)
4526
        begin
4527
          `TIME; $display("*E WB INT signal should be set");
4528
          test_fail("WB INT signal should be set");
4529
          fail = fail + 1;
4530
        end
4531 192 tadej
      end
4532 194 tadej
      else
4533 192 tadej
      begin
4534 194 tadej
        if (wb_int !== 1'b0)
4535
        begin
4536
          `TIME; $display("*E WB INT signal should not be set");
4537
          test_fail("WB INT signal should not be set");
4538
          fail = fail + 1;
4539
        end
4540 192 tadej
      end
4541 194 tadej
      // check TX buffer descriptor of a packet
4542
      check_tx_bd(0, data);
4543
      if (i_length[1] == 1'b0) // interrupt enabled
4544 192 tadej
      begin
4545 194 tadej
        if (data[15:0] !== 16'h7800)
4546
        begin
4547
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4548
          test_fail("TX buffer descriptor status is not correct");
4549
          fail = fail + 1;
4550
        end
4551 192 tadej
      end
4552 194 tadej
      else // interrupt not enabled
4553 192 tadej
      begin
4554 194 tadej
        if (data[15:0] !== 16'h3800)
4555
        begin
4556
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4557
          test_fail("TX buffer descriptor status is not correct");
4558
          fail = fail + 1;
4559
        end
4560 192 tadej
      end
4561 194 tadej
      // clear TX buffer descriptor
4562
      clear_tx_bd(0, 0);
4563
      // check interrupts
4564
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4565
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
4566 192 tadej
      begin
4567 194 tadej
        if ((data & `ETH_INT_TXB) !== 1'b1)
4568
        begin
4569
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
4570
          test_fail("Interrupt Transmit Buffer was not set");
4571
          fail = fail + 1;
4572
        end
4573
        if ((data & (~`ETH_INT_TXB)) !== 0)
4574
        begin
4575
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
4576
          test_fail("Other interrupts (except Transmit Buffer) were set");
4577
          fail = fail + 1;
4578
        end
4579 192 tadej
      end
4580 194 tadej
      else
4581 192 tadej
      begin
4582 194 tadej
        if (data !== 0)
4583
        begin
4584
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
4585
          test_fail("Any of interrupts (except Transmit Buffer) was set");
4586
          fail = fail + 1;
4587
        end
4588 192 tadej
      end
4589 194 tadej
      // clear interrupts
4590
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4591
      // check WB INT signal
4592
      if (wb_int !== 1'b0)
4593 192 tadej
      begin
4594 194 tadej
        test_fail("WB INT signal should not be set");
4595 192 tadej
        fail = fail + 1;
4596
      end
4597 194 tadej
      // INTERMEDIATE DISPLAYS
4598
      if ((i_length + 4) == (min_tmp + 64))
4599 209 tadejm
      begin
4600 194 tadej
        // starting length is min_tmp, ending length is (min_tmp + 64)
4601 209 tadejm
        $display("    pads appending to packets is NOT selected");
4602
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
4603 194 tadej
                 min_tmp, (min_tmp + 64));
4604 209 tadejm
        // set padding, remain the rest
4605
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4606
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4607
      end
4608 194 tadej
      else if ((i_length + 4) == (max_tmp - 16))
4609 209 tadejm
      begin
4610 194 tadej
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
4611 209 tadejm
        $display("    pads appending to packets is selected");
4612
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
4613 194 tadej
                 (min_tmp + 64 + 128), tmp_data);
4614 209 tadejm
        // reset padding, remain the rest
4615
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4616
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4617
      end
4618 194 tadej
      else if ((i_length + 4) == max_tmp)
4619 209 tadejm
      begin
4620
        $display("    pads appending to packets is NOT selected");
4621
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
4622 194 tadej
                 (max_tmp - (4 + 16)), max_tmp);
4623 209 tadejm
      end
4624 194 tadej
      // set length (loop variable)
4625
      if ((i_length + 4) < (min_tmp + 64))
4626
        i_length = i_length + 1;
4627
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
4628
      begin
4629
        i_length = i_length + 128;
4630
        tmp_data = i_length + 4; // last tmp_data is ending length
4631
      end
4632
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
4633
        i_length = max_tmp - (4 + 16);
4634
      else if ((i_length + 4) >= (max_tmp - 16))
4635
        i_length = i_length + 1;
4636
      else
4637
      begin
4638
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
4639
        #10 $stop;
4640
      end
4641 192 tadej
    end
4642 194 tadej
    // disable TX
4643
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4644
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4645
    if(fail == 0)
4646
      test_ok;
4647
    else
4648
      fail = 0;
4649
  end
4650
 
4651
 
4652
  ////////////////////////////////////////////////////////////////////
4653
  ////                                                            ////
4654
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
4655
  ////  one TX buffer decriptor ( 100Mbps ).                      ////
4656
  ////                                                            ////
4657
  ////////////////////////////////////////////////////////////////////
4658 209 tadejm
  if (test_num == 3) // with and without padding
4659 194 tadej
  begin
4660
    // TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
4661
    test_name = "TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )";
4662
    `TIME; $display("  TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )");
4663
 
4664
    max_tmp = 0;
4665
    min_tmp = 0;
4666
    // set one TX buffer descriptor - must be set before TX enable
4667
    wbm_write(`ETH_TX_BD_NUM, 32'h1, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4668 209 tadejm
    // enable TX, set full-duplex mode, NO padding and CRC appending
4669
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4670 194 tadej
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4671
    // prepare two packets of MAXFL length
4672
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4673
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
4674
    min_tmp = tmp[31:16];
4675
    st_data = 8'h5A;
4676 209 tadejm
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
4677 194 tadej
    st_data = 8'h10;
4678 209 tadejm
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
4679 169 mohor
    // check WB INT signal
4680 192 tadej
    if (wb_int !== 1'b0)
4681 169 mohor
    begin
4682
      test_fail("WB INT signal should not be set");
4683
      fail = fail + 1;
4684
    end
4685 194 tadej
 
4686
    // write to phy's control register for 100Mbps
4687
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
4688
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
4689
    speed = 100;
4690 192 tadej
 
4691 194 tadej
    i_length = (min_tmp - 4);
4692
    while (i_length <= (max_tmp - 4))
4693 192 tadej
    begin
4694 194 tadej
      // choose generating carrier sense and collision
4695
      case (i_length[1:0])
4696
      2'h0: // Interrupt is generated
4697 192 tadej
      begin
4698 194 tadej
        // enable interrupt generation
4699 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4700 194 tadej
        // unmask interrupts
4701 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4702 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4703
        // not detect carrier sense in FD and no collision
4704
        eth_phy.carrier_sense_tx_fd_detect(0);
4705
        eth_phy.collision(0);
4706 192 tadej
      end
4707 194 tadej
      2'h1: // Interrupt is not generated
4708 192 tadej
      begin
4709 194 tadej
        // enable interrupt generation
4710 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4711 194 tadej
        // mask interrupts
4712
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4713
        // detect carrier sense in FD and no collision
4714
        eth_phy.carrier_sense_tx_fd_detect(1);
4715
        eth_phy.collision(0);
4716 192 tadej
      end
4717 194 tadej
      2'h2: // Interrupt is not generated
4718
      begin
4719
        // disable interrupt generation
4720 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
4721 194 tadej
        // unmask interrupts
4722 209 tadejm
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
4723 194 tadej
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4724
        // not detect carrier sense in FD and set collision
4725
        eth_phy.carrier_sense_tx_fd_detect(0);
4726
        eth_phy.collision(1);
4727
      end
4728
      default: // 2'h3: // Interrupt is not generated
4729
      begin
4730
        // disable interrupt generation
4731 209 tadejm
        set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
4732 194 tadej
        // mask interrupts
4733
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4734
        // detect carrier sense in FD and set collision
4735
        eth_phy.carrier_sense_tx_fd_detect(1);
4736
        eth_phy.collision(1);
4737
      end
4738
      endcase
4739
      eth_phy.set_tx_mem_addr(max_tmp);
4740
      // set wrap bit
4741
      set_tx_bd_wrap(0);
4742
      set_tx_bd_ready(0, 0);
4743 192 tadej
      #1 check_tx_bd(0, data);
4744 194 tadej
      if (i_length < min_tmp) // just first four
4745 192 tadej
      begin
4746 194 tadej
        while (data[15] === 1)
4747
        begin
4748
          #1 check_tx_bd(0, data);
4749
          @(posedge wb_clk);
4750
        end
4751 209 tadejm
        repeat (1) @(posedge wb_clk);
4752 194 tadej
      end
4753
      else if (i_length > (max_tmp - 8)) // just last four
4754
      begin
4755
        tmp = 0;
4756
        wait (MTxEn === 1'b1); // start transmit
4757
        while (tmp < (i_length - 20))
4758
        begin
4759
          #1 tmp = tmp + 1;
4760
          @(posedge wb_clk);
4761
        end
4762 192 tadej
        #1 check_tx_bd(0, data);
4763 194 tadej
        while (data[15] === 1)
4764
        begin
4765
          #1 check_tx_bd(0, data);
4766
          @(posedge wb_clk);
4767
        end
4768 209 tadejm
        repeat (1) @(posedge wb_clk);
4769 192 tadej
      end
4770 194 tadej
      else
4771
      begin
4772
        wait (MTxEn === 1'b1); // start transmit
4773
        #1 check_tx_bd(0, data);
4774
        if (data[15] !== 1)
4775
        begin
4776
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
4777
          fail = fail + 1;
4778
        end
4779
        wait (MTxEn === 1'b0); // end transmit
4780
        while (data[15] === 1)
4781
        begin
4782
          #1 check_tx_bd(0, data);
4783
          @(posedge wb_clk);
4784
        end
4785
        repeat (1) @(posedge wb_clk);
4786
      end
4787
      // check length of a PACKET
4788
      if (eth_phy.tx_len != (i_length + 4))
4789
      begin
4790
        test_fail("Wrong length of the packet out from MAC");
4791
        fail = fail + 1;
4792
      end
4793 192 tadej
      // check transmitted TX packet data
4794
      if (i_length[0] == 0)
4795
      begin
4796 209 tadejm
        check_tx_packet((`MEMORY_BASE + i_length[1:0]), max_tmp, i_length, tmp);
4797 192 tadej
      end
4798
      else
4799
      begin
4800 209 tadejm
        check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
4801 192 tadej
      end
4802
      if (tmp > 0)
4803
      begin
4804
        test_fail("Wrong data of the transmitted packet");
4805
        fail = fail + 1;
4806
      end
4807
      // check transmited TX packet CRC
4808
      check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
4809
      if (tmp > 0)
4810
      begin
4811
        test_fail("Wrong CRC of the transmitted packet");
4812
        fail = fail + 1;
4813
      end
4814 194 tadej
      // check WB INT signal
4815
      if (i_length[1:0] == 2'h0)
4816 192 tadej
      begin
4817 194 tadej
        if (wb_int !== 1'b1)
4818
        begin
4819
          `TIME; $display("*E WB INT signal should be set");
4820
          test_fail("WB INT signal should be set");
4821
          fail = fail + 1;
4822
        end
4823 192 tadej
      end
4824 194 tadej
      else
4825 192 tadej
      begin
4826 194 tadej
        if (wb_int !== 1'b0)
4827
        begin
4828
          `TIME; $display("*E WB INT signal should not be set");
4829
          test_fail("WB INT signal should not be set");
4830
          fail = fail + 1;
4831
        end
4832 192 tadej
      end
4833 194 tadej
      // check TX buffer descriptor of a packet
4834
      check_tx_bd(0, data);
4835
      if (i_length[1] == 1'b0) // interrupt enabled
4836 192 tadej
      begin
4837 194 tadej
        if (data[15:0] !== 16'h7800)
4838
        begin
4839
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4840
          test_fail("TX buffer descriptor status is not correct");
4841
          fail = fail + 1;
4842
        end
4843 192 tadej
      end
4844 194 tadej
      else // interrupt not enabled
4845 192 tadej
      begin
4846 194 tadej
        if (data[15:0] !== 16'h3800)
4847
        begin
4848
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
4849
          test_fail("TX buffer descriptor status is not correct");
4850
          fail = fail + 1;
4851
        end
4852 192 tadej
      end
4853 194 tadej
      // clear TX buffer descriptor
4854
      clear_tx_bd(0, 0);
4855
      // check interrupts
4856
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4857
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
4858 192 tadej
      begin
4859 194 tadej
        if ((data & `ETH_INT_TXB) !== 1'b1)
4860
        begin
4861
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
4862
          test_fail("Interrupt Transmit Buffer was not set");
4863
          fail = fail + 1;
4864
        end
4865
        if ((data & (~`ETH_INT_TXB)) !== 0)
4866
        begin
4867
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
4868
          test_fail("Other interrupts (except Transmit Buffer) were set");
4869
          fail = fail + 1;
4870
        end
4871 192 tadej
      end
4872 194 tadej
      else
4873 192 tadej
      begin
4874 194 tadej
        if (data !== 0)
4875
        begin
4876
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h", data);
4877
          test_fail("Any of interrupts (except Transmit Buffer) was set");
4878
          fail = fail + 1;
4879
        end
4880 192 tadej
      end
4881 194 tadej
      // clear interrupts
4882
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4883
      // check WB INT signal
4884
      if (wb_int !== 1'b0)
4885 192 tadej
      begin
4886 194 tadej
        test_fail("WB INT signal should not be set");
4887 192 tadej
        fail = fail + 1;
4888
      end
4889 194 tadej
      // INTERMEDIATE DISPLAYS
4890
      if ((i_length + 4) == (min_tmp + 64))
4891 209 tadejm
      begin
4892 194 tadej
        // starting length is min_tmp, ending length is (min_tmp + 64)
4893 209 tadejm
        $display("    pads appending to packets is NOT selected");
4894
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
4895 194 tadej
                 min_tmp, (min_tmp + 64));
4896 209 tadejm
        // set padding, remain the rest
4897
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4898
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4899
      end
4900 194 tadej
      else if ((i_length + 4) == (max_tmp - 16))
4901 209 tadejm
      begin
4902 194 tadej
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
4903 209 tadejm
        $display("    pads appending to packets is selected");
4904
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
4905 194 tadej
                 (min_tmp + 64 + 128), tmp_data);
4906 209 tadejm
        // reset padding, remain the rest
4907
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4908
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4909
      end
4910 194 tadej
      else if ((i_length + 4) == max_tmp)
4911 209 tadejm
      begin
4912
        $display("    pads appending to packets is NOT selected");
4913
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
4914 194 tadej
                 (max_tmp - (4 + 16)), max_tmp);
4915 209 tadejm
      end
4916 194 tadej
      // set length (loop variable)
4917
      if ((i_length + 4) < (min_tmp + 64))
4918
        i_length = i_length + 1;
4919
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
4920
      begin
4921
        i_length = i_length + 128;
4922
        tmp_data = i_length + 4; // last tmp_data is ending length
4923
      end
4924
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
4925
        i_length = max_tmp - (4 + 16);
4926
      else if ((i_length + 4) >= (max_tmp - 16))
4927
        i_length = i_length + 1;
4928 192 tadej
      else
4929 194 tadej
      begin
4930
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
4931
        #10 $stop;
4932
      end
4933 179 mohor
    end
4934 194 tadej
    // disable TX
4935
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
4936
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4937
    if(fail == 0)
4938
      test_ok;
4939
    else
4940
      fail = 0;
4941 169 mohor
  end
4942
 
4943
 
4944 209 tadejm
  ////////////////////////////////////////////////////////////////////
4945
  ////                                                            ////
4946
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
4947
  ////  maximum TX buffer decriptors ( 10Mbps ).                  ////
4948
  ////                                                            ////
4949
  ////////////////////////////////////////////////////////////////////
4950
  if (test_num == 4) // without and with padding
4951
  begin
4952
    // TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )
4953
    test_name = "TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )";
4954
    `TIME; $display("  TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )");
4955
 
4956
    // reset MAC registers
4957
    hard_reset;
4958
    // reset MAC and MII LOGIC with soft reset
4959
    reset_mac;
4960
    reset_mii;
4961
    // set wb slave response
4962
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
4963 192 tadej
 
4964 209 tadejm
    max_tmp = 0;
4965
    min_tmp = 0;
4966
    num_of_frames = 0;
4967
    num_of_bd = 0;
4968
    // set maximum TX buffer descriptors (128) - must be set before TX enable
4969
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4970
    // enable TX, set full-duplex mode, NO padding and CRC appending
4971
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
4972
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4973
    // prepare two packets of MAXFL length
4974
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
4975
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
4976
    min_tmp = tmp[31:16];
4977
    st_data = 8'hA3;
4978
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
4979
    st_data = 8'h81;
4980
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
4981
    // check WB INT signal
4982
    if (wb_int !== 1'b0)
4983
    begin
4984
      test_fail("WB INT signal should not be set");
4985
      fail = fail + 1;
4986
    end
4987
 
4988
    // write to phy's control register for 10Mbps
4989
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
4990
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
4991
    speed = 10;
4992
 
4993
    i_length = (min_tmp - 4);
4994
    while (i_length <= (max_tmp - 4))
4995
    begin
4996
      // choose generating carrier sense and collision
4997
      case (i_length[1:0])
4998
      2'h0: // Interrupt is generated
4999
      begin
5000
        // Reset_tx_bd nable interrupt generation
5001
        // unmask interrupts
5002
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5003
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5004
        // not detect carrier sense in FD and no collision
5005
        eth_phy.carrier_sense_tx_fd_detect(0);
5006
        eth_phy.collision(0);
5007
      end
5008
      2'h1: // Interrupt is not generated
5009
      begin
5010
        // set_tx_bd enable interrupt generation
5011
        // mask interrupts
5012
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5013
        // detect carrier sense in FD and no collision
5014
        eth_phy.carrier_sense_tx_fd_detect(1);
5015
        eth_phy.collision(0);
5016
      end
5017
      2'h2: // Interrupt is not generated
5018
      begin
5019
        // set_tx_bd disable the interrupt generation
5020
        // unmask interrupts
5021
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5022
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5023
        // not detect carrier sense in FD and set collision
5024
        eth_phy.carrier_sense_tx_fd_detect(0);
5025
        eth_phy.collision(1);
5026
      end
5027
      default: // 2'h3: // Interrupt is not generated
5028
      begin
5029
        // set_tx_bd disable the interrupt generation
5030
        // mask interrupts
5031
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5032
        // detect carrier sense in FD and set collision
5033
        eth_phy.carrier_sense_tx_fd_detect(1);
5034
        eth_phy.collision(1);
5035
      end
5036
      endcase
5037
      // first destination address on ethernet PHY
5038
      if (i_length[0] == 0)
5039
        eth_phy.set_tx_mem_addr(0);
5040
      else
5041
        eth_phy.set_tx_mem_addr(max_tmp);
5042
      // first 8 frames are transmitted with TX BD 0 (wrap bit on TX BD 0)
5043
      // number of all frames is 154 (146 without first 8)
5044
      if (num_of_frames < 8)
5045
      begin
5046
        case (i_length[1:0])
5047
        2'h0: // Interrupt is generated
5048
        begin
5049
          // enable interrupt generation
5050
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5051
          // interrupts are unmasked
5052
        end
5053
        2'h1: // Interrupt is not generated
5054
        begin
5055
          // enable interrupt generation
5056
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5057
          // interrupts are masked
5058
        end
5059
        2'h2: // Interrupt is not generated
5060
        begin
5061
          // disable interrupt generation
5062
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5063
          // interrupts are unmasked
5064
        end
5065
        default: // 2'h3: // Interrupt is not generated
5066
        begin
5067
          // disable interrupt generation
5068
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5069
          // interrupts are masked
5070
        end
5071
        endcase
5072
        // set wrap bit
5073
        set_tx_bd_wrap(0);
5074
      end
5075
      // after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
5076
      else if ((num_of_frames - 8) == 0)
5077
      begin
5078
        tmp_len = i_length; // length of frame
5079
        tmp_bd_num = 0; // TX BD number
5080
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5081
        begin
5082
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5083
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5084
          if (tmp_len[0] == 0)
5085
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5086
          else
5087
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5088
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5089
          if ((tmp_len + 4) < (min_tmp + 128))
5090
            tmp_len = tmp_len + 1;
5091
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5092
            tmp_len = 256;
5093
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5094
            tmp_len = tmp_len + 128;
5095
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5096
            tmp_len = max_tmp - (4 + 16);
5097
          else if ((tmp_len + 4) >= (max_tmp - 16))
5098
            tmp_len = tmp_len + 1;
5099
          // set TX BD number
5100
          tmp_bd_num = tmp_bd_num + 1;
5101
        end
5102
        // set wrap bit
5103
        set_tx_bd_wrap(127);
5104
      end
5105
      // after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
5106
      else if ((num_of_frames - 8) == 20) // 128
5107
      begin
5108
        tmp_len = tmp_len; // length of frame remaines from previous settings
5109
        tmp_bd_num = 0; // TX BD number
5110
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5111
        begin
5112
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5113
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5114
          if (tmp_len[0] == 0)
5115
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5116
          else
5117
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5118
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5119
          if ((tmp_len + 4) < (min_tmp + 128))
5120
            tmp_len = tmp_len + 1;
5121
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5122
            tmp_len = 256;
5123
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5124
            tmp_len = tmp_len + 128;
5125
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5126
            tmp_len = max_tmp - (4 + 16);
5127
          else if ((tmp_len + 4) >= (max_tmp - 16))
5128
            tmp_len = tmp_len + 1;
5129
          // set TX BD number
5130
          tmp_bd_num = tmp_bd_num + 1;
5131
        end
5132
      end
5133
      // set ready bit
5134
      if (num_of_frames < 8)
5135
        set_tx_bd_ready(0, 0);
5136
      else if ((num_of_frames - 8) < 128)
5137
        set_tx_bd_ready((num_of_frames - 8), (num_of_frames - 8));
5138
      else if ((num_of_frames - 136) < 19)
5139
        set_tx_bd_ready((num_of_frames - 136), (num_of_frames - 136));
5140
      // CHECK END OF TRANSMITION
5141
      #1 check_tx_bd(num_of_bd, data);
5142
      if (i_length < min_tmp) // just first four
5143
      begin
5144
        while (data[15] === 1)
5145
        begin
5146
          #1 check_tx_bd(num_of_bd, data);
5147
          @(posedge wb_clk);
5148
        end
5149
        repeat (1) @(posedge wb_clk);
5150
      end
5151
      else if (i_length > (max_tmp - 8)) // just last four
5152
      begin
5153
        tmp = 0;
5154
        wait (MTxEn === 1'b1); // start transmit
5155
        while (tmp < (i_length - 20))
5156
        begin
5157
          #1 tmp = tmp + 1;
5158
          @(posedge wb_clk);
5159
        end
5160
        #1 check_tx_bd(num_of_bd, data);
5161
        while (data[15] === 1)
5162
        begin
5163
          #1 check_tx_bd(num_of_bd, data);
5164
          @(posedge wb_clk);
5165
        end
5166
        repeat (1) @(posedge wb_clk);
5167
      end
5168
      else
5169
      begin
5170
        wait (MTxEn === 1'b1); // start transmit
5171
        #1 check_tx_bd(num_of_bd, data);
5172
        if (data[15] !== 1)
5173
        begin
5174
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
5175
          fail = fail + 1;
5176
        end
5177
        wait (MTxEn === 1'b0); // end transmit
5178
        while (data[15] === 1)
5179
        begin
5180
          #1 check_tx_bd(num_of_bd, data);
5181
          @(posedge wb_clk);
5182
        end
5183
        repeat (1) @(posedge wb_clk);
5184
      end
5185
      // check length of a PACKET
5186
      if (eth_phy.tx_len != (i_length + 4))
5187
      begin
5188
        test_fail("Wrong length of the packet out from MAC");
5189
        fail = fail + 1;
5190
      end
5191
        // check transmitted TX packet data
5192
        if (i_length[0] == 0)
5193
        begin
5194
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), 0, i_length, tmp);
5195
        end
5196
        else
5197
        begin
5198
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
5199
        end
5200
        if (tmp > 0)
5201
        begin
5202
          test_fail("Wrong data of the transmitted packet");
5203
          fail = fail + 1;
5204
        end
5205
        // check transmited TX packet CRC
5206
        if (i_length[0] == 0)
5207
          check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
5208
        else
5209
          check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
5210
        if (tmp > 0)
5211
        begin
5212
          test_fail("Wrong CRC of the transmitted packet");
5213
          fail = fail + 1;
5214
        end
5215
      // check WB INT signal
5216
      if (i_length[1:0] == 2'h0)
5217
      begin
5218
        if (wb_int !== 1'b1)
5219
        begin
5220
          `TIME; $display("*E WB INT signal should be set");
5221
          test_fail("WB INT signal should be set");
5222
          fail = fail + 1;
5223
        end
5224
      end
5225
      else
5226
      begin
5227
        if (wb_int !== 1'b0)
5228
        begin
5229
          `TIME; $display("*E WB INT signal should not be set");
5230
          test_fail("WB INT signal should not be set");
5231
          fail = fail + 1;
5232
        end
5233
      end
5234
      // check TX buffer descriptor of a packet
5235
      check_tx_bd(num_of_bd, data);
5236
      if (i_length[1] == 1'b0) // interrupt enabled
5237
      begin
5238
        if ( ((data[15:0] !== 16'h7800) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5239
             ((data[15:0] !== 16'h5800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5240
        begin
5241
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5242
          test_fail("TX buffer descriptor status is not correct");
5243
          fail = fail + 1;
5244
        end
5245
      end
5246
      else // interrupt not enabled
5247
      begin
5248
        if ( ((data[15:0] !== 16'h3800)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5249
             ((data[15:0] !== 16'h1800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5250
        begin
5251
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5252
          test_fail("TX buffer descriptor status is not correct");
5253
          fail = fail + 1;
5254
        end
5255
      end
5256
      // clear first half of 8 frames from TX buffer descriptor 0
5257
      if (num_of_frames < 4)
5258
        clear_tx_bd(num_of_bd, num_of_bd);
5259
      // clear BD with wrap bit
5260
      if (num_of_frames == 140)
5261
        clear_tx_bd(127, 127);
5262
      // check interrupts
5263
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5264
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
5265
      begin
5266
        if ((data & `ETH_INT_TXB) !== 1'b1)
5267
        begin
5268
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
5269
          test_fail("Interrupt Transmit Buffer was not set");
5270
          fail = fail + 1;
5271
        end
5272
        if ((data & (~`ETH_INT_TXB)) !== 0)
5273
        begin
5274
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
5275
          test_fail("Other interrupts (except Transmit Buffer) were set");
5276
          fail = fail + 1;
5277
        end
5278
      end
5279
      else
5280
      begin
5281
        if (data !== 0)
5282
        begin
5283
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
5284
          test_fail("Any of interrupts (except Transmit Buffer) was set");
5285
          fail = fail + 1;
5286
        end
5287
      end
5288
      // clear interrupts
5289
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5290
      // check WB INT signal
5291
      if (wb_int !== 1'b0)
5292
      begin
5293
        test_fail("WB INT signal should not be set");
5294
        fail = fail + 1;
5295
      end
5296
      // INTERMEDIATE DISPLAYS
5297
      if ((i_length + 4) == (min_tmp + 7))
5298
      begin
5299
        // starting length is min_tmp, ending length is (min_tmp + 128)
5300
        $display("    pads appending to packets is NOT selected");
5301
        $display("    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)");
5302
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
5303
                 min_tmp, (min_tmp + 7));
5304
        $display("    ->all packets were send from TX BD 0");
5305
        // set padding, remain the rest
5306
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5307
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5308
      end
5309
      else if ((i_length + 4) == (min_tmp + 128))
5310
      begin
5311
        // starting length is min_tmp, ending length is (min_tmp + 128)
5312
        $display("    pads appending to packets is NOT selected");
5313
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5314
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
5315
                 (min_tmp + 8), (min_tmp + 128));
5316
        $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5317
                 1'b0, num_of_bd);
5318
        tmp_bd = num_of_bd + 1;
5319
        // set padding, remain the rest
5320
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5321
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5322
      end
5323
      else if ((i_length + 4) == (max_tmp - 16))
5324
      begin
5325
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
5326
        $display("    pads appending to packets is selected");
5327
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5328
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
5329
                 (min_tmp + 64 + 128), tmp_data);
5330
        if (tmp_bd > num_of_bd)
5331
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5332
                   tmp_bd, num_of_bd);
5333
        else
5334
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5335
                   tmp_bd, num_of_bd);
5336
        tmp_bd = num_of_bd + 1;
5337
        // reset padding, remain the rest
5338
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5339
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5340
      end
5341
      else if ((i_length + 4) == max_tmp)
5342
      begin
5343
        $display("    pads appending to packets is NOT selected");
5344
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5345
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
5346
                 (max_tmp - (4 + 16)), max_tmp);
5347
        if (tmp_bd > num_of_bd)
5348
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5349
                   tmp_bd, num_of_bd);
5350
        else
5351
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5352
                   tmp_bd, num_of_bd);
5353
      end
5354
      // set length (loop variable)
5355
      if ((i_length + 4) < (min_tmp + 128))
5356
        i_length = i_length + 1;
5357
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5358
        i_length = 256;
5359
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5360
      begin
5361
        i_length = i_length + 128;
5362
        tmp_data = i_length + 4; // last tmp_data is ending length
5363
      end
5364
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
5365
        i_length = max_tmp - (4 + 16);
5366
      else if ((i_length + 4) >= (max_tmp - 16))
5367
        i_length = i_length + 1;
5368
      else
5369
      begin
5370
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
5371
        #10 $stop;
5372
      end
5373
      // the number of frame transmitted
5374
      num_of_frames = num_of_frames + 1;
5375
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
5376
        num_of_bd = 0;
5377
      else
5378
        num_of_bd = num_of_bd + 1;
5379
    end
5380
    // disable TX
5381
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5382
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5383
    @(posedge wb_clk);
5384
    if(fail == 0)
5385
      test_ok;
5386
    else
5387
      fail = 0;
5388
  end
5389
 
5390
 
5391
  ////////////////////////////////////////////////////////////////////
5392
  ////                                                            ////
5393
  ////  Test transmit packets form MINFL to MAXFL sizes at        ////
5394
  ////  maximum TX buffer decriptors ( 100Mbps ).                 ////
5395
  ////                                                            ////
5396
  ////////////////////////////////////////////////////////////////////
5397
  if (test_num == 5) // with and without padding
5398
  begin
5399
    // TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )
5400
    test_name = "TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )";
5401
    `TIME; $display("  TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )");
5402
 
5403
    // reset MAC registers
5404
    hard_reset;
5405
    // reset MAC and MII LOGIC with soft reset
5406
    reset_mac;
5407
    reset_mii;
5408
    // set wb slave response
5409
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
5410
 
5411
    max_tmp = 0;
5412
    min_tmp = 0;
5413
    num_of_frames = 0;
5414
    num_of_bd = 0;
5415
    // set maximum TX buffer descriptors (128) - must be set before TX enable
5416
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5417
    // enable TX, set full-duplex mode, NO padding and CRC appending
5418
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5419
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5420
    // prepare two packets of MAXFL length
5421
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5422
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
5423
    min_tmp = tmp[31:16];
5424
    st_data = 8'hA5;
5425
    set_tx_packet(`MEMORY_BASE, (max_tmp), st_data); // length without CRC
5426
    st_data = 8'h71;
5427
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp), st_data); // length without CRC
5428
    // check WB INT signal
5429
    if (wb_int !== 1'b0)
5430
    begin
5431
      test_fail("WB INT signal should not be set");
5432
      fail = fail + 1;
5433
    end
5434
 
5435
    // write to phy's control register for 100Mbps
5436
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
5437
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
5438
    speed = 100;
5439
 
5440
    i_length = (min_tmp - 4);
5441
    while (i_length <= (max_tmp - 4))
5442
    begin
5443
      // choose generating carrier sense and collision
5444
      case (i_length[1:0])
5445
      2'h0: // Interrupt is generated
5446
      begin
5447
        // Reset_tx_bd nable interrupt generation
5448
        // unmask interrupts
5449
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5450
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5451
        // not detect carrier sense in FD and no collision
5452
        eth_phy.carrier_sense_tx_fd_detect(0);
5453
        eth_phy.collision(0);
5454
      end
5455
      2'h1: // Interrupt is not generated
5456
      begin
5457
        // set_tx_bd enable interrupt generation
5458
        // mask interrupts
5459
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5460
        // detect carrier sense in FD and no collision
5461
        eth_phy.carrier_sense_tx_fd_detect(1);
5462
        eth_phy.collision(0);
5463
      end
5464
      2'h2: // Interrupt is not generated
5465
      begin
5466
        // set_tx_bd disable the interrupt generation
5467
        // unmask interrupts
5468
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5469
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5470
        // not detect carrier sense in FD and set collision
5471
        eth_phy.carrier_sense_tx_fd_detect(0);
5472
        eth_phy.collision(1);
5473
      end
5474
      default: // 2'h3: // Interrupt is not generated
5475
      begin
5476
        // set_tx_bd disable the interrupt generation
5477
        // mask interrupts
5478
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5479
        // detect carrier sense in FD and set collision
5480
        eth_phy.carrier_sense_tx_fd_detect(1);
5481
        eth_phy.collision(1);
5482
      end
5483
      endcase
5484
      // first destination address on ethernet PHY
5485
      if (i_length[0] == 0)
5486
        eth_phy.set_tx_mem_addr(0);
5487
      else
5488
        eth_phy.set_tx_mem_addr(max_tmp);
5489
      // first 8 frames are transmitted with TX BD 0 (wrap bit on TX BD 0)
5490
      // number of all frames is 154 (146 without first 8)
5491
      if (num_of_frames < 8)
5492
      begin
5493
        case (i_length[1:0])
5494
        2'h0: // Interrupt is generated
5495
        begin
5496
          // enable interrupt generation
5497
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5498
          // interrupts are unmasked
5499
        end
5500
        2'h1: // Interrupt is not generated
5501
        begin
5502
          // enable interrupt generation
5503
          set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5504
          // interrupts are masked
5505
        end
5506
        2'h2: // Interrupt is not generated
5507
        begin
5508
          // disable interrupt generation
5509
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, (`MEMORY_BASE + i_length[1:0]));
5510
          // interrupts are unmasked
5511
        end
5512
        default: // 2'h3: // Interrupt is not generated
5513
        begin
5514
          // disable interrupt generation
5515
          set_tx_bd(0, 0, i_length, 1'b0, 1'b1, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
5516
          // interrupts are masked
5517
        end
5518
        endcase
5519
        // set wrap bit
5520
        set_tx_bd_wrap(0);
5521
      end
5522
      // after first 8 number of frames, 128 frames form TX BD 0 to 127 will be transmitted
5523
      else if ((num_of_frames - 8) == 0)
5524
      begin
5525
        tmp_len = i_length; // length of frame
5526
        tmp_bd_num = 0; // TX BD number
5527
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5528
        begin
5529
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5530
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5531
          if (tmp_len[0] == 0)
5532
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5533
          else
5534
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5535
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5536
          if ((tmp_len + 4) < (min_tmp + 128))
5537
            tmp_len = tmp_len + 1;
5538
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5539
            tmp_len = 256;
5540
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5541
            tmp_len = tmp_len + 128;
5542
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5543
            tmp_len = max_tmp - (4 + 16);
5544
          else if ((tmp_len + 4) >= (max_tmp - 16))
5545
            tmp_len = tmp_len + 1;
5546
          // set TX BD number
5547
          tmp_bd_num = tmp_bd_num + 1;
5548
        end
5549
        // set wrap bit
5550
        set_tx_bd_wrap(127);
5551
      end
5552
      // after 128 + first 8 number of frames, 19 frames form TX BD 0 to 18 will be transmitted
5553
      else if ((num_of_frames - 8) == 20) // 128
5554
      begin
5555
        tmp_len = tmp_len; // length of frame remaines from previous settings
5556
        tmp_bd_num = 0; // TX BD number
5557
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
5558
        begin
5559
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5560
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5561
          if (tmp_len[0] == 0)
5562
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
5563
          else
5564
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
5565
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
5566
          if ((tmp_len + 4) < (min_tmp + 128))
5567
            tmp_len = tmp_len + 1;
5568
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5569
            tmp_len = 256;
5570
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
5571
            tmp_len = tmp_len + 128;
5572
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
5573
            tmp_len = max_tmp - (4 + 16);
5574
          else if ((tmp_len + 4) >= (max_tmp - 16))
5575
            tmp_len = tmp_len + 1;
5576
          // set TX BD number
5577
          tmp_bd_num = tmp_bd_num + 1;
5578
        end
5579
      end
5580
      // set ready bit
5581
      if (num_of_frames < 8)
5582
        set_tx_bd_ready(0, 0);
5583
      else if ((num_of_frames - 8) < 128)
5584
        set_tx_bd_ready((num_of_frames - 8), (num_of_frames - 8));
5585
      else if ((num_of_frames - 136) < 19)
5586
        set_tx_bd_ready((num_of_frames - 136), (num_of_frames - 136));
5587
      // CHECK END OF TRANSMITION
5588
      #1 check_tx_bd(num_of_bd, data);
5589
      if (i_length < min_tmp) // just first four
5590
      begin
5591
        while (data[15] === 1)
5592
        begin
5593
          #1 check_tx_bd(num_of_bd, data);
5594
          @(posedge wb_clk);
5595
        end
5596
        repeat (1) @(posedge wb_clk);
5597
      end
5598
      else if (i_length > (max_tmp - 8)) // just last four
5599
      begin
5600
        tmp = 0;
5601
        wait (MTxEn === 1'b1); // start transmit
5602
        while (tmp < (i_length - 20))
5603
        begin
5604
          #1 tmp = tmp + 1;
5605
          @(posedge wb_clk);
5606
        end
5607
        #1 check_tx_bd(num_of_bd, data);
5608
        while (data[15] === 1)
5609
        begin
5610
          #1 check_tx_bd(num_of_bd, data);
5611
          @(posedge wb_clk);
5612
        end
5613
        repeat (1) @(posedge wb_clk);
5614
      end
5615
      else
5616
      begin
5617
        wait (MTxEn === 1'b1); // start transmit
5618
        #1 check_tx_bd(num_of_bd, data);
5619
        if (data[15] !== 1)
5620
        begin
5621
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
5622
          fail = fail + 1;
5623
        end
5624
        wait (MTxEn === 1'b0); // end transmit
5625
        while (data[15] === 1)
5626
        begin
5627
          #1 check_tx_bd(num_of_bd, data);
5628
          @(posedge wb_clk);
5629
        end
5630
        repeat (1) @(posedge wb_clk);
5631
      end
5632
      // check length of a PACKET
5633
      if (eth_phy.tx_len != (i_length + 4))
5634
      begin
5635
        test_fail("Wrong length of the packet out from MAC");
5636
        fail = fail + 1;
5637
      end
5638
      // checking in the following if statement is performed only for first and last 64 lengths
5639
        // check transmitted TX packet data
5640
        if (i_length[0] == 0)
5641
        begin
5642
          check_tx_packet((`MEMORY_BASE + i_length[1:0]), 0, i_length, tmp);
5643
        end
5644
        else
5645
        begin
5646
          check_tx_packet(((`MEMORY_BASE + i_length[1:0]) + max_tmp), max_tmp, i_length, tmp);
5647
        end
5648
        if (tmp > 0)
5649
        begin
5650
          test_fail("Wrong data of the transmitted packet");
5651
          fail = fail + 1;
5652
        end
5653
        // check transmited TX packet CRC
5654
        if (i_length[0] == 0)
5655
          check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
5656
        else
5657
          check_tx_crc(max_tmp, i_length, 1'b0, tmp); // length without CRC
5658
        if (tmp > 0)
5659
        begin
5660
          test_fail("Wrong CRC of the transmitted packet");
5661
          fail = fail + 1;
5662
        end
5663
      // check WB INT signal
5664
      if (i_length[1:0] == 2'h0)
5665
      begin
5666
        if (wb_int !== 1'b1)
5667
        begin
5668
          `TIME; $display("*E WB INT signal should be set");
5669
          test_fail("WB INT signal should be set");
5670
          fail = fail + 1;
5671
        end
5672
      end
5673
      else
5674
      begin
5675
        if (wb_int !== 1'b0)
5676
        begin
5677
          `TIME; $display("*E WB INT signal should not be set");
5678
          test_fail("WB INT signal should not be set");
5679
          fail = fail + 1;
5680
        end
5681
      end
5682
      // check TX buffer descriptor of a packet
5683
      check_tx_bd(num_of_bd, data);
5684
      if (i_length[1] == 1'b0) // interrupt enabled
5685
      begin
5686
        if ( ((data[15:0] !== 16'h7800) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5687
             ((data[15:0] !== 16'h5800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5688
        begin
5689
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5690
          test_fail("TX buffer descriptor status is not correct");
5691
          fail = fail + 1;
5692
        end
5693
      end
5694
      else // interrupt not enabled
5695
      begin
5696
        if ( ((data[15:0] !== 16'h3800)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
5697
             ((data[15:0] !== 16'h1800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
5698
        begin
5699
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
5700
          test_fail("TX buffer descriptor status is not correct");
5701
          fail = fail + 1;
5702
        end
5703
      end
5704
      // clear first half of 8 frames from TX buffer descriptor 0
5705
      if (num_of_frames < 4)
5706
        clear_tx_bd(num_of_bd, num_of_bd);
5707
      // clear BD with wrap bit
5708
      if (num_of_frames == 140)
5709
        clear_tx_bd(127, 127);
5710
      // check interrupts
5711
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5712
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
5713
      begin
5714
        if ((data & `ETH_INT_TXB) !== 1'b1)
5715
        begin
5716
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
5717
          test_fail("Interrupt Transmit Buffer was not set");
5718
          fail = fail + 1;
5719
        end
5720
        if ((data & (~`ETH_INT_TXB)) !== 0)
5721
        begin
5722
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
5723
          test_fail("Other interrupts (except Transmit Buffer) were set");
5724
          fail = fail + 1;
5725
        end
5726
      end
5727
      else
5728
      begin
5729
        if (data !== 0)
5730
        begin
5731
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
5732
          test_fail("Any of interrupts (except Transmit Buffer) was set");
5733
          fail = fail + 1;
5734
        end
5735
      end
5736
      // clear interrupts
5737
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5738
      // check WB INT signal
5739
      if (wb_int !== 1'b0)
5740
      begin
5741
        test_fail("WB INT signal should not be set");
5742
        fail = fail + 1;
5743
      end
5744
      // INTERMEDIATE DISPLAYS
5745
      if ((i_length + 4) == (min_tmp + 7))
5746
      begin
5747
        // starting length is min_tmp, ending length is (min_tmp + 128)
5748
        $display("    pads appending to packets is NOT selected");
5749
        $display("    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)");
5750
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
5751
                 min_tmp, (min_tmp + 7));
5752
        $display("    ->all packets were send from TX BD 0");
5753
        // set padding, remain the rest
5754
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5755
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5756
      end
5757
      else if ((i_length + 4) == (min_tmp + 128))
5758
      begin
5759
        // starting length is min_tmp, ending length is (min_tmp + 128)
5760
        $display("    pads appending to packets is NOT selected");
5761
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5762
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
5763
                 (min_tmp + 8), (min_tmp + 128));
5764
        $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5765
                 1'b0, num_of_bd);
5766
        tmp_bd = num_of_bd + 1;
5767
        // set padding, remain the rest
5768
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5769
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5770
      end
5771
      else if ((i_length + 4) == (max_tmp - 16))
5772
      begin
5773
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
5774
        $display("    pads appending to packets is selected");
5775
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5776
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
5777
                 (min_tmp + 64 + 128), tmp_data);
5778
        if (tmp_bd > num_of_bd)
5779
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5780
                   tmp_bd, num_of_bd);
5781
        else
5782
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5783
                   tmp_bd, num_of_bd);
5784
        tmp_bd = num_of_bd + 1;
5785
        // reset padding, remain the rest
5786
        wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5787
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5788
      end
5789
      else if ((i_length + 4) == max_tmp)
5790
      begin
5791
        $display("    pads appending to packets is NOT selected");
5792
        $display("    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)");
5793
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
5794
                 (max_tmp - (4 + 16)), max_tmp);
5795
        if (tmp_bd > num_of_bd)
5796
          $display("    ->packets were send from TX BD %0d to TX BD 127 and from TX BD 0 to TX BD %0d respectively",
5797
                   tmp_bd, num_of_bd);
5798
        else
5799
          $display("    ->packets were send from TX BD %0d to TX BD %0d respectively",
5800
                   tmp_bd, num_of_bd);
5801
      end
5802
      // set length (loop variable)
5803
      if ((i_length + 4) < (min_tmp + 128))
5804
        i_length = i_length + 1;
5805
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5806
        i_length = 256;
5807
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
5808
      begin
5809
        i_length = i_length + 128;
5810
        tmp_data = i_length + 4; // last tmp_data is ending length
5811
      end
5812
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
5813
        i_length = max_tmp - (4 + 16);
5814
      else if ((i_length + 4) >= (max_tmp - 16))
5815
        i_length = i_length + 1;
5816
      else
5817
      begin
5818
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
5819
        #10 $stop;
5820
      end
5821
      // the number of frame transmitted
5822
      num_of_frames = num_of_frames + 1;
5823
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
5824
        num_of_bd = 0;
5825
      else
5826
        num_of_bd = num_of_bd + 1;
5827
    end
5828
    // disable TX
5829
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
5830
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5831
    @(posedge wb_clk);
5832
    if(fail == 0)
5833
      test_ok;
5834
    else
5835
      fail = 0;
5836
  end
5837
 
5838
 
5839
  ////////////////////////////////////////////////////////////////////
5840
  ////                                                            ////
5841
  ////  Test transmit packets form 0 to (MINFL - 1) sizes at      ////
5842
  ////  8 TX buffer decriptors ( 10Mbps ).                        ////
5843
  ////                                                            ////
5844
  ////////////////////////////////////////////////////////////////////
5845
  if (test_num == 6) // 
5846
  begin
5847
    // TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
5848
    test_name = "TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
5849
    `TIME; $display("  TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
5850
 
5851
    // reset MAC registers
5852
    hard_reset;
5853
    // reset MAC and MII LOGIC with soft reset
5854
    reset_mac;
5855
    reset_mii;
5856
    // set wb slave response
5857
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
5858
 
5859
    max_tmp = 0;
5860
    min_tmp = 0;
5861
    // set 8 TX buffer descriptors - must be set before TX enable
5862
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5863
    // enable TX, set full-duplex mode, padding and CRC appending
5864
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
5865
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5866
    // prepare two packets of MAXFL length
5867
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5868
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
5869
    min_tmp = tmp[31:16];
5870
    st_data = 8'h12;
5871
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
5872
    st_data = 8'h34;
5873
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
5874
    // check WB INT signal
5875
    if (wb_int !== 1'b0)
5876
    begin
5877
      test_fail("WB INT signal should not be set");
5878
      fail = fail + 1;
5879
    end
5880
 
5881
    // write to phy's control register for 10Mbps
5882
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
5883
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
5884
    speed = 10;
5885
 
5886
    frame_started = 0;
5887
    num_of_frames = 0;
5888
    num_of_bd = 0;
5889
    i_length = 0; // 0;
5890
    while (i_length < 70) // (min_tmp - 4))
5891
    begin
5892
      #1;
5893
      // choose generating carrier sense and collision
5894
      case (i_length[1:0])
5895
      2'h0: // Interrupt is generated
5896
      begin
5897
        // Reset_tx_bd nable interrupt generation
5898
        // unmask interrupts
5899
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5900
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5901
        // not detect carrier sense in FD and no collision
5902
        eth_phy.carrier_sense_tx_fd_detect(0);
5903
        eth_phy.collision(0);
5904
      end
5905
      2'h1: // Interrupt is not generated
5906
      begin
5907
        // set_tx_bd enable interrupt generation
5908
        // mask interrupts
5909
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5910
        // detect carrier sense in FD and no collision
5911
        eth_phy.carrier_sense_tx_fd_detect(1);
5912
        eth_phy.collision(0);
5913
      end
5914
      2'h2: // Interrupt is not generated
5915
      begin
5916
        // set_tx_bd disable the interrupt generation
5917
        // unmask interrupts
5918
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
5919
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5920
        // not detect carrier sense in FD and set collision
5921
        eth_phy.carrier_sense_tx_fd_detect(0);
5922
        eth_phy.collision(1);
5923
      end
5924
      default: // 2'h3: // Interrupt is not generated
5925
      begin
5926
        // set_tx_bd disable the interrupt generation
5927
        // mask interrupts
5928
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
5929
        // detect carrier sense in FD and set collision
5930
        eth_phy.carrier_sense_tx_fd_detect(1);
5931
        eth_phy.collision(1);
5932
      end
5933
      endcase
5934
      #1;
5935
      // first destination address on ethernet PHY
5936
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
5937
      // SET packets and wrap bit
5938
      // num_of_frames <= 9 => wrap set to TX BD 0
5939
      if (num_of_frames <= 9)
5940
      begin
5941
        tmp_len = i_length; // length of frame
5942
        tmp_bd_num = 0; // TX BD number
5943
        // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5944
        // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5945
        if (tmp_len[0] == 0)
5946
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
5947
        else
5948
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
5949
        // set wrap bit
5950
        set_tx_bd_wrap(0);
5951
      end
5952
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
5953
      else if ((num_of_frames == 10) || (num_of_frames == 14))
5954
      begin
5955
        tmp_len = i_length; // length of frame
5956
        tmp_bd_num = 0; // TX BD number
5957
        while (tmp_bd_num < 4) //
5958
        begin
5959
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5960
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5961
          if (tmp_len[0] == 0)
5962
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
5963
          else
5964
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
5965
          tmp_len = tmp_len + 1;
5966
          // set TX BD number
5967
          tmp_bd_num = tmp_bd_num + 1;
5968
        end
5969
        // set wrap bit
5970
        set_tx_bd_wrap(3);
5971
      end
5972
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
5973
      else if ((num_of_frames == 18) || (num_of_frames == 23))
5974
      begin
5975
        tmp_len = i_length; // length of frame
5976
        tmp_bd_num = 0; // TX BD number
5977
        while (tmp_bd_num < 5) //
5978
        begin
5979
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
5980
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
5981
          if (tmp_len[0] == 0)
5982
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
5983
          else
5984
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
5985
          tmp_len = tmp_len + 1;
5986
          // set TX BD number
5987
          tmp_bd_num = tmp_bd_num + 1;
5988
        end
5989
        // set wrap bit
5990
        set_tx_bd_wrap(4);
5991
      end
5992
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
5993
      else if ((num_of_frames == 28) || (num_of_frames == 34))
5994
      begin
5995
        tmp_len = i_length; // length of frame
5996
        tmp_bd_num = 0; // TX BD number
5997
        while (tmp_bd_num < 6) //
5998
        begin
5999
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6000
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6001
          if (tmp_len[0] == 0)
6002
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6003
          else
6004
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6005
          tmp_len = tmp_len + 1;
6006
          // set TX BD number
6007
          tmp_bd_num = tmp_bd_num + 1;
6008
        end
6009
        // set wrap bit
6010
        set_tx_bd_wrap(5);
6011
      end
6012
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
6013
      else if ((num_of_frames == 40) || (num_of_frames == 47))
6014
      begin
6015
        tmp_len = i_length; // length of frame
6016
        tmp_bd_num = 0; // TX BD number
6017
        while (tmp_bd_num < 7) //
6018
        begin
6019
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6020
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6021
          if (tmp_len[0] == 0)
6022
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6023
          else
6024
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6025
          tmp_len = tmp_len + 1;
6026
          // set TX BD number
6027
          tmp_bd_num = tmp_bd_num + 1;
6028
        end
6029
        // set wrap bit
6030
        set_tx_bd_wrap(6);
6031
      end
6032
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
6033
      else if ((num_of_frames == 54) || (num_of_frames == 62))
6034
      begin
6035
        tmp_len = i_length; // length of frame
6036
        tmp_bd_num = 0; // TX BD number
6037
        while (tmp_bd_num < 8) //
6038
        begin
6039
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6040
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6041
          if (tmp_len[0] == 0)
6042
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6043
          else
6044
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6045
          tmp_len = tmp_len + 1;
6046
          // set TX BD number
6047
          tmp_bd_num = tmp_bd_num + 1;
6048
        end
6049
        // set wrap bit
6050
        set_tx_bd_wrap(7);
6051
      end
6052
      #1;
6053
      // SET ready bit
6054
      if (num_of_frames < 10)
6055
        set_tx_bd_ready(0, 0);
6056
      else if (num_of_frames < 14)
6057
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
6058
      else if (num_of_frames < 18)
6059
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
6060
      else if (num_of_frames < 23)
6061
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
6062
      else if (num_of_frames < 28)
6063
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
6064
      else if (num_of_frames < 34)
6065
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
6066
      else if (num_of_frames < 40)
6067
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
6068
      else if (num_of_frames < 47)
6069
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
6070
      else if (num_of_frames < 54)
6071
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
6072
      else if (num_of_frames < 62)
6073
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
6074
      else if (num_of_frames < 70)
6075
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
6076
      // CHECK END OF TRANSMITION
6077
      frame_started = 0;
6078
      if (num_of_frames >= 5)
6079
        #1 check_tx_bd(num_of_bd, data);
6080
      fork
6081
      begin: fr_st
6082
        wait (MTxEn === 1'b1); // start transmit
6083
        frame_started = 1;
6084
      end
6085
      begin
6086
        repeat (30) @(posedge mtx_clk);
6087
        if (num_of_frames < 5)
6088
        begin
6089
          if (frame_started == 1)
6090
          begin
6091
            `TIME; $display("*E Frame should NOT start!");
6092
          end
6093
          disable fr_st;
6094
        end
6095
        else
6096
        begin
6097
          if (frame_started == 0)
6098
          begin
6099
            `TIME; $display("*W Frame should start!");
6100
            disable fr_st;
6101
          end
6102
        end
6103
      end
6104
      join
6105
      // check packets larger than 4 bytes
6106
      if (num_of_frames >= 5)
6107
      begin
6108
        wait (MTxEn === 1'b0); // end transmit
6109
        while (data[15] === 1)
6110
        begin
6111
          #1 check_tx_bd(num_of_bd, data);
6112
          @(posedge wb_clk);
6113
        end
6114
        repeat (1) @(posedge wb_clk);
6115
        // check length of a PACKET
6116
        if (i_length <= (min_tmp - 4))
6117
        begin
6118
          if (eth_phy.tx_len != min_tmp)
6119
          begin
6120
            test_fail("Wrong length of the packet out from MAC");
6121
            fail = fail + 1;
6122
          end
6123
        end
6124
        else
6125
        begin
6126
          if (eth_phy.tx_len != (i_length + 4))
6127
          begin
6128
            test_fail("Wrong length of the packet out from MAC");
6129
            fail = fail + 1;
6130
          end
6131
        end
6132
        // check transmitted TX packet data
6133
        if (i_length[0] == 0)
6134
        begin
6135
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
6136
        end
6137
        else
6138
        begin
6139
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
6140
        end
6141
        if (tmp > 0)
6142
        begin
6143
          test_fail("Wrong data of the transmitted packet");
6144
          fail = fail + 1;
6145
        end
6146
        // check transmited TX packet CRC
6147
        if (num_of_frames < (min_tmp - 4))
6148
          #1 check_tx_crc((num_of_frames * 16), (min_tmp - 4), 1'b0, tmp); // length without CRC
6149
        else
6150
          #1 check_tx_crc((num_of_frames * 16), i_length, 1'b0, tmp); // length without CRC
6151
        if (tmp > 0)
6152
        begin
6153
          test_fail("Wrong CRC of the transmitted packet");
6154
          fail = fail + 1;
6155
        end
6156
      end
6157
      // check WB INT signal
6158
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
6159
      begin
6160
        if (wb_int !== 1'b1)
6161
        begin
6162
          `TIME; $display("*E WB INT signal should be set");
6163
          test_fail("WB INT signal should be set");
6164
          fail = fail + 1;
6165
        end
6166
      end
6167
      else
6168
      begin
6169
        if (wb_int !== 1'b0)
6170
        begin
6171
          `TIME; $display("*E WB INT signal should not be set");
6172
          test_fail("WB INT signal should not be set");
6173
          fail = fail + 1;
6174
        end
6175
      end
6176
      // check TX buffer descriptor of a packet
6177
      check_tx_bd(num_of_bd, data);
6178
      if (num_of_frames >= 5)
6179
      begin
6180
        if (i_length[1] == 1'b0) // interrupt enabled
6181
        begin
6182
          if ( (data[15:0] !== 16'h7800) && // wrap bit
6183
               (data[15:0] !== 16'h5800) ) // without wrap bit
6184
          begin
6185
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6186
            test_fail("TX buffer descriptor status is not correct");
6187
            fail = fail + 1;
6188
          end
6189
        end
6190
        else // interrupt not enabled
6191
        begin
6192
          if ( (data[15:0] !== 16'h3800) && // wrap bit
6193
               (data[15:0] !== 16'h1800) ) // without wrap bit
6194
          begin
6195
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6196
            test_fail("TX buffer descriptor status is not correct");
6197
            fail = fail + 1;
6198
          end
6199
        end
6200
      end
6201
      else
6202
      begin
6203
        if (data[15] !== 1'b1)
6204
        begin
6205
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6206
          test_fail("TX buffer descriptor status is not correct");
6207
          fail = fail + 1;
6208
        end
6209
      end
6210
      // clear TX BD with wrap bit
6211
      if (num_of_frames == 63)
6212
        clear_tx_bd(16, 16);
6213
      // check interrupts
6214
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6215
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
6216
      begin
6217
        if ((data & `ETH_INT_TXB) !== 1'b1)
6218
        begin
6219
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
6220
          test_fail("Interrupt Transmit Buffer was not set");
6221
          fail = fail + 1;
6222
        end
6223
        if ((data & (~`ETH_INT_TXB)) !== 0)
6224
        begin
6225
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
6226
          test_fail("Other interrupts (except Transmit Buffer) were set");
6227
          fail = fail + 1;
6228
        end
6229
      end
6230
      else
6231
      begin
6232
        if (data !== 0)
6233
        begin
6234
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
6235
          test_fail("Any of interrupts (except Transmit Buffer) was set");
6236
          fail = fail + 1;
6237
        end
6238
      end
6239
      // clear interrupts
6240
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6241
      // check WB INT signal
6242
      if (wb_int !== 1'b0)
6243
      begin
6244
        test_fail("WB INT signal should not be set");
6245
        fail = fail + 1;
6246
      end
6247
      // INTERMEDIATE DISPLAYS
6248
      if (i_length == 3)
6249
      begin
6250
        $display("    pads appending to packets is selected");
6251
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6252
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
6253
                 0, 3);
6254
      end
6255
      else if (i_length == 9)
6256
      begin
6257
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6258
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
6259
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6260
                 5, 9);
6261
      end
6262
      else if (i_length == 17)
6263
      begin
6264
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
6265
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6266
                 10, 17);
6267
      end
6268
      else if (i_length == 27)
6269
      begin
6270
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
6271
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6272
                 18, 27);
6273
      end
6274
      else if (i_length == 40)
6275
      begin
6276
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
6277
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6278
                 28, 40);
6279
      end
6280
      else if (i_length == 54)
6281
      begin
6282
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
6283
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6284
                 41, 54);
6285
      end
6286
      else if (i_length == 69)
6287
      begin
6288
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
6289
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6290
                 55, 69);
6291
      end
6292
      // set length (loop variable)
6293
      i_length = i_length + 1;
6294
      // the number of frame transmitted
6295
      num_of_frames = num_of_frames + 1;
6296
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
6297
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
6298
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
6299
          (num_of_frames == 54) || (num_of_frames == 62))
6300
        num_of_bd = 0;
6301
      else
6302
        num_of_bd = num_of_bd + 1;
6303
    end
6304
    // disable TX
6305
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
6306
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6307
    @(posedge wb_clk);
6308
    if(fail == 0)
6309
      test_ok;
6310
    else
6311
      fail = 0;
6312
  end
6313
 
6314
 
6315
  ////////////////////////////////////////////////////////////////////
6316
  ////                                                            ////
6317
  ////  Test transmit packets form 0 to (MINFL - 1) sizes at      ////
6318
  ////  8 TX buffer decriptors ( 100Mbps ).                       ////
6319
  ////                                                            ////
6320
  ////////////////////////////////////////////////////////////////////
6321
  if (test_num == 7) // 
6322
  begin
6323
    // TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
6324
    test_name = "TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
6325
    `TIME; $display("  TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
6326
 
6327
    // reset MAC registers
6328
    hard_reset;
6329
    // reset MAC and MII LOGIC with soft reset
6330
    reset_mac;
6331
    reset_mii;
6332
    // set wb slave response
6333
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
6334
 
6335
    max_tmp = 0;
6336
    min_tmp = 0;
6337
    // set 8 TX buffer descriptors - must be set before TX enable
6338
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6339
    // enable TX, set full-duplex mode, padding and CRC appending
6340
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
6341
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6342
    // prepare two packets of MAXFL length
6343
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6344
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
6345
    min_tmp = tmp[31:16];
6346
    st_data = 8'h12;
6347
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
6348
    st_data = 8'h34;
6349
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
6350
    // check WB INT signal
6351
    if (wb_int !== 1'b0)
6352
    begin
6353
      test_fail("WB INT signal should not be set");
6354
      fail = fail + 1;
6355
    end
6356
 
6357
    // write to phy's control register for 100Mbps
6358
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
6359
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
6360
    speed = 100;
6361
 
6362
    frame_started = 0;
6363
    num_of_frames = 0;
6364
    num_of_bd = 0;
6365
    i_length = 0; // 0;
6366
    while (i_length < 70) // (min_tmp - 4))
6367
    begin
6368
      #1;
6369
      // choose generating carrier sense and collision
6370
      case (i_length[1:0])
6371
      2'h0: // Interrupt is generated
6372
      begin
6373
        // Reset_tx_bd nable interrupt generation
6374
        // unmask interrupts
6375
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6376
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6377
        // not detect carrier sense in FD and no collision
6378
        eth_phy.carrier_sense_tx_fd_detect(0);
6379
        eth_phy.collision(0);
6380
      end
6381
      2'h1: // Interrupt is not generated
6382
      begin
6383
        // set_tx_bd enable interrupt generation
6384
        // mask interrupts
6385
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6386
        // detect carrier sense in FD and no collision
6387
        eth_phy.carrier_sense_tx_fd_detect(1);
6388
        eth_phy.collision(0);
6389
      end
6390
      2'h2: // Interrupt is not generated
6391
      begin
6392
        // set_tx_bd disable the interrupt generation
6393
        // unmask interrupts
6394
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6395
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6396
        // not detect carrier sense in FD and set collision
6397
        eth_phy.carrier_sense_tx_fd_detect(0);
6398
        eth_phy.collision(1);
6399
      end
6400
      default: // 2'h3: // Interrupt is not generated
6401
      begin
6402
        // set_tx_bd disable the interrupt generation
6403
        // mask interrupts
6404
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6405
        // detect carrier sense in FD and set collision
6406
        eth_phy.carrier_sense_tx_fd_detect(1);
6407
        eth_phy.collision(1);
6408
      end
6409
      endcase
6410
      #1;
6411
      // first destination address on ethernet PHY
6412
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
6413
      // SET packets and wrap bit
6414
      // num_of_frames <= 9 => wrap set to TX BD 0
6415
      if (num_of_frames <= 9)
6416
      begin
6417
        tmp_len = i_length; // length of frame
6418
        tmp_bd_num = 0; // TX BD number
6419
        // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6420
        // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6421
        if (tmp_len[0] == 0)
6422
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6423
        else
6424
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6425
        // set wrap bit
6426
        set_tx_bd_wrap(0);
6427
      end
6428
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
6429
      else if ((num_of_frames == 10) || (num_of_frames == 14))
6430
      begin
6431
        tmp_len = i_length; // length of frame
6432
        tmp_bd_num = 0; // TX BD number
6433
        while (tmp_bd_num < 4) //
6434
        begin
6435
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6436
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6437
          if (tmp_len[0] == 0)
6438
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6439
          else
6440
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6441
          tmp_len = tmp_len + 1;
6442
          // set TX BD number
6443
          tmp_bd_num = tmp_bd_num + 1;
6444
        end
6445
        // set wrap bit
6446
        set_tx_bd_wrap(3);
6447
      end
6448
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
6449
      else if ((num_of_frames == 18) || (num_of_frames == 23))
6450
      begin
6451
        tmp_len = i_length; // length of frame
6452
        tmp_bd_num = 0; // TX BD number
6453
        while (tmp_bd_num < 5) //
6454
        begin
6455
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6456
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6457
          if (tmp_len[0] == 0)
6458
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6459
          else
6460
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6461
          tmp_len = tmp_len + 1;
6462
          // set TX BD number
6463
          tmp_bd_num = tmp_bd_num + 1;
6464
        end
6465
        // set wrap bit
6466
        set_tx_bd_wrap(4);
6467
      end
6468
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
6469
      else if ((num_of_frames == 28) || (num_of_frames == 34))
6470
      begin
6471
        tmp_len = i_length; // length of frame
6472
        tmp_bd_num = 0; // TX BD number
6473
        while (tmp_bd_num < 6) //
6474
        begin
6475
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6476
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6477
          if (tmp_len[0] == 0)
6478
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6479
          else
6480
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6481
          tmp_len = tmp_len + 1;
6482
          // set TX BD number
6483
          tmp_bd_num = tmp_bd_num + 1;
6484
        end
6485
        // set wrap bit
6486
        set_tx_bd_wrap(5);
6487
      end
6488
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
6489
      else if ((num_of_frames == 40) || (num_of_frames == 47))
6490
      begin
6491
        tmp_len = i_length; // length of frame
6492
        tmp_bd_num = 0; // TX BD number
6493
        while (tmp_bd_num < 7) //
6494
        begin
6495
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6496
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6497
          if (tmp_len[0] == 0)
6498
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6499
          else
6500
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6501
          tmp_len = tmp_len + 1;
6502
          // set TX BD number
6503
          tmp_bd_num = tmp_bd_num + 1;
6504
        end
6505
        // set wrap bit
6506
        set_tx_bd_wrap(6);
6507
      end
6508
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
6509
      else if ((num_of_frames == 54) || (num_of_frames == 62))
6510
      begin
6511
        tmp_len = i_length; // length of frame
6512
        tmp_bd_num = 0; // TX BD number
6513
        while (tmp_bd_num < 8) //
6514
        begin
6515
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6516
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6517
          if (tmp_len[0] == 0)
6518
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
6519
          else
6520
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
6521
          tmp_len = tmp_len + 1;
6522
          // set TX BD number
6523
          tmp_bd_num = tmp_bd_num + 1;
6524
        end
6525
        // set wrap bit
6526
        set_tx_bd_wrap(7);
6527
      end
6528
      #1;
6529
      // SET ready bit
6530
      if (num_of_frames < 10)
6531
        set_tx_bd_ready(0, 0);
6532
      else if (num_of_frames < 14)
6533
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
6534
      else if (num_of_frames < 18)
6535
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
6536
      else if (num_of_frames < 23)
6537
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
6538
      else if (num_of_frames < 28)
6539
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
6540
      else if (num_of_frames < 34)
6541
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
6542
      else if (num_of_frames < 40)
6543
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
6544
      else if (num_of_frames < 47)
6545
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
6546
      else if (num_of_frames < 54)
6547
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
6548
      else if (num_of_frames < 62)
6549
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
6550
      else if (num_of_frames < 70)
6551
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
6552
      // CHECK END OF TRANSMITION
6553
      frame_started = 0;
6554
      if (num_of_frames >= 5)
6555
        #1 check_tx_bd(num_of_bd, data);
6556
      fork
6557
      begin: fr_st1
6558
        wait (MTxEn === 1'b1); // start transmit
6559
        frame_started = 1;
6560
      end
6561
      begin
6562
        repeat (30) @(posedge mtx_clk);
6563
        if (num_of_frames < 5)
6564
        begin
6565
          if (frame_started == 1)
6566
          begin
6567
            `TIME; $display("*E Frame should NOT start!");
6568
          end
6569
          disable fr_st1;
6570
        end
6571
        else
6572
        begin
6573
          if (frame_started == 0)
6574
          begin
6575
            `TIME; $display("*W Frame should start!");
6576
            disable fr_st1;
6577
          end
6578
        end
6579
      end
6580
      join
6581
      // check packets larger than 4 bytes
6582
      if (num_of_frames >= 5)
6583
      begin
6584
        wait (MTxEn === 1'b0); // end transmit
6585
        while (data[15] === 1)
6586
        begin
6587
          #1 check_tx_bd(num_of_bd, data);
6588
          @(posedge wb_clk);
6589
        end
6590
        repeat (1) @(posedge wb_clk);
6591
        // check length of a PACKET
6592
        if (i_length <= (min_tmp - 4))
6593
        begin
6594
          if (eth_phy.tx_len != min_tmp)
6595
          begin
6596
            test_fail("Wrong length of the packet out from MAC");
6597
            fail = fail + 1;
6598
          end
6599
        end
6600
        else
6601
        begin
6602
          if (eth_phy.tx_len != (i_length + 4))
6603
          begin
6604
            test_fail("Wrong length of the packet out from MAC");
6605
            fail = fail + 1;
6606
          end
6607
        end
6608
        // check transmitted TX packet data
6609
        if (i_length[0] == 0)
6610
        begin
6611
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
6612
        end
6613
        else
6614
        begin
6615
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
6616
        end
6617
        if (tmp > 0)
6618
        begin
6619
          test_fail("Wrong data of the transmitted packet");
6620
          fail = fail + 1;
6621
        end
6622
        // check transmited TX packet CRC
6623
        if (num_of_frames < (min_tmp - 4))
6624
          #1 check_tx_crc((num_of_frames * 16), (min_tmp - 4), 1'b0, tmp); // length without CRC
6625
        else
6626
          #1 check_tx_crc((num_of_frames * 16), i_length, 1'b0, tmp); // length without CRC
6627
        if (tmp > 0)
6628
        begin
6629
          test_fail("Wrong CRC of the transmitted packet");
6630
          fail = fail + 1;
6631
        end
6632
      end
6633
      // check WB INT signal
6634
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
6635
      begin
6636
        if (wb_int !== 1'b1)
6637
        begin
6638
          `TIME; $display("*E WB INT signal should be set");
6639
          test_fail("WB INT signal should be set");
6640
          fail = fail + 1;
6641
        end
6642
      end
6643
      else
6644
      begin
6645
        if (wb_int !== 1'b0)
6646
        begin
6647
          `TIME; $display("*E WB INT signal should not be set");
6648
          test_fail("WB INT signal should not be set");
6649
          fail = fail + 1;
6650
        end
6651
      end
6652
      // check TX buffer descriptor of a packet
6653
      check_tx_bd(num_of_bd, data);
6654
      if (num_of_frames >= 5)
6655
      begin
6656
        if (i_length[1] == 1'b0) // interrupt enabled
6657
        begin
6658
          if ( (data[15:0] !== 16'h7800) && // wrap bit
6659
               (data[15:0] !== 16'h5800) ) // without wrap bit
6660
          begin
6661
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6662
            test_fail("TX buffer descriptor status is not correct");
6663
            fail = fail + 1;
6664
          end
6665
        end
6666
        else // interrupt not enabled
6667
        begin
6668
          if ( (data[15:0] !== 16'h3800) && // wrap bit
6669
               (data[15:0] !== 16'h1800) ) // without wrap bit
6670
          begin
6671
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6672
            test_fail("TX buffer descriptor status is not correct");
6673
            fail = fail + 1;
6674
          end
6675
        end
6676
      end
6677
      else
6678
      begin
6679
        if (data[15] !== 1'b1)
6680
        begin
6681
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
6682
          test_fail("TX buffer descriptor status is not correct");
6683
          fail = fail + 1;
6684
        end
6685
      end
6686
      // clear TX BD with wrap bit
6687
      if (num_of_frames == 63)
6688
        clear_tx_bd(16, 16);
6689
      // check interrupts
6690
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6691
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
6692
      begin
6693
        if ((data & `ETH_INT_TXB) !== 1'b1)
6694
        begin
6695
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
6696
          test_fail("Interrupt Transmit Buffer was not set");
6697
          fail = fail + 1;
6698
        end
6699
        if ((data & (~`ETH_INT_TXB)) !== 0)
6700
        begin
6701
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
6702
          test_fail("Other interrupts (except Transmit Buffer) were set");
6703
          fail = fail + 1;
6704
        end
6705
      end
6706
      else
6707
      begin
6708
        if (data !== 0)
6709
        begin
6710
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
6711
          test_fail("Any of interrupts (except Transmit Buffer) was set");
6712
          fail = fail + 1;
6713
        end
6714
      end
6715
      // clear interrupts
6716
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6717
      // check WB INT signal
6718
      if (wb_int !== 1'b0)
6719
      begin
6720
        test_fail("WB INT signal should not be set");
6721
        fail = fail + 1;
6722
      end
6723
      // INTERMEDIATE DISPLAYS
6724
      if (i_length == 3)
6725
      begin
6726
        $display("    pads appending to packets is selected");
6727
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6728
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
6729
                 0, 3);
6730
      end
6731
      else if (i_length == 9)
6732
      begin
6733
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
6734
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
6735
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6736
                 5, 9);
6737
      end
6738
      else if (i_length == 17)
6739
      begin
6740
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
6741
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6742
                 10, 17);
6743
      end
6744
      else if (i_length == 27)
6745
      begin
6746
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
6747
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6748
                 18, 27);
6749
      end
6750
      else if (i_length == 40)
6751
      begin
6752
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
6753
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6754
                 28, 40);
6755
      end
6756
      else if (i_length == 54)
6757
      begin
6758
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
6759
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6760
                 41, 54);
6761
      end
6762
      else if (i_length == 69)
6763
      begin
6764
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
6765
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
6766
                 55, 69);
6767
      end
6768
      // set length (loop variable)
6769
      i_length = i_length + 1;
6770
      // the number of frame transmitted
6771
      num_of_frames = num_of_frames + 1;
6772
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
6773
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
6774
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
6775
          (num_of_frames == 54) || (num_of_frames == 62))
6776
        num_of_bd = 0;
6777
      else
6778
        num_of_bd = num_of_bd + 1;
6779
    end
6780
    // disable TX
6781
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
6782
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6783
    @(posedge wb_clk);
6784
    if(fail == 0)
6785
      test_ok;
6786
    else
6787
      fail = 0;
6788
  end
6789
 
6790
 
6791
  ////////////////////////////////////////////////////////////////////
6792
  ////                                                            ////
6793 243 tadejm
  ////  Test transmit packets (no pads) from 0 to (MINFL - 1)     ////
6794 209 tadejm
  ////  sizes at 8 TX buffer decriptors ( 10Mbps ).               ////
6795
  ////                                                            ////
6796
  ////////////////////////////////////////////////////////////////////
6797
  if (test_num == 8) // 
6798
  begin
6799 243 tadejm
    // TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
6800
    test_name = "TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )";
6801
    `TIME; $display("  TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )");
6802 209 tadejm
 
6803
    // reset MAC registers
6804
    hard_reset;
6805
    // reset MAC and MII LOGIC with soft reset
6806
    reset_mac;
6807
    reset_mii;
6808
    // set wb slave response
6809
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
6810
 
6811
    max_tmp = 0;
6812
    min_tmp = 0;
6813
    // set 8 TX buffer descriptors - must be set before TX enable
6814
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6815
    // enable TX, set full-duplex mode, padding and CRC appending
6816 243 tadejm
//    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
6817
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
6818 209 tadejm
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6819
    // prepare two packets of MAXFL length
6820
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6821
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
6822
    min_tmp = tmp[31:16];
6823
    st_data = 8'h12;
6824
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
6825
    st_data = 8'h34;
6826
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
6827
    // check WB INT signal
6828
    if (wb_int !== 1'b0)
6829
    begin
6830
      test_fail("WB INT signal should not be set");
6831
      fail = fail + 1;
6832
    end
6833
 
6834
    // write to phy's control register for 10Mbps
6835
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
6836
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
6837
    speed = 10;
6838
 
6839
    frame_started = 0;
6840
    num_of_frames = 0;
6841
    num_of_bd = 0;
6842
    i_length = 0; // 0;
6843
    while (i_length < 70) // (min_tmp - 4))
6844
    begin
6845
      #1;
6846
      // choose generating carrier sense and collision
6847
      case (i_length[1:0])
6848
      2'h0: // Interrupt is generated
6849
      begin
6850
        // Reset_tx_bd nable interrupt generation
6851
        // unmask interrupts
6852
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6853
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6854
        // not detect carrier sense in FD and no collision
6855
        eth_phy.carrier_sense_tx_fd_detect(0);
6856
        eth_phy.collision(0);
6857
      end
6858
      2'h1: // Interrupt is not generated
6859
      begin
6860
        // set_tx_bd enable interrupt generation
6861
        // mask interrupts
6862
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6863
        // detect carrier sense in FD and no collision
6864
        eth_phy.carrier_sense_tx_fd_detect(1);
6865
        eth_phy.collision(0);
6866
      end
6867
      2'h2: // Interrupt is not generated
6868
      begin
6869
        // set_tx_bd disable the interrupt generation
6870
        // unmask interrupts
6871
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
6872
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6873
        // not detect carrier sense in FD and set collision
6874
        eth_phy.carrier_sense_tx_fd_detect(0);
6875
        eth_phy.collision(1);
6876
      end
6877
      default: // 2'h3: // Interrupt is not generated
6878
      begin
6879
        // set_tx_bd disable the interrupt generation
6880
        // mask interrupts
6881
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
6882
        // detect carrier sense in FD and set collision
6883
        eth_phy.carrier_sense_tx_fd_detect(1);
6884
        eth_phy.collision(1);
6885
      end
6886
      endcase
6887 243 tadejm
//      // append CRC
6888
//      if ((i_length[0] == 1'b0) && (num_of_frames >= 6))
6889
//      begin
6890
//        append_tx_crc(`MEMORY_BASE, i_length, 1'b0);
6891
//      end
6892 209 tadejm
      #1;
6893
      // first destination address on ethernet PHY
6894
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
6895
      // SET packets and wrap bit
6896
      // num_of_frames <= 9 => wrap set to TX BD 0
6897 243 tadejm
      if (num_of_frames <= 5)
6898
        begin
6899
          tmp_len = i_length; // length of frame
6900
          tmp_bd_num = 0; // TX BD number
6901
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6902
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6903
          if (tmp_len[0] == 0) // CRC appended by 'HARDWARE'
6904
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, `MEMORY_BASE);
6905
          else
6906
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
6907
          // set wrap bit
6908
          set_tx_bd_wrap(0);
6909
        end
6910
        else if (num_of_frames <= 9)
6911
        begin
6912
          tmp_len = i_length; // length of frame
6913
          tmp_bd_num = 0; // TX BD number
6914
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6915
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6916
          if (tmp_len[0] == 0) // CRC appended by 'SOFTWARE'
6917
            set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
6918
          else
6919
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
6920
          // set wrap bit
6921
          set_tx_bd_wrap(0);
6922 209 tadejm
      end
6923
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
6924
      else if ((num_of_frames == 10) || (num_of_frames == 14))
6925
      begin
6926
        tmp_len = i_length; // length of frame
6927
        tmp_bd_num = 0; // TX BD number
6928
        while (tmp_bd_num < 4) //
6929
        begin
6930
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6931
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6932
          if (tmp_len[0] == 0)
6933 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
6934 209 tadejm
          else
6935 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
6936 209 tadejm
          tmp_len = tmp_len + 1;
6937
          // set TX BD number
6938
          tmp_bd_num = tmp_bd_num + 1;
6939
        end
6940
        // set wrap bit
6941
        set_tx_bd_wrap(3);
6942
      end
6943
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
6944
      else if ((num_of_frames == 18) || (num_of_frames == 23))
6945
      begin
6946
        tmp_len = i_length; // length of frame
6947
        tmp_bd_num = 0; // TX BD number
6948
        while (tmp_bd_num < 5) //
6949
        begin
6950
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6951
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6952
          if (tmp_len[0] == 0)
6953 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
6954
          else // when (num_of_frames == 23), (i_length == 23) and therefor i_length[0] == 1 !!!
6955
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1],
6956
                      ((num_of_frames == 23) && (tmp_bd_num == 0)), 1'b1, (`MEMORY_BASE + max_tmp));
6957 209 tadejm
          tmp_len = tmp_len + 1;
6958
          // set TX BD number
6959
          tmp_bd_num = tmp_bd_num + 1;
6960
        end
6961
        // set wrap bit
6962
        set_tx_bd_wrap(4);
6963
      end
6964
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
6965
      else if ((num_of_frames == 28) || (num_of_frames == 34))
6966
      begin
6967
        tmp_len = i_length; // length of frame
6968
        tmp_bd_num = 0; // TX BD number
6969
        while (tmp_bd_num < 6) //
6970
        begin
6971
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6972
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6973
          if (tmp_len[0] == 0)
6974 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
6975 209 tadejm
          else
6976 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
6977 209 tadejm
          tmp_len = tmp_len + 1;
6978
          // set TX BD number
6979
          tmp_bd_num = tmp_bd_num + 1;
6980
        end
6981
        // set wrap bit
6982
        set_tx_bd_wrap(5);
6983
      end
6984
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
6985
      else if ((num_of_frames == 40) || (num_of_frames == 47))
6986
      begin
6987
        tmp_len = i_length; // length of frame
6988
        tmp_bd_num = 0; // TX BD number
6989
        while (tmp_bd_num < 7) //
6990
        begin
6991
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
6992
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
6993
          if (tmp_len[0] == 0)
6994 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
6995 209 tadejm
          else
6996 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
6997 209 tadejm
          tmp_len = tmp_len + 1;
6998
          // set TX BD number
6999
          tmp_bd_num = tmp_bd_num + 1;
7000
        end
7001
        // set wrap bit
7002
        set_tx_bd_wrap(6);
7003
      end
7004
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
7005
      else if ((num_of_frames == 54) || (num_of_frames == 62))
7006
      begin
7007
        tmp_len = i_length; // length of frame
7008
        tmp_bd_num = 0; // TX BD number
7009
        while (tmp_bd_num < 8) //
7010
        begin
7011
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7012
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7013
          if (tmp_len[0] == 0)
7014 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, (tmp_len + 0), !tmp_len[1], 1'b0, 1'b0, `MEMORY_BASE);
7015 209 tadejm
          else
7016 243 tadejm
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b0, 1'b1, (`MEMORY_BASE + max_tmp));
7017 209 tadejm
          tmp_len = tmp_len + 1;
7018
          // set TX BD number
7019
          tmp_bd_num = tmp_bd_num + 1;
7020
        end
7021
        // set wrap bit
7022
        set_tx_bd_wrap(7);
7023
      end
7024
      #1;
7025
      // SET ready bit
7026
      if (num_of_frames < 10)
7027
        set_tx_bd_ready(0, 0);
7028
      else if (num_of_frames < 14)
7029
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
7030
      else if (num_of_frames < 18)
7031
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
7032
      else if (num_of_frames < 23)
7033
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
7034
      else if (num_of_frames < 28)
7035
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
7036
      else if (num_of_frames < 34)
7037
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
7038
      else if (num_of_frames < 40)
7039
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
7040
      else if (num_of_frames < 47)
7041
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
7042
      else if (num_of_frames < 54)
7043
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
7044
      else if (num_of_frames < 62)
7045
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
7046
      else if (num_of_frames < 70)
7047
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
7048
      // CHECK END OF TRANSMITION
7049
      frame_started = 0;
7050
      if (num_of_frames >= 5)
7051
        #1 check_tx_bd(num_of_bd, data);
7052
      fork
7053
      begin: fr_st2
7054
        wait (MTxEn === 1'b1); // start transmit
7055
        frame_started = 1;
7056
      end
7057
      begin
7058
        repeat (30) @(posedge mtx_clk);
7059
        if (num_of_frames < 5)
7060
        begin
7061
          if (frame_started == 1)
7062
          begin
7063
            `TIME; $display("*E Frame should NOT start!");
7064
          end
7065
          disable fr_st2;
7066
        end
7067
        else
7068
        begin
7069
          if (frame_started == 0)
7070
          begin
7071
            `TIME; $display("*W Frame should start!");
7072
            disable fr_st2;
7073
          end
7074
        end
7075
      end
7076
      join
7077
      // check packets larger than 4 bytes
7078
      if (num_of_frames >= 5)
7079
      begin
7080
        wait (MTxEn === 1'b0); // end transmit
7081
        while (data[15] === 1)
7082
        begin
7083
          #1 check_tx_bd(num_of_bd, data);
7084
          @(posedge wb_clk);
7085
        end
7086
        repeat (1) @(posedge wb_clk);
7087 243 tadejm
        // check length of a PACKET 
7088
        if ((eth_phy.tx_len != i_length) && (i_length[0] == 1'b0) && (num_of_frames >= 6))
7089 209 tadejm
        begin
7090
          `TIME; $display("*E Wrong length of the packet out from MAC");
7091
          test_fail("Wrong length of the packet out from MAC");
7092
          fail = fail + 1;
7093
        end
7094 243 tadejm
        else if ((eth_phy.tx_len != (i_length + 4)) && (num_of_frames != 23))
7095
        begin
7096
          `TIME; $display("*E Wrong length of the packet out from MAC");
7097
          test_fail("Wrong length of the packet out from MAC");
7098
          fail = fail + 1;
7099
        end
7100
        else if ((eth_phy.tx_len != (min_tmp)) && (num_of_frames == 23))
7101
        begin
7102
          `TIME; $display("*E Wrong length of the packet out from MAC");
7103
          test_fail("Wrong length of the packet out from MAC");
7104
          fail = fail + 1;
7105
        end
7106 209 tadejm
        // check transmitted TX packet data
7107
        if (i_length[0] == 0)
7108
        begin
7109
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
7110
        end
7111 243 tadejm
        else if (num_of_frames == 23) // i_length[0] == 1 here
7112
        begin
7113
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), (min_tmp - 4), tmp);
7114
        end
7115 209 tadejm
        else
7116
        begin
7117
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
7118
        end
7119
        if (tmp > 0)
7120
        begin
7121
          test_fail("Wrong data of the transmitted packet");
7122
          fail = fail + 1;
7123
        end
7124
        // check transmited TX packet CRC
7125 243 tadejm
        #1;
7126
        if ((i_length[0] == 1'b0) && (num_of_frames >= 6))
7127
        begin
7128
        end
7129
        else
7130
          check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
7131 209 tadejm
        if (tmp > 0)
7132
        begin
7133
          test_fail("Wrong CRC of the transmitted packet");
7134
          fail = fail + 1;
7135
        end
7136
      end
7137
      // check WB INT signal
7138
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
7139
      begin
7140
        if (wb_int !== 1'b1)
7141
        begin
7142
          `TIME; $display("*E WB INT signal should be set");
7143
          test_fail("WB INT signal should be set");
7144
          fail = fail + 1;
7145
        end
7146
      end
7147
      else
7148
      begin
7149
        if (wb_int !== 1'b0)
7150
        begin
7151
          `TIME; $display("*E WB INT signal should not be set");
7152
          test_fail("WB INT signal should not be set");
7153
          fail = fail + 1;
7154
        end
7155
      end
7156
      // check TX buffer descriptor of a packet
7157
      check_tx_bd(num_of_bd, data);
7158
      if (num_of_frames >= 5)
7159
      begin
7160 243 tadejm
        if ((i_length[1] == 1'b0) && (i_length[0] == 1'b0)) // interrupt enabled
7161 209 tadejm
        begin
7162 243 tadejm
          if ( (data[15:0] !== 16'h6000) &&  // wrap bit
7163
               (data[15:0] !== 16'h4000) )  // without wrap bit
7164 209 tadejm
          begin
7165
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7166
            test_fail("TX buffer descriptor status is not correct");
7167
            fail = fail + 1;
7168
          end
7169
        end
7170 243 tadejm
        else if ((i_length[1] == 1'b1) && (i_length[0] == 1'b0)) // interrupt not enabled
7171 209 tadejm
        begin
7172 243 tadejm
          if ( (data[15:0] !== 16'h2000) && // wrap bit
7173
               (data[15:0] !== 16'h0000) ) // without wrap bit
7174
          begin
7175
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7176
            test_fail("TX buffer descriptor status is not correct");
7177
            fail = fail + 1;
7178
          end
7179
        end
7180
        else if ((i_length[1] == 1'b0) && (i_length[0] == 1'b1)) // interrupt enabled
7181
        begin
7182
          if ( (data[15:0] !== 16'h6800) && // wrap bit
7183
               (data[15:0] !== 16'h4800) ) // without wrap bit
7184
          begin
7185
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7186
            test_fail("TX buffer descriptor status is not correct");
7187
            fail = fail + 1;
7188
          end
7189
        end
7190
        else if (num_of_frames != 23) // ((i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
7191
        begin
7192
          if ( (data[15:0] !== 16'h2800) && // wrap bit
7193
               (data[15:0] !== 16'h0800) ) // without wrap bit
7194
          begin
7195
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7196
            test_fail("TX buffer descriptor status is not correct");
7197
            fail = fail + 1;
7198
          end
7199
        end
7200
        else // ((num_of_frames != 23) && (i_length[1] == 1'b1) && (i_length[0] == 1'b1)) // interrupt not enabled
7201
        begin
7202 209 tadejm
          if ( (data[15:0] !== 16'h3800) && // wrap bit
7203
               (data[15:0] !== 16'h1800) ) // without wrap bit
7204
          begin
7205
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7206
            test_fail("TX buffer descriptor status is not correct");
7207
            fail = fail + 1;
7208
          end
7209
        end
7210
      end
7211
      else
7212
      begin
7213
        if (data[15] !== 1'b1)
7214
        begin
7215
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7216
          test_fail("TX buffer descriptor status is not correct");
7217
          fail = fail + 1;
7218
        end
7219
      end
7220
      // clear TX BD with wrap bit
7221
      if (num_of_frames == 63)
7222
        clear_tx_bd(16, 16);
7223
      // check interrupts
7224
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7225
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
7226
      begin
7227
        if ((data & `ETH_INT_TXB) !== 1'b1)
7228
        begin
7229
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
7230
          test_fail("Interrupt Transmit Buffer was not set");
7231
          fail = fail + 1;
7232
        end
7233
        if ((data & (~`ETH_INT_TXB)) !== 0)
7234
        begin
7235
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
7236
          test_fail("Other interrupts (except Transmit Buffer) were set");
7237
          fail = fail + 1;
7238
        end
7239
      end
7240
      else
7241
      begin
7242
        if (data !== 0)
7243
        begin
7244
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
7245
          test_fail("Any of interrupts (except Transmit Buffer) was set");
7246
          fail = fail + 1;
7247
        end
7248
      end
7249
      // clear interrupts
7250
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7251
      // check WB INT signal
7252
      if (wb_int !== 1'b0)
7253
      begin
7254
        test_fail("WB INT signal should not be set");
7255
        fail = fail + 1;
7256
      end
7257
      // INTERMEDIATE DISPLAYS
7258
      if (i_length == 3)
7259
      begin
7260
        $display("    pads appending to packets is selected");
7261
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7262
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
7263
                 0, 3);
7264
      end
7265
      else if (i_length == 9)
7266
      begin
7267
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7268
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
7269
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7270
                 5, 9);
7271
      end
7272
      else if (i_length == 17)
7273
      begin
7274
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
7275
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7276
                 10, 17);
7277
      end
7278
      else if (i_length == 27)
7279
      begin
7280
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
7281
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7282
                 18, 27);
7283
      end
7284
      else if (i_length == 40)
7285
      begin
7286
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
7287
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7288
                 28, 40);
7289
      end
7290
      else if (i_length == 54)
7291
      begin
7292
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
7293
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7294
                 41, 54);
7295
      end
7296
      else if (i_length == 69)
7297
      begin
7298
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
7299
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7300
                 55, 69);
7301
      end
7302
      // set length (loop variable)
7303
      i_length = i_length + 1;
7304
      // the number of frame transmitted
7305
      num_of_frames = num_of_frames + 1;
7306
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
7307
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
7308
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
7309
          (num_of_frames == 54) || (num_of_frames == 62))
7310
        num_of_bd = 0;
7311
      else
7312
        num_of_bd = num_of_bd + 1;
7313
    end
7314
    // disable TX
7315
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
7316
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7317
    @(posedge wb_clk);
7318
    if(fail == 0)
7319
      test_ok;
7320
    else
7321
      fail = 0;
7322
  end
7323
 
7324
 
7325
  ////////////////////////////////////////////////////////////////////
7326
  ////                                                            ////
7327 243 tadejm
  ////  Test transmit packets (no pads) form 0 to (MINFL - 1)     ////
7328 209 tadejm
  ////  sizes at 8 TX buffer decriptors ( 100Mbps ).              ////
7329
  ////                                                            ////
7330
  ////////////////////////////////////////////////////////////////////
7331
  if (test_num == 9) // 
7332
  begin
7333 243 tadejm
    // TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
7334
    test_name = "TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )";
7335
    `TIME; $display("  TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )");
7336 209 tadejm
 
7337
    // reset MAC registers
7338
    hard_reset;
7339
    // reset MAC and MII LOGIC with soft reset
7340
    reset_mac;
7341
    reset_mii;
7342
    // set wb slave response
7343
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
7344
 
7345
    max_tmp = 0;
7346
    min_tmp = 0;
7347
    // set 8 TX buffer descriptors - must be set before TX enable
7348
    wbm_write(`ETH_TX_BD_NUM, 32'h8, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7349
    // enable TX, set full-duplex mode, padding and CRC appending
7350
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
7351
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7352
    // prepare two packets of MAXFL length
7353
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7354
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
7355
    min_tmp = tmp[31:16];
7356
    st_data = 8'h12;
7357
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
7358
    st_data = 8'h34;
7359
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC
7360
    // check WB INT signal
7361
    if (wb_int !== 1'b0)
7362
    begin
7363
      test_fail("WB INT signal should not be set");
7364
      fail = fail + 1;
7365
    end
7366
 
7367
    // write to phy's control register for 100Mbps
7368
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
7369
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
7370
    speed = 100;
7371
 
7372
    frame_started = 0;
7373
    num_of_frames = 0;
7374
    num_of_bd = 0;
7375
    i_length = 0; // 0;
7376
    while (i_length < 70) // (min_tmp - 4))
7377
    begin
7378
      #1;
7379
      // choose generating carrier sense and collision
7380
      case (i_length[1:0])
7381
      2'h0: // Interrupt is generated
7382
      begin
7383
        // Reset_tx_bd nable interrupt generation
7384
        // unmask interrupts
7385
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
7386
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7387
        // not detect carrier sense in FD and no collision
7388
        eth_phy.carrier_sense_tx_fd_detect(0);
7389
        eth_phy.collision(0);
7390
      end
7391
      2'h1: // Interrupt is not generated
7392
      begin
7393
        // set_tx_bd enable interrupt generation
7394
        // mask interrupts
7395
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7396
        // detect carrier sense in FD and no collision
7397
        eth_phy.carrier_sense_tx_fd_detect(1);
7398
        eth_phy.collision(0);
7399
      end
7400
      2'h2: // Interrupt is not generated
7401
      begin
7402
        // set_tx_bd disable the interrupt generation
7403
        // unmask interrupts
7404
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
7405
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7406
        // not detect carrier sense in FD and set collision
7407
        eth_phy.carrier_sense_tx_fd_detect(0);
7408
        eth_phy.collision(1);
7409
      end
7410
      default: // 2'h3: // Interrupt is not generated
7411
      begin
7412
        // set_tx_bd disable the interrupt generation
7413
        // mask interrupts
7414
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7415
        // detect carrier sense in FD and set collision
7416
        eth_phy.carrier_sense_tx_fd_detect(1);
7417
        eth_phy.collision(1);
7418
      end
7419
      endcase
7420
      #1;
7421
      // first destination address on ethernet PHY
7422
      eth_phy.set_tx_mem_addr(num_of_frames * 16);
7423
      // SET packets and wrap bit
7424
      // num_of_frames <= 9 => wrap set to TX BD 0
7425
      if (num_of_frames <= 9)
7426
      begin
7427
        tmp_len = i_length; // length of frame
7428
        tmp_bd_num = 0; // TX BD number
7429
        // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7430
        // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7431
        if (tmp_len[0] == 0)
7432
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7433
        else
7434
          set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7435
        // set wrap bit
7436
        set_tx_bd_wrap(0);
7437
      end
7438
      // 10 <= num_of_frames < 18 => wrap set to TX BD 3
7439
      else if ((num_of_frames == 10) || (num_of_frames == 14))
7440
      begin
7441
        tmp_len = i_length; // length of frame
7442
        tmp_bd_num = 0; // TX BD number
7443
        while (tmp_bd_num < 4) //
7444
        begin
7445
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7446
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7447
          if (tmp_len[0] == 0)
7448
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7449
          else
7450
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7451
          tmp_len = tmp_len + 1;
7452
          // set TX BD number
7453
          tmp_bd_num = tmp_bd_num + 1;
7454
        end
7455
        // set wrap bit
7456
        set_tx_bd_wrap(3);
7457
      end
7458
      // 18 <= num_of_frames < 28 => wrap set to TX BD 4
7459
      else if ((num_of_frames == 18) || (num_of_frames == 23))
7460
      begin
7461
        tmp_len = i_length; // length of frame
7462
        tmp_bd_num = 0; // TX BD number
7463
        while (tmp_bd_num < 5) //
7464
        begin
7465
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7466
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7467
          if (tmp_len[0] == 0)
7468
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7469
          else
7470
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7471
          tmp_len = tmp_len + 1;
7472
          // set TX BD number
7473
          tmp_bd_num = tmp_bd_num + 1;
7474
        end
7475
        // set wrap bit
7476
        set_tx_bd_wrap(4);
7477
      end
7478
      // 28 <= num_of_frames < 40 => wrap set to TX BD 5
7479
      else if ((num_of_frames == 28) || (num_of_frames == 34))
7480
      begin
7481
        tmp_len = i_length; // length of frame
7482
        tmp_bd_num = 0; // TX BD number
7483
        while (tmp_bd_num < 6) //
7484
        begin
7485
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7486
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7487
          if (tmp_len[0] == 0)
7488
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7489
          else
7490
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7491
          tmp_len = tmp_len + 1;
7492
          // set TX BD number
7493
          tmp_bd_num = tmp_bd_num + 1;
7494
        end
7495
        // set wrap bit
7496
        set_tx_bd_wrap(5);
7497
      end
7498
      // 40 <= num_of_frames < 54 => wrap set to TX BD 6
7499
      else if ((num_of_frames == 40) || (num_of_frames == 47))
7500
      begin
7501
        tmp_len = i_length; // length of frame
7502
        tmp_bd_num = 0; // TX BD number
7503
        while (tmp_bd_num < 7) //
7504
        begin
7505
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7506
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7507
          if (tmp_len[0] == 0)
7508
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7509
          else
7510
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7511
          tmp_len = tmp_len + 1;
7512
          // set TX BD number
7513
          tmp_bd_num = tmp_bd_num + 1;
7514
        end
7515
        // set wrap bit
7516
        set_tx_bd_wrap(6);
7517
      end
7518
      // 54 <= num_of_frames < 70 => wrap set to TX BD 7
7519
      else if ((num_of_frames == 54) || (num_of_frames == 62))
7520
      begin
7521
        tmp_len = i_length; // length of frame
7522
        tmp_bd_num = 0; // TX BD number
7523
        while (tmp_bd_num < 8) //
7524
        begin
7525
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7526
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7527
          if (tmp_len[0] == 0)
7528
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7529
          else
7530
            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + max_tmp));
7531
          tmp_len = tmp_len + 1;
7532
          // set TX BD number
7533
          tmp_bd_num = tmp_bd_num + 1;
7534
        end
7535
        // set wrap bit
7536
        set_tx_bd_wrap(7);
7537
      end
7538
      #1;
7539
      // SET ready bit
7540
      if (num_of_frames < 10)
7541
        set_tx_bd_ready(0, 0);
7542
      else if (num_of_frames < 14)
7543
        set_tx_bd_ready((num_of_frames - 10), (num_of_frames - 10));
7544
      else if (num_of_frames < 18)
7545
        set_tx_bd_ready((num_of_frames - 14), (num_of_frames - 14));
7546
      else if (num_of_frames < 23)
7547
        set_tx_bd_ready((num_of_frames - 18), (num_of_frames - 18));
7548
      else if (num_of_frames < 28)
7549
        set_tx_bd_ready((num_of_frames - 23), (num_of_frames - 23));
7550
      else if (num_of_frames < 34)
7551
        set_tx_bd_ready((num_of_frames - 28), (num_of_frames - 28));
7552
      else if (num_of_frames < 40)
7553
        set_tx_bd_ready((num_of_frames - 34), (num_of_frames - 34));
7554
      else if (num_of_frames < 47)
7555
        set_tx_bd_ready((num_of_frames - 40), (num_of_frames - 40));
7556
      else if (num_of_frames < 54)
7557
        set_tx_bd_ready((num_of_frames - 47), (num_of_frames - 47));
7558
      else if (num_of_frames < 62)
7559
        set_tx_bd_ready((num_of_frames - 54), (num_of_frames - 54));
7560
      else if (num_of_frames < 70)
7561
        set_tx_bd_ready((num_of_frames - 62), (num_of_frames - 62));
7562
      // CHECK END OF TRANSMITION
7563
      frame_started = 0;
7564
      if (num_of_frames >= 5)
7565
        #1 check_tx_bd(num_of_bd, data);
7566
      fork
7567
      begin: fr_st3
7568
        wait (MTxEn === 1'b1); // start transmit
7569
        frame_started = 1;
7570
      end
7571
      begin
7572
        repeat (30) @(posedge mtx_clk);
7573
        if (num_of_frames < 5)
7574
        begin
7575
          if (frame_started == 1)
7576
          begin
7577
            `TIME; $display("*E Frame should NOT start!");
7578
          end
7579
          disable fr_st3;
7580
        end
7581
        else
7582
        begin
7583
          if (frame_started == 0)
7584
          begin
7585
            `TIME; $display("*W Frame should start!");
7586
            disable fr_st3;
7587
          end
7588
        end
7589
      end
7590
      join
7591
      // check packets larger than 4 bytes
7592
      if (num_of_frames >= 5)
7593
      begin
7594
        wait (MTxEn === 1'b0); // end transmit
7595
        while (data[15] === 1)
7596
        begin
7597
          #1 check_tx_bd(num_of_bd, data);
7598
          @(posedge wb_clk);
7599
        end
7600
        repeat (1) @(posedge wb_clk);
7601
        // check length of a PACKET
7602
        if (eth_phy.tx_len != (i_length + 4))
7603
        begin
7604
          `TIME; $display("*E Wrong length of the packet out from MAC");
7605
          test_fail("Wrong length of the packet out from MAC");
7606
          fail = fail + 1;
7607
        end
7608
        // check transmitted TX packet data
7609
        if (i_length[0] == 0)
7610
        begin
7611
          #1 check_tx_packet(`MEMORY_BASE, (num_of_frames * 16), i_length, tmp);
7612
        end
7613
        else
7614
        begin
7615
          #1 check_tx_packet((`MEMORY_BASE + max_tmp), (num_of_frames * 16), i_length, tmp);
7616
        end
7617
        if (tmp > 0)
7618
        begin
7619
          test_fail("Wrong data of the transmitted packet");
7620
          fail = fail + 1;
7621
        end
7622
        // check transmited TX packet CRC
7623
        #1 check_tx_crc((num_of_frames * 16), (eth_phy.tx_len - 4), 1'b0, tmp); // length without CRC
7624
        if (tmp > 0)
7625
        begin
7626
          test_fail("Wrong CRC of the transmitted packet");
7627
          fail = fail + 1;
7628
        end
7629
      end
7630
      // check WB INT signal
7631
      if ((i_length[1:0] == 2'h0) && (num_of_frames >= 5))
7632
      begin
7633
        if (wb_int !== 1'b1)
7634
        begin
7635
          `TIME; $display("*E WB INT signal should be set");
7636
          test_fail("WB INT signal should be set");
7637
          fail = fail + 1;
7638
        end
7639
      end
7640
      else
7641
      begin
7642
        if (wb_int !== 1'b0)
7643
        begin
7644
          `TIME; $display("*E WB INT signal should not be set");
7645
          test_fail("WB INT signal should not be set");
7646
          fail = fail + 1;
7647
        end
7648
      end
7649
      // check TX buffer descriptor of a packet
7650
      check_tx_bd(num_of_bd, data);
7651
      if (num_of_frames >= 5)
7652
      begin
7653
        if (i_length[1] == 1'b0) // interrupt enabled
7654
        begin
7655
          if ( (data[15:0] !== 16'h7800) && // wrap bit
7656
               (data[15:0] !== 16'h5800) ) // without wrap bit
7657
          begin
7658
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7659
            test_fail("TX buffer descriptor status is not correct");
7660
            fail = fail + 1;
7661
          end
7662
        end
7663
        else // interrupt not enabled
7664
        begin
7665
          if ( (data[15:0] !== 16'h3800) && // wrap bit
7666
               (data[15:0] !== 16'h1800) ) // without wrap bit
7667
          begin
7668
            `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7669
            test_fail("TX buffer descriptor status is not correct");
7670
            fail = fail + 1;
7671
          end
7672
        end
7673
      end
7674
      else
7675
      begin
7676
        if (data[15] !== 1'b1)
7677
        begin
7678
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
7679
          test_fail("TX buffer descriptor status is not correct");
7680
          fail = fail + 1;
7681
        end
7682
      end
7683
      // clear TX BD with wrap bit
7684
      if (num_of_frames == 63)
7685
        clear_tx_bd(16, 16);
7686
      // check interrupts
7687
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7688
      if ( ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1)) && (num_of_frames >= 5) )
7689
      begin
7690
        if ((data & `ETH_INT_TXB) !== 1'b1)
7691
        begin
7692
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
7693
          test_fail("Interrupt Transmit Buffer was not set");
7694
          fail = fail + 1;
7695
        end
7696
        if ((data & (~`ETH_INT_TXB)) !== 0)
7697
        begin
7698
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
7699
          test_fail("Other interrupts (except Transmit Buffer) were set");
7700
          fail = fail + 1;
7701
        end
7702
      end
7703
      else
7704
      begin
7705
        if (data !== 0)
7706
        begin
7707
          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
7708
          test_fail("Any of interrupts (except Transmit Buffer) was set");
7709
          fail = fail + 1;
7710
        end
7711
      end
7712
      // clear interrupts
7713
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7714
      // check WB INT signal
7715
      if (wb_int !== 1'b0)
7716
      begin
7717
        test_fail("WB INT signal should not be set");
7718
        fail = fail + 1;
7719
      end
7720
      // INTERMEDIATE DISPLAYS
7721
      if (i_length == 3)
7722
      begin
7723
        $display("    pads appending to packets is selected");
7724
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7725
        $display("    ->packets with lengths from %0d to %0d are not transmitted (length increasing by 1 byte)",
7726
                 0, 3);
7727
      end
7728
      else if (i_length == 9)
7729
      begin
7730
        $display("    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)");
7731
        $display("    ->packet with length 4 is not transmitted (length increasing by 1 byte)");
7732
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7733
                 5, 9);
7734
      end
7735
      else if (i_length == 17)
7736
      begin
7737
        $display("    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)");
7738
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7739
                 10, 17);
7740
      end
7741
      else if (i_length == 27)
7742
      begin
7743
        $display("    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)");
7744
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7745
                 18, 27);
7746
      end
7747
      else if (i_length == 40)
7748
      begin
7749
        $display("    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)");
7750
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7751
                 28, 40);
7752
      end
7753
      else if (i_length == 54)
7754
      begin
7755
        $display("    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)");
7756
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7757
                 41, 54);
7758
      end
7759
      else if (i_length == 69)
7760
      begin
7761
        $display("    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)");
7762
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
7763
                 55, 69);
7764
      end
7765
      // set length (loop variable)
7766
      i_length = i_length + 1;
7767
      // the number of frame transmitted
7768
      num_of_frames = num_of_frames + 1;
7769
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
7770
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
7771
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
7772
          (num_of_frames == 54) || (num_of_frames == 62))
7773
        num_of_bd = 0;
7774
      else
7775
        num_of_bd = num_of_bd + 1;
7776
    end
7777
    // disable TX
7778
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
7779
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7780
    @(posedge wb_clk);
7781
    if(fail == 0)
7782
      test_ok;
7783
    else
7784
      fail = 0;
7785
  end
7786
 
7787
 
7788
  ////////////////////////////////////////////////////////////////////
7789
  ////                                                            ////
7790
  ////  Test transmit packets across MAXFL value at               ////
7791
  ////  13 TX buffer decriptors ( 10Mbps ).                       ////
7792
  ////                                                            ////
7793
  ////////////////////////////////////////////////////////////////////
7794
  if (test_num == 10) // without and with padding
7795
  begin
7796
    // TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )
7797
    test_name = "TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
7798
    `TIME; $display("  TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
7799
 
7800
    // reset MAC registers
7801
    hard_reset;
7802
    // reset MAC and MII LOGIC with soft reset
7803
    reset_mac;
7804
    reset_mii;
7805
    // set wb slave response
7806
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
7807
 
7808
    max_tmp = 0;
7809
    min_tmp = 0;
7810
    num_of_frames = 0;
7811
    num_of_bd = 0;
7812
    // set 13 TX buffer descriptors - must be set before TX enable
7813
    wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7814
    // enable TX, set full-duplex mode, NO padding and CRC appending
7815
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
7816
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7817
    // prepare a packet of MAXFL + 10 length
7818
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7819
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
7820
    min_tmp = tmp[31:16];
7821
    st_data = 8'hA3;
7822
    set_tx_packet(`MEMORY_BASE, (max_tmp + 10), st_data); // length without CRC
7823
    // check WB INT signal
7824
    if (wb_int !== 1'b0)
7825
    begin
7826
      test_fail("WB INT signal should not be set");
7827
      fail = fail + 1;
7828
    end
7829
 
7830
    // write to phy's control register for 10Mbps
7831
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
7832
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
7833
    speed = 10;
7834
 
7835
    i_length = (max_tmp - 5);
7836
    while (i_length <= (max_tmp - 3)) // (max_tmp - 4) is the limit
7837
    begin
7838
$display("   i_length = %0d", i_length);
7839
      // choose generating carrier sense and collision
7840
//      case (i_length[1:0])
7841
//      2'h0: // Interrupt is generated
7842
//      begin
7843
        // Reset_tx_bd nable interrupt generation
7844
        // unmask interrupts
7845
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
7846
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7847
        // not detect carrier sense in FD and no collision
7848
        eth_phy.carrier_sense_tx_fd_detect(0);
7849
        eth_phy.collision(0);
7850
//      end
7851
//      2'h1: // Interrupt is not generated
7852
//      begin
7853
        // set_tx_bd enable interrupt generation
7854
        // mask interrupts
7855
//        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7856
        // detect carrier sense in FD and no collision
7857
//        eth_phy.carrier_sense_tx_fd_detect(1);
7858
//        eth_phy.collision(0);
7859
//      end
7860
//      2'h2: // Interrupt is not generated
7861
//      begin
7862
        // set_tx_bd disable the interrupt generation
7863
        // unmask interrupts
7864
//        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
7865
//                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7866
        // not detect carrier sense in FD and set collision
7867
//        eth_phy.carrier_sense_tx_fd_detect(0);
7868
//        eth_phy.collision(1);
7869
//      end
7870
//      default: // 2'h3: // Interrupt is not generated
7871
//      begin
7872
        // set_tx_bd disable the interrupt generation
7873
        // mask interrupts
7874
//        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
7875
        // detect carrier sense in FD and set collision
7876
//        eth_phy.carrier_sense_tx_fd_detect(1);
7877
//        eth_phy.collision(1);
7878
//      end
7879
//      endcase
7880
      // first destination address on ethernet PHY
7881
      eth_phy.set_tx_mem_addr(0);
7882
      // 
7883
if (num_of_bd == 0)
7884
begin
7885
set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
7886
set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
7887
set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
7888
set_tx_bd_wrap(2);
7889
set_tx_bd_ready(0, 0);
7890
end
7891
else if (num_of_bd == 1)
7892
set_tx_bd_ready(1, 1);
7893
else if (num_of_bd == 2)
7894
set_tx_bd_ready(2, 2);
7895
 
7896
 
7897
//        tmp_len = i_length; // length of frame
7898
//        tmp_bd_num = 0; // TX BD number
7899
//        while (tmp_bd_num < 8) // 
7900
//        begin
7901
//          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
7902
//          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
7903
//          if (tmp_len[0] == 0)
7904
//            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, `MEMORY_BASE);
7905
//          else
7906
//            set_tx_bd(tmp_bd_num, tmp_bd_num, tmp_len, !tmp_len[1], 1'b1, 1'b1, (`MEMORY_BASE + 2*max_tmp));
7907
//          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
7908
//          tmp_len = tmp_len + 1;
7909
//          // set TX BD number
7910
//          tmp_bd_num = tmp_bd_num + 1;
7911
//        end
7912
//        // set wrap bit
7913
//        set_tx_bd_wrap(7);
7914
//      // set ready bit
7915
//      set_tx_bd_ready((i_length - (max_tmp - 8)), (i_length - (max_tmp - 8)));
7916
      // CHECK END OF TRANSMITION
7917
check_tx_bd(num_of_bd, data);
7918
//      #1 check_tx_bd((i_length - (max_tmp - 8)), data);
7919
        wait (MTxEn === 1'b1); // start transmit
7920
check_tx_bd(num_of_bd, data);
7921
//        #1 check_tx_bd((i_length - (max_tmp - 8)), data);
7922
        if (data[15] !== 1)
7923
        begin
7924
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
7925
          fail = fail + 1;
7926
        end
7927
        wait (MTxEn === 1'b0); // end transmit
7928
        while (data[15] === 1)
7929
        begin
7930
check_tx_bd(num_of_bd, data);
7931
//          #1 check_tx_bd((i_length - (max_tmp - 8)), data);
7932
          @(posedge wb_clk);
7933
        end
7934
        repeat (1) @(posedge wb_clk);
7935
      // check length of a PACKET
7936
$display("   eth_phy length = %0d", eth_phy.tx_len);
7937
tmp_len = eth_phy.tx_len;
7938
#1;
7939
if (tmp_len != (i_length + 4))
7940
//      if (eth_phy.tx_len != (i_length + 4))
7941
      begin
7942
        test_fail("Wrong length of the packet out from MAC");
7943
        fail = fail + 1;
7944
      end
7945
      // checking in the following if statement is performed only for first and last 64 lengths
7946
//      if ( ((i_length + 4) <= (min_tmp + 64)) || ((i_length + 4) > (max_tmp - 64)) )
7947
//      begin
7948
        // check transmitted TX packet data
7949
//        if (i_length[0] == 0)
7950
//        begin
7951
          check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
7952
//        end
7953
//        else
7954
//        begin
7955
//          check_tx_packet((`MEMORY_BASE + 2*max_tmp), 0, i_length, tmp);
7956
//        end
7957
        if (tmp > 0)
7958
        begin
7959
          test_fail("Wrong data of the transmitted packet");
7960
          fail = fail + 1;
7961
        end
7962
        // check transmited TX packet CRC
7963
//        if (i_length[0] == 0)
7964
          check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
7965
//        else
7966
//          check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
7967
        if (tmp > 0)
7968
        begin
7969
          test_fail("Wrong CRC of the transmitted packet");
7970
          fail = fail + 1;
7971
        end
7972
//      end
7973
      // check WB INT signal
7974
//      if (i_length[1:0] == 2'h0)
7975
//      begin
7976
        if (wb_int !== 1'b1)
7977
        begin
7978
          `TIME; $display("*E WB INT signal should be set");
7979
          test_fail("WB INT signal should be set");
7980
          fail = fail + 1;
7981
        end
7982
//      end
7983
//      else
7984
//      begin
7985
//        if (wb_int !== 1'b0)
7986
//        begin
7987
//          `TIME; $display("*E WB INT signal should not be set");
7988
//          test_fail("WB INT signal should not be set");
7989
//          fail = fail + 1;
7990
//        end
7991
//      end
7992
//      // check TX buffer descriptor of a packet
7993
//      check_tx_bd((i_length - (max_tmp - 8)), data);
7994
check_tx_bd(num_of_bd, data);
7995
if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
7996
     ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
7997
//      if (i_length[1] == 1'b0) // interrupt enabled
7998
//      begin
7999
//        if ( ((data[15:0] !== 16'h7800) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
8000
//             ((data[15:0] !== 16'h5800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
8001
        begin
8002
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8003
          test_fail("TX buffer descriptor status is not correct");
8004
          fail = fail + 1;
8005
        end
8006
//      end
8007
//      else // interrupt not enabled
8008
//      begin
8009
//        if ( ((data[15:0] !== 16'h3800)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
8010
//             ((data[15:0] !== 16'h1800) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
8011
//        begin
8012
//          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8013
//          test_fail("TX buffer descriptor status is not correct");
8014
//          fail = fail + 1;
8015
//        end
8016
//      end
8017
//      // clear first half of 8 frames from TX buffer descriptor 0
8018
//      if (num_of_frames < 4)
8019
//        clear_tx_bd((i_length - (max_tmp - 8)), (i_length - (max_tmp - 8)));
8020
      // check interrupts
8021
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8022
//      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
8023
//      begin
8024
        if ((data & `ETH_INT_TXB) !== 1'b1)
8025
        begin
8026
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8027
          test_fail("Interrupt Transmit Buffer was not set");
8028
          fail = fail + 1;
8029
        end
8030
        if ((data & (~`ETH_INT_TXB)) !== 0)
8031
        begin
8032
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8033
          test_fail("Other interrupts (except Transmit Buffer) were set");
8034
          fail = fail + 1;
8035
        end
8036
//      end
8037
//      else
8038
//      begin
8039
//        if (data !== 0)
8040
//        begin
8041
//          `TIME; $display("*E Any of interrupts (except Transmit Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
8042
//          test_fail("Any of interrupts (except Transmit Buffer) was set");
8043
//          fail = fail + 1;
8044
//        end
8045
//      end
8046
      // clear interrupts
8047
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8048
      // check WB INT signal
8049
      if (wb_int !== 1'b0)
8050
      begin
8051
        test_fail("WB INT signal should not be set");
8052
        fail = fail + 1;
8053
      end
8054
      // INTERMEDIATE DISPLAYS
8055
if (num_of_bd == 0)
8056
  $display("    ->packet with length %0d sent", (i_length + 4));
8057
else if (num_of_bd == 1)
8058
  $display("    ->packet with length %0d sent", (i_length + 4));
8059
else if (num_of_bd == 2)
8060
  $display("    ->packet with length %0d sent", (i_length + 4));
8061
      // set length (loop variable)
8062
      i_length = i_length + 1;
8063
      // the number of frame transmitted
8064
      num_of_frames = num_of_frames + 1;
8065
      num_of_bd = num_of_bd + 1;
8066
      @(posedge wb_clk);
8067
    end
8068
    // disable TX
8069
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8070
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8071
    @(posedge wb_clk);
8072
    if(fail == 0)
8073
      test_ok;
8074
    else
8075
      fail = 0;
8076
  end
8077
 
8078
 
8079
  ////////////////////////////////////////////////////////////////////
8080
  ////                                                            ////
8081
  ////  Test transmit packets across MAXFL value at               ////
8082
  ////  13 TX buffer decriptors ( 100Mbps ).                      ////
8083
  ////                                                            ////
8084
  ////////////////////////////////////////////////////////////////////
8085
  if (test_num == 11) // without and with padding
8086
  begin
8087
    // TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )
8088
    test_name = "TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
8089
    `TIME; $display("  TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
8090
 
8091
    // reset MAC registers
8092
    hard_reset;
8093
    // reset MAC and MII LOGIC with soft reset
8094
    reset_mac;
8095
    reset_mii;
8096
    // set wb slave response
8097
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8098
 
8099
    max_tmp = 0;
8100
    min_tmp = 0;
8101
    num_of_frames = 0;
8102
    num_of_bd = 0;
8103
    // set 13 TX buffer descriptors - must be set before TX enable
8104
    wbm_write(`ETH_TX_BD_NUM, 32'hD, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8105
    // enable TX, set full-duplex mode, NO padding and CRC appending
8106
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8107
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8108
    // prepare a packet of MAXFL + 10 length
8109
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8110
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8111
    min_tmp = tmp[31:16];
8112
    st_data = 8'hA3;
8113
    set_tx_packet(`MEMORY_BASE, (max_tmp + 10), st_data); // length without CRC
8114
    // check WB INT signal
8115
    if (wb_int !== 1'b0)
8116
    begin
8117
      test_fail("WB INT signal should not be set");
8118
      fail = fail + 1;
8119
    end
8120
 
8121
    // write to phy's control register for 100Mbps
8122
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
8123
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
8124
    speed = 100;
8125
 
8126
    i_length = (max_tmp - 5);
8127
    while (i_length <= (max_tmp - 3)) // (max_tmp - 4) is the limit
8128
    begin
8129
      $display("   i_length = %0d", i_length);
8130
      // Reset_tx_bd nable interrupt generation
8131
      // unmask interrupts
8132
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8133
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8134
      // not detect carrier sense in FD and no collision
8135
      eth_phy.carrier_sense_tx_fd_detect(0);
8136
      eth_phy.collision(0);
8137
      // first destination address on ethernet PHY
8138
      eth_phy.set_tx_mem_addr(0);
8139
      // prepare BDs
8140
      if (num_of_bd == 0)
8141
      begin
8142
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8143
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8144
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8145
        set_tx_bd_wrap(2);
8146
        set_tx_bd_ready(0, 0);
8147
      end
8148
      else if (num_of_bd == 1)
8149
        set_tx_bd_ready(1, 1);
8150
      else if (num_of_bd == 2)
8151
        set_tx_bd_ready(2, 2);
8152
      // CHECK END OF TRANSMITION
8153
      check_tx_bd(num_of_bd, data);
8154
        wait (MTxEn === 1'b1); // start transmit
8155
      check_tx_bd(num_of_bd, data);
8156
        if (data[15] !== 1)
8157
        begin
8158
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8159
          fail = fail + 1;
8160
        end
8161
        wait (MTxEn === 1'b0); // end transmit
8162
        while (data[15] === 1)
8163
        begin
8164
      check_tx_bd(num_of_bd, data);
8165
          @(posedge wb_clk);
8166
        end
8167
        repeat (1) @(posedge wb_clk);
8168
      // check length of a PACKET
8169
      $display("   eth_phy length = %0d", eth_phy.tx_len);
8170
      tmp_len = eth_phy.tx_len;
8171
      #1;
8172
      if (tmp_len != (i_length + 4))
8173
      begin
8174
        test_fail("Wrong length of the packet out from MAC");
8175
        fail = fail + 1;
8176
      end
8177
      // checking packet
8178
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8179
      if (tmp > 0)
8180
      begin
8181
        test_fail("Wrong data of the transmitted packet");
8182
        fail = fail + 1;
8183
      end
8184
      // check transmited TX packet CRC
8185
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8186
      if (tmp > 0)
8187
      begin
8188
        test_fail("Wrong CRC of the transmitted packet");
8189
        fail = fail + 1;
8190
      end
8191
      // check WB INT signal
8192
      if (wb_int !== 1'b1)
8193
      begin
8194
        `TIME; $display("*E WB INT signal should be set");
8195
        test_fail("WB INT signal should be set");
8196
        fail = fail + 1;
8197
      end
8198
      // check TX buffer descriptor of a packet
8199
      check_tx_bd(num_of_bd, data);
8200
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8201
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8202
      begin
8203
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8204
        test_fail("TX buffer descriptor status is not correct");
8205
        fail = fail + 1;
8206
      end
8207
      // check interrupts
8208
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8209
      if ((data & `ETH_INT_TXB) !== 1'b1)
8210
      begin
8211
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8212
        test_fail("Interrupt Transmit Buffer was not set");
8213
        fail = fail + 1;
8214
      end
8215
      if ((data & (~`ETH_INT_TXB)) !== 0)
8216
      begin
8217
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8218
        test_fail("Other interrupts (except Transmit Buffer) were set");
8219
        fail = fail + 1;
8220
      end
8221
      // clear interrupts
8222
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8223
      // check WB INT signal
8224
      if (wb_int !== 1'b0)
8225
      begin
8226
        test_fail("WB INT signal should not be set");
8227
        fail = fail + 1;
8228
      end
8229
      // INTERMEDIATE DISPLAYS
8230
      if (num_of_bd == 0)
8231
        $display("    ->packet with length %0d sent", (i_length + 4));
8232
      else if (num_of_bd == 1)
8233
        $display("    ->packet with length %0d sent", (i_length + 4));
8234
      else if (num_of_bd == 2)
8235
        $display("    ->packet with length %0d sent", (i_length + 4));
8236
      // set length (loop variable)
8237
      i_length = i_length + 1;
8238
      // the number of frame transmitted
8239
      num_of_frames = num_of_frames + 1;
8240
      num_of_bd = num_of_bd + 1;
8241
      @(posedge wb_clk);
8242
    end
8243
    // disable TX
8244
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8245
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8246
    @(posedge wb_clk);
8247
    if(fail == 0)
8248
      test_ok;
8249
    else
8250
      fail = 0;
8251
  end
8252
 
8253
 
8254
  ////////////////////////////////////////////////////////////////////
8255
  ////                                                            ////
8256
  ////  Test transmit packets across changed MAXFL value at       ////
8257
  ////  47 TX buffer decriptors ( 10Mbps ).                       ////
8258
  ////                                                            ////
8259
  ////////////////////////////////////////////////////////////////////
8260
  if (test_num == 12) // without and with padding
8261
  begin
8262
    // TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )
8263
    test_name = "TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )";
8264
    `TIME; $display("  TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )");
8265
 
8266
    // reset MAC registers
8267
    hard_reset;
8268
    // reset MAC and MII LOGIC with soft reset
8269
    reset_mac;
8270
    reset_mii;
8271
    // set wb slave response
8272
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8273
 
8274
    max_tmp = 0;
8275
    min_tmp = 0;
8276
    num_of_frames = 0;
8277
    num_of_bd = 0;
8278
    // set 47 TX buffer descriptors - must be set before TX enable
8279
    wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8280
    // prepare a packet of MAXFL + 10 length
8281
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8282
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8283
    min_tmp = tmp[31:16];
8284
    // change MAXFL value
8285
    max_tmp = min_tmp + 53;
8286
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8287
    st_data = 8'h62;
8288
    set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
8289
    append_tx_crc(`MEMORY_BASE, (max_tmp - 5), 1'b0); // for first packet
8290
    // enable TX, set full-duplex mode, NO padding and NO CRC appending
8291
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
8292
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8293
    // check WB INT signal
8294
    if (wb_int !== 1'b0)
8295
    begin
8296
      test_fail("WB INT signal should not be set");
8297
      fail = fail + 1;
8298
    end
8299
 
8300
    // write to phy's control register for 10Mbps
8301
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
8302
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8303
    speed = 10;
8304
 
8305
    i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
8306
    while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
8307
    begin
8308
      $display("   i_length = %0d", i_length);
8309
      // prepare packet's CRC
8310
      if (num_of_bd == 1)
8311
        append_tx_crc(`MEMORY_BASE, (max_tmp - 4), 1'b0); // for second and third packets
8312
      // Reset_tx_bd nable interrupt generation
8313
      // unmask interrupts
8314
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8315
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8316
      // not detect carrier sense in FD and no collision
8317
      eth_phy.carrier_sense_tx_fd_detect(0);
8318
      eth_phy.collision(0);
8319
      // first destination address on ethernet PHY
8320
      eth_phy.set_tx_mem_addr(0);
8321
      // prepare BDs
8322
      if (num_of_bd == 0)
8323
      begin
8324
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8325
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8326
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8327
        set_tx_bd_wrap(2);
8328
        set_tx_bd_ready(0, 0);
8329
      end
8330
      else if (num_of_bd == 1)
8331
        set_tx_bd_ready(1, 1);
8332
      else if (num_of_bd == 2)
8333
        set_tx_bd_ready(2, 2);
8334
      // CHECK END OF TRANSMITION
8335
      check_tx_bd(num_of_bd, data);
8336
        wait (MTxEn === 1'b1); // start transmit
8337
      check_tx_bd(num_of_bd, data);
8338
        if (data[15] !== 1)
8339
        begin
8340
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8341
          fail = fail + 1;
8342
        end
8343
        wait (MTxEn === 1'b0); // end transmit
8344
        while (data[15] === 1)
8345
        begin
8346
      check_tx_bd(num_of_bd, data);
8347
          @(posedge wb_clk);
8348
        end
8349
        repeat (1) @(posedge wb_clk);
8350
      // check length of a PACKET
8351
      $display("   eth_phy length = %0d", eth_phy.tx_len);
8352
      tmp_len = eth_phy.tx_len;
8353
      #1;
8354
      if (tmp_len != (i_length + 4))
8355
      begin
8356
        test_fail("Wrong length of the packet out from MAC");
8357
        fail = fail + 1;
8358
      end
8359
      // checking packet
8360
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8361
      if (tmp > 0)
8362
      begin
8363
        test_fail("Wrong data of the transmitted packet");
8364
        fail = fail + 1;
8365
      end
8366
      // check transmited TX packet CRC
8367
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8368
      if (tmp > 0)
8369
      begin
8370
        test_fail("Wrong CRC of the transmitted packet");
8371
        fail = fail + 1;
8372
      end
8373
      // check WB INT signal
8374
      if (wb_int !== 1'b1)
8375
      begin
8376
        `TIME; $display("*E WB INT signal should be set");
8377
        test_fail("WB INT signal should be set");
8378
        fail = fail + 1;
8379
      end
8380
      // check TX buffer descriptor of a packet
8381
      check_tx_bd(num_of_bd, data);
8382
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8383
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8384
      begin
8385
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8386
        test_fail("TX buffer descriptor status is not correct");
8387
        fail = fail + 1;
8388
      end
8389
      // check interrupts
8390
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8391
      if ((data & `ETH_INT_TXB) !== 1'b1)
8392
      begin
8393
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8394
        test_fail("Interrupt Transmit Buffer was not set");
8395
        fail = fail + 1;
8396
      end
8397
      if ((data & (~`ETH_INT_TXB)) !== 0)
8398
      begin
8399
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8400
        test_fail("Other interrupts (except Transmit Buffer) were set");
8401
        fail = fail + 1;
8402
      end
8403
      // clear interrupts
8404
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8405
      // check WB INT signal
8406
      if (wb_int !== 1'b0)
8407
      begin
8408
        test_fail("WB INT signal should not be set");
8409
        fail = fail + 1;
8410
      end
8411
      // INTERMEDIATE DISPLAYS
8412
      if (num_of_bd == 0)
8413
        $display("    ->packet with length %0d sent", (i_length + 4));
8414
      else if (num_of_bd == 1)
8415
        $display("    ->packet with length %0d sent", (i_length + 4));
8416
      else if (num_of_bd == 2)
8417
        $display("    ->packet with length %0d sent", (i_length + 4));
8418
      // set length (loop variable)
8419
      i_length = i_length + 1;
8420
      // the number of frame transmitted
8421
      num_of_frames = num_of_frames + 1;
8422
      num_of_bd = num_of_bd + 1;
8423
      @(posedge wb_clk);
8424
    end
8425
    // disable TX
8426
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8427
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8428
    @(posedge wb_clk);
8429
    if(fail == 0)
8430
      test_ok;
8431
    else
8432
      fail = 0;
8433
  end
8434
 
8435
 
8436
  ////////////////////////////////////////////////////////////////////
8437
  ////                                                            ////
8438
  ////  Test transmit packets across changed MAXFL value at       ////
8439
  ////  47 TX buffer decriptors ( 100Mbps ).                      ////
8440
  ////                                                            ////
8441
  ////////////////////////////////////////////////////////////////////
8442
  if (test_num == 13) // without and with padding
8443
  begin
8444
    // TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )
8445
    test_name = "TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )";
8446
    `TIME; $display("  TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )");
8447
 
8448
    // reset MAC registers
8449
    hard_reset;
8450
    // reset MAC and MII LOGIC with soft reset
8451
    reset_mac;
8452
    reset_mii;
8453
    // set wb slave response
8454
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8455
 
8456
    max_tmp = 0;
8457
    min_tmp = 0;
8458
    num_of_frames = 0;
8459
    num_of_bd = 0;
8460
    // set 47 TX buffer descriptors - must be set before TX enable
8461
    wbm_write(`ETH_TX_BD_NUM, 32'h2F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8462
    // prepare a packet of MAXFL + 10 length
8463
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8464
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8465
    min_tmp = tmp[31:16];
8466
    // change MAXFL value
8467
    max_tmp = min_tmp + 53;
8468
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8469
    st_data = 8'h62;
8470
    set_tx_packet(`MEMORY_BASE, max_tmp, st_data); // length with CRC
8471
    append_tx_crc(`MEMORY_BASE, (max_tmp - 5), 1'b0); // for first packet
8472
    // enable TX, set full-duplex mode, NO padding and NO CRC appending
8473
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD,
8474
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8475
    // check WB INT signal
8476
    if (wb_int !== 1'b0)
8477
    begin
8478
      test_fail("WB INT signal should not be set");
8479
      fail = fail + 1;
8480
    end
8481
 
8482
    // write to phy's control register for 100Mbps
8483
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
8484
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
8485
    speed = 100;
8486
 
8487
    i_length = (max_tmp - 5); // (max_tmp - 1); // not (max_tmp - 5) because NO automatic CRC appending
8488
    while (i_length <= (max_tmp - 3)) // (max_tmp + 1)) // (max_tmp) is the limit
8489
    begin
8490
      $display("   i_length = %0d", i_length);
8491
      // prepare packet's CRC
8492
      if (num_of_bd == 1)
8493
        append_tx_crc(`MEMORY_BASE, (max_tmp - 4), 1'b0); // for second and third packets
8494
      // Reset_tx_bd nable interrupt generation
8495
      // unmask interrupts
8496
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8497
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8498
      // not detect carrier sense in FD and no collision
8499
      eth_phy.carrier_sense_tx_fd_detect(0);
8500
      eth_phy.collision(0);
8501
      // first destination address on ethernet PHY
8502
      eth_phy.set_tx_mem_addr(0);
8503
      // prepare BDs
8504
      if (num_of_bd == 0)
8505
      begin
8506
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8507
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8508
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8509
        set_tx_bd_wrap(2);
8510
        set_tx_bd_ready(0, 0);
8511
      end
8512
      else if (num_of_bd == 1)
8513
        set_tx_bd_ready(1, 1);
8514
      else if (num_of_bd == 2)
8515
        set_tx_bd_ready(2, 2);
8516
      // CHECK END OF TRANSMITION
8517
      check_tx_bd(num_of_bd, data);
8518
        wait (MTxEn === 1'b1); // start transmit
8519
      check_tx_bd(num_of_bd, data);
8520
        if (data[15] !== 1)
8521
        begin
8522
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8523
          fail = fail + 1;
8524
        end
8525
        wait (MTxEn === 1'b0); // end transmit
8526
        while (data[15] === 1)
8527
        begin
8528
      check_tx_bd(num_of_bd, data);
8529
          @(posedge wb_clk);
8530
        end
8531
        repeat (1) @(posedge wb_clk);
8532
      // check length of a PACKET
8533
      $display("   eth_phy length = %0d", eth_phy.tx_len);
8534
      tmp_len = eth_phy.tx_len;
8535
      #1;
8536
      if (tmp_len != (i_length + 4))
8537
      begin
8538
        test_fail("Wrong length of the packet out from MAC");
8539
        fail = fail + 1;
8540
      end
8541
      // checking packet
8542
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8543
      if (tmp > 0)
8544
      begin
8545
        test_fail("Wrong data of the transmitted packet");
8546
        fail = fail + 1;
8547
      end
8548
      // check transmited TX packet CRC
8549
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8550
      if (tmp > 0)
8551
      begin
8552
        test_fail("Wrong CRC of the transmitted packet");
8553
        fail = fail + 1;
8554
      end
8555
      // check WB INT signal
8556
      if (wb_int !== 1'b1)
8557
      begin
8558
        `TIME; $display("*E WB INT signal should be set");
8559
        test_fail("WB INT signal should be set");
8560
        fail = fail + 1;
8561
      end
8562
      // check TX buffer descriptor of a packet
8563
      check_tx_bd(num_of_bd, data);
8564
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8565
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8566
      begin
8567
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8568
        test_fail("TX buffer descriptor status is not correct");
8569
        fail = fail + 1;
8570
      end
8571
      // check interrupts
8572
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8573
      if ((data & `ETH_INT_TXB) !== 1'b1)
8574
      begin
8575
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8576
        test_fail("Interrupt Transmit Buffer was not set");
8577
        fail = fail + 1;
8578
      end
8579
      if ((data & (~`ETH_INT_TXB)) !== 0)
8580
      begin
8581
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8582
        test_fail("Other interrupts (except Transmit Buffer) were set");
8583
        fail = fail + 1;
8584
      end
8585
      // clear interrupts
8586
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8587
      // check WB INT signal
8588
      if (wb_int !== 1'b0)
8589
      begin
8590
        test_fail("WB INT signal should not be set");
8591
        fail = fail + 1;
8592
      end
8593
      // INTERMEDIATE DISPLAYS
8594
      if (num_of_bd == 0)
8595
        $display("    ->packet with length %0d sent", (i_length + 4));
8596
      else if (num_of_bd == 1)
8597
        $display("    ->packet with length %0d sent", (i_length + 4));
8598
      else if (num_of_bd == 2)
8599
        $display("    ->packet with length %0d sent", (i_length + 4));
8600
      // set length (loop variable)
8601
      i_length = i_length + 1;
8602
      // the number of frame transmitted
8603
      num_of_frames = num_of_frames + 1;
8604
      num_of_bd = num_of_bd + 1;
8605
      @(posedge wb_clk);
8606
    end
8607
    // disable TX
8608
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8609
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8610
    @(posedge wb_clk);
8611
    if(fail == 0)
8612
      test_ok;
8613
    else
8614
      fail = 0;
8615
  end
8616
 
8617
 
8618
  ////////////////////////////////////////////////////////////////////
8619
  ////                                                            ////
8620
  ////  Test transmit packets across changed MINFL value at       ////
8621
  ////  7 TX buffer decriptors ( 10Mbps ).                        ////
8622
  ////                                                            ////
8623
  ////////////////////////////////////////////////////////////////////
8624
  if (test_num == 14) // without and with padding
8625
  begin
8626
    // TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )
8627
    test_name = "TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )";
8628
    `TIME; $display("  TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )");
8629
 
8630
    // reset MAC registers
8631
    hard_reset;
8632
    // reset MAC and MII LOGIC with soft reset
8633
    reset_mac;
8634
    reset_mii;
8635
    // set wb slave response
8636
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8637
 
8638
    max_tmp = 0;
8639
    min_tmp = 0;
8640
    num_of_frames = 0;
8641
    num_of_bd = 0;
8642
    // set 7 TX buffer descriptors - must be set before TX enable
8643
    wbm_write(`ETH_TX_BD_NUM, 32'h7, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8644
    // prepare a packet of MAXFL + 10 length
8645
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8646
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8647
    min_tmp = tmp[31:16];
8648
    // change MINFL value
8649
    min_tmp = max_tmp - 177;
8650
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8651
    st_data = 8'h62;
8652
    set_tx_packet(`MEMORY_BASE, min_tmp, st_data); // length without CRC
8653
    // enable TX, set full-duplex mode, padding and CRC appending
8654
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8655
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8656
    // check WB INT signal
8657
    if (wb_int !== 1'b0)
8658
    begin
8659
      test_fail("WB INT signal should not be set");
8660
      fail = fail + 1;
8661
    end
8662
 
8663
    // write to phy's control register for 10Mbps
8664
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
8665
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
8666
    speed = 10;
8667
 
8668
    i_length = (min_tmp - 5);
8669
    while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
8670
    begin
8671
      $display("   i_length = %0d", i_length);
8672
      // Reset_tx_bd nable interrupt generation
8673
      // unmask interrupts
8674
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8675
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8676
      // not detect carrier sense in FD and no collision
8677
      eth_phy.carrier_sense_tx_fd_detect(0);
8678
      eth_phy.collision(0);
8679
      // first destination address on ethernet PHY
8680
      eth_phy.set_tx_mem_addr(0);
8681
      // prepare BDs
8682
      if (num_of_bd == 0)
8683
      begin
8684
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8685
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8686
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8687
        set_tx_bd_wrap(2);
8688
        set_tx_bd_ready(0, 0);
8689
      end
8690
      else if (num_of_bd == 1)
8691
        set_tx_bd_ready(1, 1);
8692
      else if (num_of_bd == 2)
8693
        set_tx_bd_ready(2, 2);
8694
      // CHECK END OF TRANSMITION
8695
      check_tx_bd(num_of_bd, data);
8696
        wait (MTxEn === 1'b1); // start transmit
8697
      check_tx_bd(num_of_bd, data);
8698
        if (data[15] !== 1)
8699
        begin
8700
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8701
          fail = fail + 1;
8702
        end
8703
        wait (MTxEn === 1'b0); // end transmit
8704
        while (data[15] === 1)
8705
        begin
8706
      check_tx_bd(num_of_bd, data);
8707
          @(posedge wb_clk);
8708
        end
8709
        repeat (1) @(posedge wb_clk);
8710
      // check length of a PACKET
8711
      $display("   eth_phy length = %0d", eth_phy.tx_len);
8712
      tmp_len = eth_phy.tx_len;
8713
      #1;
8714
      if (tmp_len != (i_length + 4))
8715
      begin
8716
        test_fail("Wrong length of the packet out from MAC");
8717
        fail = fail + 1;
8718
      end
8719
      // checking packet
8720
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8721
      if (tmp > 0)
8722
      begin
8723
        test_fail("Wrong data of the transmitted packet");
8724
        fail = fail + 1;
8725
      end
8726
      // check transmited TX packet CRC
8727
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8728
      if (tmp > 0)
8729
      begin
8730
        test_fail("Wrong CRC of the transmitted packet");
8731
        fail = fail + 1;
8732
      end
8733
      // check WB INT signal
8734
      if (wb_int !== 1'b1)
8735
      begin
8736
        `TIME; $display("*E WB INT signal should be set");
8737
        test_fail("WB INT signal should be set");
8738
        fail = fail + 1;
8739
      end
8740
      // check TX buffer descriptor of a packet
8741
      check_tx_bd(num_of_bd, data);
8742
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8743
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8744
      begin
8745
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8746
        test_fail("TX buffer descriptor status is not correct");
8747
        fail = fail + 1;
8748
      end
8749
      // check interrupts
8750
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8751
      if ((data & `ETH_INT_TXB) !== 1'b1)
8752
      begin
8753
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8754
        test_fail("Interrupt Transmit Buffer was not set");
8755
        fail = fail + 1;
8756
      end
8757
      if ((data & (~`ETH_INT_TXB)) !== 0)
8758
      begin
8759
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8760
        test_fail("Other interrupts (except Transmit Buffer) were set");
8761
        fail = fail + 1;
8762
      end
8763
      // clear interrupts
8764
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8765
      // check WB INT signal
8766
      if (wb_int !== 1'b0)
8767
      begin
8768
        test_fail("WB INT signal should not be set");
8769
        fail = fail + 1;
8770
      end
8771
      // INTERMEDIATE DISPLAYS
8772
      if (num_of_bd == 0)
8773
        $display("    ->packet with length %0d sent", (i_length + 4));
8774
      else if (num_of_bd == 1)
8775
        $display("    ->packet with length %0d sent", (i_length + 4));
8776
      else if (num_of_bd == 2)
8777
        $display("    ->packet with length %0d sent", (i_length + 4));
8778
      // set length (loop variable)
8779
      i_length = i_length + 1;
8780
      // the number of frame transmitted
8781
      num_of_frames = num_of_frames + 1;
8782
      num_of_bd = num_of_bd + 1;
8783
      @(posedge wb_clk);
8784
    end
8785
    // disable TX
8786
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8787
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8788
    @(posedge wb_clk);
8789
    if(fail == 0)
8790
      test_ok;
8791
    else
8792
      fail = 0;
8793
  end
8794
 
8795
 
8796
  ////////////////////////////////////////////////////////////////////
8797
  ////                                                            ////
8798
  ////  Test transmit packets across changed MINFL value at       ////
8799
  ////  7 TX buffer decriptors ( 100Mbps ).                       ////
8800
  ////                                                            ////
8801
  ////////////////////////////////////////////////////////////////////
8802
  if (test_num == 15) // without and with padding
8803
  begin
8804
    // TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )
8805
    test_name = "TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )";
8806
    `TIME; $display("  TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )");
8807
 
8808
    // reset MAC registers
8809
    hard_reset;
8810
    // reset MAC and MII LOGIC with soft reset
8811
    reset_mac;
8812
    reset_mii;
8813
    // set wb slave response
8814
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8815
 
8816
    max_tmp = 0;
8817
    min_tmp = 0;
8818
    num_of_frames = 0;
8819
    num_of_bd = 0;
8820
    // set 7 TX buffer descriptors - must be set before TX enable
8821
    wbm_write(`ETH_TX_BD_NUM, 32'h7, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8822
    // prepare a packet of MAXFL + 10 length
8823
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8824
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
8825
    min_tmp = tmp[31:16];
8826
    // change MINFL value
8827
    min_tmp = max_tmp - 177;
8828
    wbm_write(`ETH_PACKETLEN, {min_tmp, max_tmp}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8829
    st_data = 8'h62;
8830
    set_tx_packet(`MEMORY_BASE, min_tmp, st_data); // length without CRC
8831
    // enable TX, set full-duplex mode, padding and CRC appending
8832
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
8833
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8834
    // check WB INT signal
8835
    if (wb_int !== 1'b0)
8836
    begin
8837
      test_fail("WB INT signal should not be set");
8838
      fail = fail + 1;
8839
    end
8840
 
8841
    // write to phy's control register for 100Mbps
8842
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
8843
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
8844
    speed = 100;
8845
 
8846
    i_length = (min_tmp - 5);
8847
    while (i_length <= (min_tmp - 3)) // (min_tmp - 4) is the limit
8848
    begin
8849
      $display("   i_length = %0d", i_length);
8850
      // Reset_tx_bd nable interrupt generation
8851
      // unmask interrupts
8852
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
8853
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8854
      // not detect carrier sense in FD and no collision
8855
      eth_phy.carrier_sense_tx_fd_detect(0);
8856
      eth_phy.collision(0);
8857
      // first destination address on ethernet PHY
8858
      eth_phy.set_tx_mem_addr(0);
8859
      // prepare BDs
8860
      if (num_of_bd == 0)
8861
      begin
8862
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8863
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8864
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
8865
        set_tx_bd_wrap(2);
8866
        set_tx_bd_ready(0, 0);
8867
      end
8868
      else if (num_of_bd == 1)
8869
        set_tx_bd_ready(1, 1);
8870
      else if (num_of_bd == 2)
8871
        set_tx_bd_ready(2, 2);
8872
      // CHECK END OF TRANSMITION
8873
      check_tx_bd(num_of_bd, data);
8874
        wait (MTxEn === 1'b1); // start transmit
8875
      check_tx_bd(num_of_bd, data);
8876
        if (data[15] !== 1)
8877
        begin
8878
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
8879
          fail = fail + 1;
8880
        end
8881
        wait (MTxEn === 1'b0); // end transmit
8882
        while (data[15] === 1)
8883
        begin
8884
      check_tx_bd(num_of_bd, data);
8885
          @(posedge wb_clk);
8886
        end
8887
        repeat (1) @(posedge wb_clk);
8888
      // check length of a PACKET
8889
      $display("   eth_phy length = %0d", eth_phy.tx_len);
8890
      tmp_len = eth_phy.tx_len;
8891
      #1;
8892
      if (tmp_len != (i_length + 4))
8893
      begin
8894
        test_fail("Wrong length of the packet out from MAC");
8895
        fail = fail + 1;
8896
      end
8897
      // checking packet
8898
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
8899
      if (tmp > 0)
8900
      begin
8901
        test_fail("Wrong data of the transmitted packet");
8902
        fail = fail + 1;
8903
      end
8904
      // check transmited TX packet CRC
8905
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
8906
      if (tmp > 0)
8907
      begin
8908
        test_fail("Wrong CRC of the transmitted packet");
8909
        fail = fail + 1;
8910
      end
8911
      // check WB INT signal
8912
      if (wb_int !== 1'b1)
8913
      begin
8914
        `TIME; $display("*E WB INT signal should be set");
8915
        test_fail("WB INT signal should be set");
8916
        fail = fail + 1;
8917
      end
8918
      // check TX buffer descriptor of a packet
8919
      check_tx_bd(num_of_bd, data);
8920
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 2)) || // wrap bit
8921
           ((data[15:0] !== 16'h5800) && (num_of_bd < 2)) )   // without wrap bit
8922
      begin
8923
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
8924
        test_fail("TX buffer descriptor status is not correct");
8925
        fail = fail + 1;
8926
      end
8927
      // check interrupts
8928
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8929
      if ((data & `ETH_INT_TXB) !== 1'b1)
8930
      begin
8931
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
8932
        test_fail("Interrupt Transmit Buffer was not set");
8933
        fail = fail + 1;
8934
      end
8935
      if ((data & (~`ETH_INT_TXB)) !== 0)
8936
      begin
8937
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
8938
        test_fail("Other interrupts (except Transmit Buffer) were set");
8939
        fail = fail + 1;
8940
      end
8941
      // clear interrupts
8942
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8943
      // check WB INT signal
8944
      if (wb_int !== 1'b0)
8945
      begin
8946
        test_fail("WB INT signal should not be set");
8947
        fail = fail + 1;
8948
      end
8949
      // INTERMEDIATE DISPLAYS
8950
      if (num_of_bd == 0)
8951
        $display("    ->packet with length %0d sent", (i_length + 4));
8952
      else if (num_of_bd == 1)
8953
        $display("    ->packet with length %0d sent", (i_length + 4));
8954
      else if (num_of_bd == 2)
8955
        $display("    ->packet with length %0d sent", (i_length + 4));
8956
      // set length (loop variable)
8957
      i_length = i_length + 1;
8958
      // the number of frame transmitted
8959
      num_of_frames = num_of_frames + 1;
8960
      num_of_bd = num_of_bd + 1;
8961
      @(posedge wb_clk);
8962
    end
8963
    // disable TX
8964
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
8965
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
8966
    @(posedge wb_clk);
8967
    if(fail == 0)
8968
      test_ok;
8969
    else
8970
      fail = 0;
8971
  end
8972
 
8973
 
8974
  ////////////////////////////////////////////////////////////////////
8975
  ////                                                            ////
8976
  ////  Test transmit packets across MAXFL with HUGEN at          ////
8977
  ////  19 TX buffer decriptors ( 10Mbps ).                       ////
8978
  ////                                                            ////
8979
  ////////////////////////////////////////////////////////////////////
8980
  if (test_num == 16) // without and with padding
8981
  begin
8982
    // TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )
8983
    test_name = "TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )";
8984
    `TIME; $display("  TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )");
8985
 
8986
    // reset MAC registers
8987
    hard_reset;
8988
    // reset MAC and MII LOGIC with soft reset
8989
    reset_mac;
8990
    reset_mii;
8991
    // set wb slave response
8992
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
8993
 
8994
    max_tmp = 0;
8995
    min_tmp = 0;
8996
    num_of_frames = 0;
8997
    num_of_bd = 0;
8998
    // set 19 TX buffer descriptors - must be set before TX enable
8999
    wbm_write(`ETH_TX_BD_NUM, 32'h13, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9000
    // prepare a packet of 64k - 1 length (16'hFFFF)
9001
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9002
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9003
    min_tmp = tmp[31:16];
9004
    st_data = 8'h8D;
9005
    set_tx_packet(`MEMORY_BASE, 16'hFFFF, st_data); // length with CRC
9006
    // enable TX, set full-duplex mode, NO padding, CRC appending and huge enabled
9007
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_HUGEN,
9008
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9009
    // check WB INT signal
9010
    if (wb_int !== 1'b0)
9011
    begin
9012
      test_fail("WB INT signal should not be set");
9013
      fail = fail + 1;
9014
    end
9015
 
9016
    // write to phy's control register for 10Mbps
9017
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
9018
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
9019
    speed = 10;
9020
 
9021
    i_length = (max_tmp - 5); // (max_tmp - 4) is the MAXFL limit
9022
    while (i_length <= (16'hFFFF - 4)) // (16'hFFFF - 4) is the limit
9023
    begin
9024
      $display("   i_length = %0d", i_length);
9025
      // Reset_tx_bd nable interrupt generation
9026
      // unmask interrupts
9027
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9028
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9029
      // not detect carrier sense in FD and no collision
9030
      eth_phy.carrier_sense_tx_fd_detect(0);
9031
      eth_phy.collision(0);
9032
      // first destination address on ethernet PHY
9033
      eth_phy.set_tx_mem_addr(0);
9034
      // prepare BDs
9035
      if (num_of_bd == 0)
9036
      begin
9037
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9038
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9039
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9040
        set_tx_bd(3, 3, (16'hFFFF - 5), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9041
        set_tx_bd(4, 4, (16'hFFFF - 4), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9042
        set_tx_bd_wrap(4);
9043
        set_tx_bd_ready(0, 0);
9044
      end
9045
      else if (num_of_bd == 1)
9046
        set_tx_bd_ready(1, 1);
9047
      else if (num_of_bd == 2)
9048
        set_tx_bd_ready(2, 2);
9049
      else if (num_of_bd == 3)
9050
        set_tx_bd_ready(3, 3);
9051
      else if (num_of_bd == 4)
9052
        set_tx_bd_ready(4, 4);
9053
      // CHECK END OF TRANSMITION
9054
      check_tx_bd(num_of_bd, data);
9055
        wait (MTxEn === 1'b1); // start transmit
9056
      check_tx_bd(num_of_bd, data);
9057
        if (data[15] !== 1)
9058
        begin
9059
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9060
          fail = fail + 1;
9061
        end
9062
        wait (MTxEn === 1'b0); // end transmit
9063
        while (data[15] === 1)
9064
        begin
9065
      check_tx_bd(num_of_bd, data);
9066
          @(posedge wb_clk);
9067
        end
9068
        repeat (1) @(posedge wb_clk);
9069
      // check length of a PACKET
9070
      $display("   eth_phy length = %0d", eth_phy.tx_len);
9071
      tmp_len = eth_phy.tx_len;
9072
      #1;
9073
      if (tmp_len != (i_length + 4))
9074
      begin
9075
        test_fail("Wrong length of the packet out from MAC");
9076
        fail = fail + 1;
9077
      end
9078
      // checking packet
9079
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
9080
      if (tmp > 0)
9081
      begin
9082
        test_fail("Wrong data of the transmitted packet");
9083
        fail = fail + 1;
9084
      end
9085
      // check transmited TX packet CRC
9086
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
9087
      if (tmp > 0)
9088
      begin
9089
        test_fail("Wrong CRC of the transmitted packet");
9090
        fail = fail + 1;
9091
      end
9092
      // check WB INT signal
9093
      if (wb_int !== 1'b1)
9094
      begin
9095
        `TIME; $display("*E WB INT signal should be set");
9096
        test_fail("WB INT signal should be set");
9097
        fail = fail + 1;
9098
      end
9099
      // check TX buffer descriptor of a packet
9100
      check_tx_bd(num_of_bd, data);
9101
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 4)) || // wrap bit
9102
           ((data[15:0] !== 16'h5800) && (num_of_bd < 4)) )   // without wrap bit
9103
      begin
9104
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9105
        test_fail("TX buffer descriptor status is not correct");
9106
        fail = fail + 1;
9107
      end
9108
      // check interrupts
9109
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9110
      if ((data & `ETH_INT_TXB) !== 1'b1)
9111
      begin
9112
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9113
        test_fail("Interrupt Transmit Buffer was not set");
9114
        fail = fail + 1;
9115
      end
9116
      if ((data & (~`ETH_INT_TXB)) !== 0)
9117
      begin
9118
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9119
        test_fail("Other interrupts (except Transmit Buffer) were set");
9120
        fail = fail + 1;
9121
      end
9122
      // clear interrupts
9123
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9124
      // check WB INT signal
9125
      if (wb_int !== 1'b0)
9126
      begin
9127
        test_fail("WB INT signal should not be set");
9128
        fail = fail + 1;
9129
      end
9130
      // INTERMEDIATE DISPLAYS
9131
      $display("    ->packet with length %0d sent", (i_length + 4));
9132
      // set length (loop variable)
9133
      if ((num_of_bd < 2) || (num_of_bd >= 3))
9134
        i_length = i_length + 1;
9135
      else if (num_of_bd == 2)
9136
        i_length = (16'hFFFF - 5);
9137
      // the number of frame transmitted
9138
      num_of_frames = num_of_frames + 1;
9139
      num_of_bd = num_of_bd + 1;
9140
      @(posedge wb_clk);
9141
    end
9142
    // disable TX
9143
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9144
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9145
    @(posedge wb_clk);
9146
    if(fail == 0)
9147
      test_ok;
9148
    else
9149
      fail = 0;
9150
  end
9151
 
9152
 
9153
  ////////////////////////////////////////////////////////////////////
9154
  ////                                                            ////
9155
  ////  Test transmit packets across MAXFL with HUGEN at          ////
9156
  ////  19 TX buffer decriptors ( 100Mbps ).                      ////
9157
  ////                                                            ////
9158
  ////////////////////////////////////////////////////////////////////
9159
  if (test_num == 17) // without and with padding
9160
  begin
9161
    // TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )
9162
    test_name = "TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )";
9163
    `TIME; $display("  TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )");
9164
 
9165
    // reset MAC registers
9166
    hard_reset;
9167
    // reset MAC and MII LOGIC with soft reset
9168
    reset_mac;
9169
    reset_mii;
9170
    // set wb slave response
9171
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9172
 
9173
    max_tmp = 0;
9174
    min_tmp = 0;
9175
    num_of_frames = 0;
9176
    num_of_bd = 0;
9177
    // set 19 TX buffer descriptors - must be set before TX enable
9178
    wbm_write(`ETH_TX_BD_NUM, 32'h13, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9179
    // prepare a packet of 64k - 1 length (16'hFFFF)
9180
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9181
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9182
    min_tmp = tmp[31:16];
9183
    st_data = 8'h8D;
9184
    set_tx_packet(`MEMORY_BASE, 16'hFFFF, st_data); // length with CRC
9185
    // enable TX, set full-duplex mode, NO padding, CRC appending and huge enabled
9186
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN | `ETH_MODER_HUGEN,
9187
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9188
    // check WB INT signal
9189
    if (wb_int !== 1'b0)
9190
    begin
9191
      test_fail("WB INT signal should not be set");
9192
      fail = fail + 1;
9193
    end
9194
 
9195
    // write to phy's control register for 100Mbps
9196
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
9197
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
9198
    speed = 100;
9199
 
9200
    i_length = (max_tmp - 5); // (max_tmp - 4) is the MAXFL limit
9201
    while (i_length <= (16'hFFFF - 4)) // (16'hFFFF - 4) is the limit
9202
    begin
9203
      $display("   i_length = %0d", i_length);
9204
      // Reset_tx_bd nable interrupt generation
9205
      // unmask interrupts
9206
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9207
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9208
      // not detect carrier sense in FD and no collision
9209
      eth_phy.carrier_sense_tx_fd_detect(0);
9210
      eth_phy.collision(0);
9211
      // first destination address on ethernet PHY
9212
      eth_phy.set_tx_mem_addr(0);
9213
      // prepare BDs
9214
      if (num_of_bd == 0)
9215
      begin
9216
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9217
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9218
        set_tx_bd(2, 2, i_length+2, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9219
        set_tx_bd(3, 3, (16'hFFFF - 5), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9220
        set_tx_bd(4, 4, (16'hFFFF - 4), 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9221
        set_tx_bd_wrap(4);
9222
        set_tx_bd_ready(0, 0);
9223
      end
9224
      else if (num_of_bd == 1)
9225
        set_tx_bd_ready(1, 1);
9226
      else if (num_of_bd == 2)
9227
        set_tx_bd_ready(2, 2);
9228
      else if (num_of_bd == 3)
9229
        set_tx_bd_ready(3, 3);
9230
      else if (num_of_bd == 4)
9231
        set_tx_bd_ready(4, 4);
9232
      // CHECK END OF TRANSMITION
9233
      check_tx_bd(num_of_bd, data);
9234
        wait (MTxEn === 1'b1); // start transmit
9235
      check_tx_bd(num_of_bd, data);
9236
        if (data[15] !== 1)
9237
        begin
9238
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9239
          fail = fail + 1;
9240
        end
9241
        wait (MTxEn === 1'b0); // end transmit
9242
        while (data[15] === 1)
9243
        begin
9244
      check_tx_bd(num_of_bd, data);
9245
          @(posedge wb_clk);
9246
        end
9247
        repeat (1) @(posedge wb_clk);
9248
      // check length of a PACKET
9249
      $display("   eth_phy length = %0d", eth_phy.tx_len);
9250
      tmp_len = eth_phy.tx_len;
9251
      #1;
9252
      if (tmp_len != (i_length + 4))
9253
      begin
9254
        test_fail("Wrong length of the packet out from MAC");
9255
        fail = fail + 1;
9256
      end
9257
      // checking packet
9258
      check_tx_packet(`MEMORY_BASE, 0, i_length, tmp);
9259
      if (tmp > 0)
9260
      begin
9261
        test_fail("Wrong data of the transmitted packet");
9262
        fail = fail + 1;
9263
      end
9264
      // check transmited TX packet CRC
9265
      check_tx_crc(0, i_length, 1'b0, tmp); // length without CRC
9266
      if (tmp > 0)
9267
      begin
9268
        test_fail("Wrong CRC of the transmitted packet");
9269
        fail = fail + 1;
9270
      end
9271
      // check WB INT signal
9272
      if (wb_int !== 1'b1)
9273
      begin
9274
        `TIME; $display("*E WB INT signal should be set");
9275
        test_fail("WB INT signal should be set");
9276
        fail = fail + 1;
9277
      end
9278
      // check TX buffer descriptor of a packet
9279
      check_tx_bd(num_of_bd, data);
9280
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 4)) || // wrap bit
9281
           ((data[15:0] !== 16'h5800) && (num_of_bd < 4)) )   // without wrap bit
9282
      begin
9283
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9284
        test_fail("TX buffer descriptor status is not correct");
9285
        fail = fail + 1;
9286
      end
9287
      // check interrupts
9288
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9289
      if ((data & `ETH_INT_TXB) !== 1'b1)
9290
      begin
9291
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9292
        test_fail("Interrupt Transmit Buffer was not set");
9293
        fail = fail + 1;
9294
      end
9295
      if ((data & (~`ETH_INT_TXB)) !== 0)
9296
      begin
9297
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9298
        test_fail("Other interrupts (except Transmit Buffer) were set");
9299
        fail = fail + 1;
9300
      end
9301
      // clear interrupts
9302
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9303
      // check WB INT signal
9304
      if (wb_int !== 1'b0)
9305
      begin
9306
        test_fail("WB INT signal should not be set");
9307
        fail = fail + 1;
9308
      end
9309
      // INTERMEDIATE DISPLAYS
9310
      $display("    ->packet with length %0d sent", (i_length + 4));
9311
      // set length (loop variable)
9312
      if ((num_of_bd < 2) || (num_of_bd >= 3))
9313
        i_length = i_length + 1;
9314
      else if (num_of_bd == 2)
9315
        i_length = (16'hFFFF - 5);
9316
      // the number of frame transmitted
9317
      num_of_frames = num_of_frames + 1;
9318
      num_of_bd = num_of_bd + 1;
9319
      @(posedge wb_clk);
9320
    end
9321
    // disable TX
9322
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9323
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9324
    @(posedge wb_clk);
9325
    if(fail == 0)
9326
      test_ok;
9327
    else
9328
      fail = 0;
9329
  end
9330
 
9331
 
9332
  ////////////////////////////////////////////////////////////////////
9333
  ////                                                            ////
9334
  ////  Test IPG during Back-to-Back transmit at                  ////
9335
  ////  88 TX buffer decriptors ( 10Mbps ).                       ////
9336
  ////                                                            ////
9337
  ////////////////////////////////////////////////////////////////////
9338
  if (test_num == 18) // without and with padding
9339
  begin
9340
    // TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )
9341
    test_name = "TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )";
9342
    `TIME; $display("  TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )");
9343
 
9344
    // reset MAC registers
9345
    hard_reset;
9346
    // reset MAC and MII LOGIC with soft reset
9347
    reset_mac;
9348
    reset_mii;
9349
    // set wb slave response
9350
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9351
 
9352
    max_tmp = 0;
9353
    min_tmp = 0;
9354
    num_of_frames = 0;
9355
    num_of_bd = 0;
9356
    tmp_ipgt = 0;
9357
    // set 88 TX buffer descriptors - must be set before TX enable
9358
    wbm_write(`ETH_TX_BD_NUM, 32'h58, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9359
    // enable TX, set full-duplex mode, NO padding and CRC appending
9360
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9361
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9362
    // prepare two packets of MAXFL length
9363
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9364
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9365
    min_tmp = tmp[31:16];
9366
    st_data = 8'h29;
9367
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
9368
    // check WB INT signal
9369
    if (wb_int !== 1'b0)
9370
    begin
9371
      test_fail("WB INT signal should not be set");
9372
      fail = fail + 1;
9373
    end
9374
 
9375
    // write to phy's control register for 10Mbps
9376
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
9377
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
9378
    speed = 10;
9379
 
9380
    i_length = (min_tmp - 4);
9381
    while (i_length < (max_tmp - 4))
9382
    begin
9383
      // disable TX, set full-duplex mode, NO padding and CRC appending
9384
      wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9385
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9386
      // set IPGT register
9387
      wbm_write(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9388
      // enable TX, set full-duplex mode, NO padding and CRC appending
9389
      wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9390
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9391
      // Reset_tx_bd enable interrupt generation
9392
      // unmask interrupts
9393
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9394
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9395
      // not detect carrier sense in FD and no collision
9396
      eth_phy.carrier_sense_tx_fd_detect(0);
9397
      eth_phy.collision(0);
9398
      // first destination address on ethernet PHY
9399
      eth_phy.set_tx_mem_addr(0);
9400
      // prepare BDs
9401
      if (num_of_bd == 0)
9402
      begin
9403
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9404
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9405
        set_tx_bd_wrap(1);
9406
        set_tx_bd_ready(0, 0);
9407
        set_tx_bd_ready(1, 1);
9408
      end
9409
      // CHECK END OF TWO TRANSMITIONs
9410
      // wait for first transmit to end
9411
      check_tx_bd(num_of_bd, data);
9412
      wait (MTxEn === 1'b1); // start transmit
9413
      if (data[15] !== 1)
9414
      begin
9415
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9416
        fail = fail + 1;
9417
      end
9418
      wait (MTxEn === 1'b0); // end transmit
9419
      num_of_frames = num_of_frames + 1;
9420
      num_of_bd = num_of_bd + 1;
9421
      #Tp;
9422
      // destination address on ethernet PHY
9423
      eth_phy.set_tx_mem_addr(0);
9424
      i1 = 0;
9425
      i2 = 0;
9426
      // count IPG clock periods
9427
      fork
9428
        begin
9429
          wait (MTxEn === 1'b1); // start second transmit
9430
          #Tp;
9431
          disable count_rising;
9432
          disable count_falling;
9433
        end
9434
        begin: count_rising
9435
          forever
9436
          begin
9437
            @(posedge mtx_clk);
9438
            i1 = i1 + 1;
9439
            #Tp;
9440
          end
9441
        end
9442
        begin: count_falling
9443
          forever
9444
          begin
9445
            @(negedge mtx_clk);
9446
            i2 = i2 + 1;
9447
            #Tp;
9448
          end
9449
        end
9450
      join
9451
      // check IPG length - INTERMEDIATE DISPLAYS
9452
      if((i1 == i2) && (i1 >= (tmp_ipgt + 3)))
9453
      begin
9454
        $display("    ->IPG with %0d mtx_clk periods (min %0d) between packets with lengths %0d and %0d checked",
9455
                  i1, (tmp_ipgt + 3), (i_length + 4), (i_length + 4 + 1));
9456
      end
9457
      else
9458
      begin
9459
        `TIME; $display("*E IPG is not correct: (%0d + %0d) / 2, requested: %d", i1, i2, (tmp_ipgt + 3));
9460
        fail = fail + 1;
9461
        test_fail("IPG is not correct");
9462
      end
9463
      // wait for second transmit to end
9464
      wait (MTxEn === 1'b0); // end second transmit
9465
      while (data[15] === 1)
9466
      begin
9467
        check_tx_bd(num_of_bd, data);
9468
        @(posedge wb_clk);
9469
      end
9470
      repeat (1) @(posedge wb_clk);
9471
      // check length of a second PACKET
9472
      tmp_len = eth_phy.tx_len;
9473
      #1;
9474
      if (tmp_len != (i_length + 4 + 1))
9475
      begin
9476
        test_fail("Wrong length of second packet out from MAC");
9477
        fail = fail + 1;
9478
      end
9479
      // checking second packet
9480
      check_tx_packet(`MEMORY_BASE, 0, (i_length + 1), tmp);
9481
      if (tmp > 0)
9482
      begin
9483
        test_fail("Wrong data of second transmitted packet");
9484
        fail = fail + 1;
9485
      end
9486
      // check second transmited TX packet CRC
9487
      check_tx_crc(0, (i_length + 1), 1'b0, tmp); // length without CRC
9488
      if (tmp > 0)
9489
      begin
9490
        test_fail("Wrong CRC of second transmitted packet");
9491
        fail = fail + 1;
9492
      end
9493
      // check WB INT signal
9494
      if (wb_int !== 1'b1)
9495
      begin
9496
        `TIME; $display("*E WB INT signal should be set");
9497
        test_fail("WB INT signal should be set");
9498
        fail = fail + 1;
9499
      end
9500
      // check TX buffer descriptor of a packet
9501
      check_tx_bd(num_of_bd, data);
9502
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
9503
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
9504
      begin
9505
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9506
        test_fail("TX buffer descriptor status is not correct");
9507
        fail = fail + 1;
9508
      end
9509
      // check interrupts
9510
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9511
      if ((data & `ETH_INT_TXB) !== 1'b1)
9512
      begin
9513
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9514
        test_fail("Interrupt Transmit Buffer was not set");
9515
        fail = fail + 1;
9516
      end
9517
      if ((data & (~`ETH_INT_TXB)) !== 0)
9518
      begin
9519
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9520
        test_fail("Other interrupts (except Transmit Buffer) were set");
9521
        fail = fail + 1;
9522
      end
9523
      // clear interrupts
9524
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9525
      // check WB INT signal
9526
      if (wb_int !== 1'b0)
9527
      begin
9528
        test_fail("WB INT signal should not be set");
9529
        fail = fail + 1;
9530
      end
9531
      // set length (LOOP variable)
9532
      if ((tmp_ipgt + 3) < 130) // tmp_ipgt < 124
9533
        i_length = i_length + 2;
9534
      else
9535
        i_length = (max_tmp - 4);
9536
      // set IPGT
9537
      if ((tmp_ipgt + 3) < 10)
9538
        tmp_ipgt = tmp_ipgt + 1;
9539
      else if ((tmp_ipgt + 3) < 24)
9540
        tmp_ipgt = tmp_ipgt + 7;
9541
      else if ((tmp_ipgt + 3) == 24)
9542
        tmp_ipgt = 38 - 3;
9543
      else if ((tmp_ipgt + 3) == 38)
9544
        tmp_ipgt = 72 - 3;
9545
      else if ((tmp_ipgt + 3) == 72)
9546
        tmp_ipgt = 130 - 3; // 124 - 3
9547
      // the number of frame transmitted
9548
      num_of_frames = num_of_frames + 1;
9549
      num_of_bd = 0;
9550
      @(posedge wb_clk);
9551
    end
9552
    // disable TX
9553
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9554
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9555
    @(posedge wb_clk);
9556
    if(fail == 0)
9557
      test_ok;
9558
    else
9559
      fail = 0;
9560
  end
9561
 
9562
 
9563
  ////////////////////////////////////////////////////////////////////
9564
  ////                                                            ////
9565
  ////  Test IPG during Back-to-Back transmit at                  ////
9566
  ////  88 TX buffer decriptors ( 100Mbps ).                      ////
9567
  ////                                                            ////
9568
  ////////////////////////////////////////////////////////////////////
9569
  if (test_num == 19) // without and with padding
9570
  begin
9571
    // TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )
9572
    test_name = "TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )";
9573
    `TIME; $display("  TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )");
9574
 
9575
    // reset MAC registers
9576
    hard_reset;
9577
    // reset MAC and MII LOGIC with soft reset
9578
    reset_mac;
9579
    reset_mii;
9580
    // set wb slave response
9581
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9582
 
9583
    max_tmp = 0;
9584
    min_tmp = 0;
9585
    num_of_frames = 0;
9586
    num_of_bd = 0;
9587
    tmp_ipgt = 0;
9588
    // set 88 TX buffer descriptors - must be set before TX enable
9589
    wbm_write(`ETH_TX_BD_NUM, 32'h58, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9590
    // enable TX, set full-duplex mode, NO padding and CRC appending
9591
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9592
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9593
    // prepare two packets of MAXFL length
9594
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9595
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9596
    min_tmp = tmp[31:16];
9597
    st_data = 8'h29;
9598
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
9599
    // check WB INT signal
9600
    if (wb_int !== 1'b0)
9601
    begin
9602
      test_fail("WB INT signal should not be set");
9603
      fail = fail + 1;
9604
    end
9605
 
9606
    // write to phy's control register for 100Mbps
9607
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
9608
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
9609
    speed = 100;
9610
 
9611
    i_length = (min_tmp - 4);
9612
    while (i_length < (max_tmp - 4))
9613
    begin
9614
      // disable TX, set full-duplex mode, NO padding and CRC appending
9615
      wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9616
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9617
      // set IPGT register
9618
      wbm_write(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9619
      // enable TX, set full-duplex mode, NO padding and CRC appending
9620
      wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9621
                4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9622
      // Reset_tx_bd enable interrupt generation
9623
      // unmask interrupts
9624
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9625
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9626
      // not detect carrier sense in FD and no collision
9627
      eth_phy.carrier_sense_tx_fd_detect(0);
9628
      eth_phy.collision(0);
9629
      // first destination address on ethernet PHY
9630
      eth_phy.set_tx_mem_addr(0);
9631
      // prepare BDs
9632
      if (num_of_bd == 0)
9633
      begin
9634
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9635
        set_tx_bd(1, 1, i_length+1, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9636
        set_tx_bd_wrap(1);
9637
        set_tx_bd_ready(0, 0);
9638
        set_tx_bd_ready(1, 1);
9639
      end
9640
      // CHECK END OF TWO TRANSMITIONs
9641
      // wait for first transmit to end
9642
      check_tx_bd(num_of_bd, data);
9643
      wait (MTxEn === 1'b1); // start transmit
9644
      if (data[15] !== 1)
9645
      begin
9646
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9647
        fail = fail + 1;
9648
      end
9649
      wait (MTxEn === 1'b0); // end transmit
9650
      num_of_frames = num_of_frames + 1;
9651
      num_of_bd = num_of_bd + 1;
9652
      #Tp;
9653
      // destination address on ethernet PHY
9654
      eth_phy.set_tx_mem_addr(0);
9655
      i1 = 0;
9656
      i2 = 0;
9657
      // count IPG clock periods
9658
      fork
9659
        begin
9660
          wait (MTxEn === 1'b1); // start second transmit
9661
          #Tp;
9662
          disable count_rising1;
9663
          disable count_falling1;
9664
        end
9665
        begin: count_rising1
9666
          forever
9667
          begin
9668
            @(posedge mtx_clk);
9669
            i1 = i1 + 1;
9670
            #Tp;
9671
          end
9672
        end
9673
        begin: count_falling1
9674
          forever
9675
          begin
9676
            @(negedge mtx_clk);
9677
            i2 = i2 + 1;
9678
            #Tp;
9679
          end
9680
        end
9681
      join
9682
      // check IPG length - INTERMEDIATE DISPLAYS
9683
      if((i1 == i2) && (i1 >= (tmp_ipgt + 3)))
9684
      begin
9685
        $display("    ->IPG with %0d mtx_clk periods (min %0d) between packets with lengths %0d and %0d checked",
9686
                  i1, (tmp_ipgt + 3), (i_length + 4), (i_length + 4 + 1));
9687
      end
9688
      else
9689
      begin
9690
        `TIME; $display("*E IPG is not correct: (%0d + %0d) / 2, requested: %d", i1, i2, (tmp_ipgt + 3));
9691
        fail = fail + 1;
9692
        test_fail("IPG is not correct");
9693
      end
9694
      // wait for second transmit to end
9695
      wait (MTxEn === 1'b0); // end second transmit
9696
      while (data[15] === 1)
9697
      begin
9698
        check_tx_bd(num_of_bd, data);
9699
        @(posedge wb_clk);
9700
      end
9701
      repeat (1) @(posedge wb_clk);
9702
      // check length of a second PACKET
9703
      tmp_len = eth_phy.tx_len;
9704
      #1;
9705
      if (tmp_len != (i_length + 4 + 1))
9706
      begin
9707
        test_fail("Wrong length of second packet out from MAC");
9708
        fail = fail + 1;
9709
      end
9710
      // checking second packet
9711
      check_tx_packet(`MEMORY_BASE, 0, (i_length + 1), tmp);
9712
      if (tmp > 0)
9713
      begin
9714
        test_fail("Wrong data of second transmitted packet");
9715
        fail = fail + 1;
9716
      end
9717
      // check second transmited TX packet CRC
9718
      check_tx_crc(0, (i_length + 1), 1'b0, tmp); // length without CRC
9719
      if (tmp > 0)
9720
      begin
9721
        test_fail("Wrong CRC of second transmitted packet");
9722
        fail = fail + 1;
9723
      end
9724
      // check WB INT signal
9725
      if (wb_int !== 1'b1)
9726
      begin
9727
        `TIME; $display("*E WB INT signal should be set");
9728
        test_fail("WB INT signal should be set");
9729
        fail = fail + 1;
9730
      end
9731
      // check TX buffer descriptor of a packet
9732
      check_tx_bd(num_of_bd, data);
9733
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
9734
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
9735
      begin
9736
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9737
        test_fail("TX buffer descriptor status is not correct");
9738
        fail = fail + 1;
9739
      end
9740
      // check interrupts
9741
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9742
      if ((data & `ETH_INT_TXB) !== 1'b1)
9743
      begin
9744
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9745
        test_fail("Interrupt Transmit Buffer was not set");
9746
        fail = fail + 1;
9747
      end
9748
      if ((data & (~`ETH_INT_TXB)) !== 0)
9749
      begin
9750
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9751
        test_fail("Other interrupts (except Transmit Buffer) were set");
9752
        fail = fail + 1;
9753
      end
9754
      // clear interrupts
9755
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9756
      // check WB INT signal
9757
      if (wb_int !== 1'b0)
9758
      begin
9759
        test_fail("WB INT signal should not be set");
9760
        fail = fail + 1;
9761
      end
9762
      // set length (LOOP variable)
9763
      if ((tmp_ipgt + 3) < 130) // tmp_ipgt < 124
9764
        i_length = i_length + 2;
9765
      else
9766
        i_length = (max_tmp - 4);
9767
      // set IPGT
9768
      if ((tmp_ipgt + 3) < 10)
9769
        tmp_ipgt = tmp_ipgt + 1;
9770
      else if ((tmp_ipgt + 3) < 24)
9771
        tmp_ipgt = tmp_ipgt + 7;
9772
      else if ((tmp_ipgt + 3) == 24)
9773
        tmp_ipgt = 38 - 3;
9774
      else if ((tmp_ipgt + 3) == 38)
9775
        tmp_ipgt = 72 - 3;
9776
      else if ((tmp_ipgt + 3) == 72)
9777
        tmp_ipgt = 130 - 3; // 124 - 3
9778
      // the number of frame transmitted
9779
      num_of_frames = num_of_frames + 1;
9780
      num_of_bd = 0;
9781
      @(posedge wb_clk);
9782
    end
9783
    // disable TX
9784
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
9785
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9786
    @(posedge wb_clk);
9787
    if(fail == 0)
9788
      test_ok;
9789
    else
9790
      fail = 0;
9791
  end
9792
 
9793
 
9794
  ////////////////////////////////////////////////////////////////////
9795
  ////                                                            ////
9796
  ////  Test transmit packets after TX under-run on each packet's ////
9797
  ////  byte at 2 TX buffer decriptors ( 10Mbps ).                ////
9798
  ////                                                            ////
9799
  ////////////////////////////////////////////////////////////////////
9800
  if (test_num == 20) // without padding
9801
  begin
9802
    // TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )
9803
    test_name = "TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )";
9804
    `TIME;
9805
    $display("  TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )");
9806
 
9807
    // reset MAC registers
9808
    hard_reset;
9809
    // reset MAC and MII LOGIC with soft reset
9810
    reset_mac;
9811
    reset_mii;
9812
    // set wb slave response
9813
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
9814
 
9815
    max_tmp = 0;
9816
    min_tmp = 0;
9817
    // set 2 TX buffer descriptors - must be set before TX enable
9818
    wbm_write(`ETH_TX_BD_NUM, 32'h2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9819
    // enable TX, set full-duplex mode, NO padding and CRC appending
9820
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN |/* `ETH_MODER_PAD |*/ `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
9821
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9822
    // prepare a packet of MAXFL length
9823
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9824
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
9825
    min_tmp = tmp[31:16];
9826
    st_data = 8'h99;
9827
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
9828
    // read IPG value
9829
    wbm_read(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9830
    // check WB INT signal
9831
    if (wb_int !== 1'b0)
9832
    begin
9833
      test_fail("WB INT signal should not be set");
9834
      fail = fail + 1;
9835
    end
9836
 
9837
    // write to phy's control register for 10Mbps
9838
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
9839
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
9840
    speed = 10;
9841
 
9842 223 tadejm
    num_of_frames = 40; // (0..3) => start under-run on first word
9843 209 tadejm
    num_of_bd = 0;
9844
    i_data = 3; // (3) => one BYTE read in first word - FIRST byte
9845
    i_length = (min_tmp + 4);
9846
    while (i_length < (max_tmp - 4))
9847
    begin
9848
      // Reset_tx_bd enable interrupt generation
9849
      // unmask interrupts
9850
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
9851
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9852
      // not detect carrier sense in FD and no collision
9853
      eth_phy.carrier_sense_tx_fd_detect(0);
9854
      eth_phy.collision(0);
9855
      // first destination address on ethernet PHY
9856
      eth_phy.set_tx_mem_addr(0);
9857
      // prepare BDs
9858
      if (num_of_bd == 0)
9859
      begin
9860
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
9861
        set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
9862
        set_tx_bd_wrap(1);
9863
        // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
9864
        //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
9865 223 tadejm
        #1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
9866 209 tadejm
        set_tx_bd_ready(1, 1);
9867
        set_tx_bd_ready(0, 0);
9868
      end
9869
      // frame under-run checking
9870
      frame_started = 0;
9871
      frame_ended = 0;
9872
      wait_for_frame = 0;
9873
      fork
9874
        begin
9875
          // for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
9876
          // in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
9877
          repeat ((num_of_frames[31:2] + 1'b1)) @(posedge eth_ma_wb_ack_i);
9878
          @(negedge eth_ma_wb_ack_i); // wait for last ACK to finish
9879
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
9880
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
9881 223 tadejm
          #1 wb_slave.cycle_response(`NO_RESPONSE, 3'h0, 8'hFF);
9882 209 tadejm
          // wait for synchronization and some additional clocks
9883
          wait_for_frame = 1;
9884
          // wait for frame
9885
          wait ((wait_for_frame == 0) || (frame_started == 1))
9886
          if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
9887
          begin
9888
            disable check_fr;
9889
          end
9890
          else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
9891
          begin
9892
            disable wait_fr;
9893
            wait (frame_ended == 1);
9894
          end
9895
          repeat (2) @(posedge wb_clk);
9896
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
9897
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
9898 223 tadejm
          wb_slave.cycle_response(`ACK_RESPONSE, 3'h0, 8'h0);
9899 209 tadejm
        end
9900
        begin: wait_fr
9901
          wait (wait_for_frame == 1)
9902
          begin
9903
            // wait for synchronization and some additional clocks
9904
            repeat (3) @(posedge wb_clk);
9905
            repeat (2 * tmp_ipgt) @(posedge mtx_clk);
9906
            repeat (2) @(posedge wb_clk);
9907
            repeat (2) @(posedge mtx_clk);
9908
            wait_for_frame = 0;
9909
          end
9910
        end
9911
        begin: check_fr
9912
          // wait for frame to start
9913
          @(posedge MTxEn);
9914
          frame_started = 1;
9915 223 tadejm
`TIME; $display("  Under-run (on %0d. byte) frame started", (num_of_frames + 1));
9916 209 tadejm
          // wait for frame to end due to under-run
9917
          @(negedge MTxEn);
9918
          frame_ended = 1;
9919 223 tadejm
`TIME; $display("  Under-run frame ended");
9920 209 tadejm
        end
9921
      join
9922
      // wait for first transmit to end, if under-run didn't happen
9923
      if (frame_ended == 0)
9924
      begin
9925
        // WAIT FOR FIRST TRANSMIT
9926
        check_tx_bd(num_of_bd, data);
9927
        wait (MTxEn === 1'b1); // start first transmit
9928
        if (data[15] !== 1)
9929
        begin
9930
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
9931
          fail = fail + 1;
9932
        end
9933
        wait (MTxEn === 1'b0); // end first transmit
9934
        while (data[15] === 1)
9935
        begin
9936
          check_tx_bd(num_of_bd, data);
9937
          @(posedge wb_clk);
9938
        end
9939
        repeat (1) @(posedge wb_clk);
9940
        // CHECK FIRST FRAME
9941
        // check length of a first PACKET
9942
        tmp_len = eth_phy.tx_len;
9943
        #1;
9944
        if (tmp_len != (i_length + 4))
9945
        begin
9946 223 tadejm
          `TIME; $display("*E Wrong length of first packet out from MAC");
9947
          test_fail("Wrong length of first packet out from MAC");
9948 209 tadejm
          fail = fail + 1;
9949
        end
9950
        // checking first packet
9951
        check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
9952
        if (tmp > 0)
9953
        begin
9954 223 tadejm
          `TIME; $display("*E Wrong data of first transmitted packet");
9955
          test_fail("Wrong data of first transmitted packet");
9956 209 tadejm
          fail = fail + 1;
9957
        end
9958
        // check first transmited TX packet CRC
9959
        check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
9960
        if (tmp > 0)
9961
        begin
9962 223 tadejm
          `TIME; $display("*E Wrong CRC of first transmitted packet");
9963
          test_fail("Wrong CRC of first transmitted packet");
9964 209 tadejm
          fail = fail + 1;
9965
        end
9966
        // check WB INT signal
9967
        if (wb_int !== 1'b1)
9968
        begin
9969
          `TIME; $display("*E WB INT signal should be set");
9970
          test_fail("WB INT signal should be set");
9971
          fail = fail + 1;
9972
        end
9973
        // check TX buffer descriptor of a packet
9974
        check_tx_bd(num_of_bd, data);
9975
        if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
9976
             ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
9977
        begin
9978
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
9979
          test_fail("TX buffer descriptor status is not correct");
9980
          fail = fail + 1;
9981
        end
9982
        // check interrupts
9983
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9984
        if ((data & `ETH_INT_TXB) !== 1'b1)
9985
        begin
9986
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
9987
          test_fail("Interrupt Transmit Buffer was not set");
9988
          fail = fail + 1;
9989
        end
9990
        if ((data & (~`ETH_INT_TXB)) !== 0)
9991
        begin
9992
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
9993
          test_fail("Other interrupts (except Transmit Buffer) were set");
9994
          fail = fail + 1;
9995
        end
9996
        // clear interrupts
9997
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
9998
        // check WB INT signal
9999
        if (wb_int !== 1'b0)
10000
        begin
10001
          test_fail("WB INT signal should not be set");
10002
          fail = fail + 1;
10003
        end
10004
      end
10005 223 tadejm
      else
10006
      begin
10007
        // CHECK FIRST FRAME
10008
        // check length of a first PACKET
10009
        tmp_len = eth_phy.tx_len_err;
10010
        #1;
10011
        if (tmp_len != (num_of_frames + (4 - i_data)))
10012
        begin
10013
          `TIME; $display("*E Wrong length of first packet out from MAC");
10014
          test_fail("Wrong length of first packet out from MAC");
10015
          fail = fail + 1;
10016
        end
10017
        // checking first packet
10018
        check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (num_of_frames), tmp);
10019
        if (tmp > 0)
10020
        begin
10021
          `TIME; $display("*E Wrong data of first transmitted packet");
10022
          test_fail("Wrong data of first transmitted packet");
10023
          fail = fail + 1;
10024
        end
10025
        // check WB INT signal
10026
        if (wb_int !== 1'b1)
10027
        begin
10028
          `TIME; $display("*E WB INT signal should be set");
10029
          test_fail("WB INT signal should be set");
10030
          fail = fail + 1;
10031
        end
10032
        // check TX buffer descriptor of a packet
10033
        check_tx_bd(num_of_bd, data);
10034
        if ( ((data[15:0] !== 16'h7900) && (num_of_bd == 1)) || // under-run, wrap bit
10035
             ((data[15:0] !== 16'h5900) && (num_of_bd < 1)) )   // under-run, without wrap bit
10036
        begin
10037
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10038
          test_fail("TX buffer descriptor status is not correct");
10039
          fail = fail + 1;
10040
        end
10041
        // check interrupts
10042
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10043
        if ((data & `ETH_INT_TXE) !== 2'b10)
10044
        begin
10045
          `TIME; $display("*E Interrupt Transmit Error was not set, interrupt reg: %0h", data);
10046
          test_fail("Interrupt Transmit Buffer was not set");
10047
          fail = fail + 1;
10048
        end
10049
        if ((data & (~`ETH_INT_TXE)) !== 0)
10050
        begin
10051
          `TIME; $display("*E Other interrupts (except Transmit Error) were set, interrupt reg: %0h", data);
10052
          test_fail("Other interrupts (except Transmit Buffer) were set");
10053
          fail = fail + 1;
10054
        end
10055
        // clear interrupts
10056
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10057
        // check WB INT signal
10058
        if (wb_int !== 1'b0)
10059
        begin
10060
          test_fail("WB INT signal should not be set");
10061
          fail = fail + 1;
10062
        end
10063
      end
10064 209 tadejm
      num_of_bd = num_of_bd + 1;
10065
      // destination address on ethernet PHY
10066
      eth_phy.set_tx_mem_addr(0);
10067 223 tadejm
      // WAIT FOR SECOND TRANSMIT
10068 209 tadejm
      check_tx_bd(num_of_bd, data);
10069
      wait (MTxEn === 1'b1); // start first transmit
10070
      if (data[15] !== 1)
10071
      begin
10072
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10073
        fail = fail + 1;
10074
      end
10075
      wait (MTxEn === 1'b0); // end first transmit
10076
      while (data[15] === 1)
10077
      begin
10078
        check_tx_bd(num_of_bd, data);
10079
        @(posedge wb_clk);
10080
      end
10081
      repeat (1) @(posedge wb_clk);
10082
      // CHECK SECOND FRAME
10083
      // check length of a second PACKET
10084 223 tadejm
if (frame_ended == 1'b1)
10085
begin
10086
`TIME; $display("  Second frame after under-run ended");
10087
end
10088 209 tadejm
      tmp_len = eth_phy.tx_len;
10089
      #1;
10090
      if (tmp_len != (i_length + 4))
10091
      begin
10092 223 tadejm
        `TIME; $display("*E Wrong length of second packet out from MAC");
10093 209 tadejm
        test_fail("Wrong length of second packet out from MAC");
10094
        fail = fail + 1;
10095
      end
10096
      // checking second packet
10097
      check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
10098
      if (tmp > 0)
10099
      begin
10100 223 tadejm
        `TIME; $display("*E Wrong data of second transmitted packet");
10101 209 tadejm
        test_fail("Wrong data of second transmitted packet");
10102
        fail = fail + 1;
10103
      end
10104
      // check second transmited TX packet CRC
10105
      check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10106
      if (tmp > 0)
10107
      begin
10108 223 tadejm
        `TIME; $display("*E Wrong CRC of second transmitted packet");
10109 209 tadejm
        test_fail("Wrong CRC of second transmitted packet");
10110
        fail = fail + 1;
10111
      end
10112
      // check WB INT signal
10113
      if (wb_int !== 1'b1)
10114
      begin
10115
        `TIME; $display("*E WB INT signal should be set");
10116
        test_fail("WB INT signal should be set");
10117
        fail = fail + 1;
10118
      end
10119
      // check TX buffer descriptor of a packet
10120
      check_tx_bd(num_of_bd, data);
10121
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10122
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10123
      begin
10124
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10125
        test_fail("TX buffer descriptor status is not correct");
10126
        fail = fail + 1;
10127
      end
10128
      // check interrupts
10129
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10130
      if ((data & `ETH_INT_TXB) !== 1'b1)
10131
      begin
10132
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10133
        test_fail("Interrupt Transmit Buffer was not set");
10134
        fail = fail + 1;
10135
      end
10136
      if ((data & (~`ETH_INT_TXB)) !== 0)
10137
      begin
10138
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10139
        test_fail("Other interrupts (except Transmit Buffer) were set");
10140
        fail = fail + 1;
10141
      end
10142
      // clear interrupts
10143
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10144
      // check WB INT signal
10145
      if (wb_int !== 1'b0)
10146
      begin
10147
        test_fail("WB INT signal should not be set");
10148
        fail = fail + 1;
10149
      end
10150
      // set initial value
10151
      i_data = i_data - 1;
10152
      // the number of frame transmitted
10153
      num_of_frames = num_of_frames + 1;
10154
      num_of_bd = 0;
10155
      // set length (LOOP variable)
10156 223 tadejm
      if (num_of_frames == i_length + 4) // 64 => this was last Byte (1st .. 64th) when i_length = min_tmp - 4
10157 209 tadejm
        i_length = (max_tmp - 4);
10158
      @(posedge wb_clk);
10159
    end
10160
    // disable TX
10161
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
10162
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10163
    @(posedge wb_clk);
10164
    if(fail == 0)
10165
      test_ok;
10166
    else
10167
      fail = 0;
10168
  end
10169
 
10170
 
10171
  ////////////////////////////////////////////////////////////////////
10172
  ////                                                            ////
10173
  ////  Test transmit packets after TX under-run on each packet's ////
10174
  ////  byte at 2 TX buffer decriptors ( 100Mbps ).               ////
10175
  ////                                                            ////
10176
  ////////////////////////////////////////////////////////////////////
10177
  if (test_num == 21) // without padding
10178
  begin
10179
    // TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )
10180
    test_name = "TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )";
10181
    `TIME;
10182
    $display("  TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )");
10183
 
10184
    // reset MAC registers
10185
    hard_reset;
10186
    // reset MAC and MII LOGIC with soft reset
10187
    reset_mac;
10188
    reset_mii;
10189
    // set wb slave response
10190
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
10191
 
10192
    max_tmp = 0;
10193
    min_tmp = 0;
10194
    // set 2 TX buffer descriptors - must be set before TX enable
10195
    wbm_write(`ETH_TX_BD_NUM, 32'h2, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10196
    // enable TX, set full-duplex mode, NO padding and CRC appending
10197
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN |/* `ETH_MODER_PAD |*/ `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
10198
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10199
    // prepare a packet of MAXFL length
10200
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10201
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
10202
    min_tmp = tmp[31:16];
10203
    st_data = 8'h99;
10204
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC
10205
    // read IPG value
10206
    wbm_read(`ETH_IPGT, tmp_ipgt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10207
    // check WB INT signal
10208
    if (wb_int !== 1'b0)
10209
    begin
10210
      test_fail("WB INT signal should not be set");
10211
      fail = fail + 1;
10212
    end
10213
 
10214
    // write to phy's control register for 100Mbps
10215
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
10216
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
10217
    speed = 100;
10218
 
10219
    num_of_frames = 0; // (0..3) => start under-run on first word
10220
    num_of_bd = 0;
10221
    i_data = 3; // (3) => one BYTE read in first word - FIRST byte
10222
    i_length = (min_tmp + 4);
10223
    while (i_length < (max_tmp - 4))
10224
    begin
10225
      // Reset_tx_bd enable interrupt generation
10226
      // unmask interrupts
10227
      wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
10228
                               `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10229
      // not detect carrier sense in FD and no collision
10230
      eth_phy.carrier_sense_tx_fd_detect(0);
10231
      eth_phy.collision(0);
10232
      // first destination address on ethernet PHY
10233
      eth_phy.set_tx_mem_addr(0);
10234
      // prepare BDs
10235
      if (num_of_bd == 0)
10236
      begin
10237
        set_tx_bd(0, 0, i_length, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE + i_data[1:0]));
10238
        set_tx_bd(1, 1, i_length, 1'b1, 1'b1, 1'b1, `MEMORY_BASE);
10239
        set_tx_bd_wrap(1);
10240
        // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10241
        //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10242
        #1 wb_slave.cycle_response(`ACK_RESPONSE, 3'h2, 8'h0);
10243
        set_tx_bd_ready(1, 1);
10244
        set_tx_bd_ready(0, 0);
10245
      end
10246
      // frame under-run checking
10247
      frame_started = 0;
10248
      frame_ended = 0;
10249
      wait_for_frame = 0;
10250
      fork
10251
        begin
10252
          // for every 4 frames bytes 1, 2, 3 and 4 respectively are read in first word => 1 ACK
10253
          // in other words 4 bytes are read, since length is MINFL => num_of_frames[31:2] ACKs
10254
          repeat ((num_of_frames[31:2] + 1'b1)) @(posedge eth_ma_wb_ack_i);
10255
          @(negedge eth_ma_wb_ack_i); // wait for last ACK to finish
10256
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10257
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10258
          #1 wb_slave.cycle_response(`NO_RESPONSE, 3'h7, 8'hFF);
10259
          // wait for synchronization and some additional clocks
10260
          wait_for_frame = 1;
10261
          // wait for frame
10262
          wait ((wait_for_frame == 0) || (frame_started == 1))
10263
          if ((wait_for_frame == 0) && (frame_started == 0)) // frame didn't start
10264
          begin
10265
            disable check_fr1;
10266
          end
10267
          else if ((wait_for_frame == 1) && (frame_started == 1)) // frame started
10268
          begin
10269
            disable wait_fr1;
10270
            wait (frame_ended == 1);
10271
          end
10272
          repeat (2) @(posedge wb_clk);
10273
          // set wb slave response: ACK (response), wbs_waits[2:0] (waits before response), 
10274
          //                       wbs_retries[7:0] (RTYs before ACK if RTY response selected)
10275
          wb_slave.cycle_response(`ACK_RESPONSE, 3'h2, 8'h0);
10276
        end
10277
        begin: wait_fr1
10278
          wait (wait_for_frame == 1)
10279
          begin
10280
            // wait for synchronization and some additional clocks
10281
            repeat (3) @(posedge wb_clk);
10282
            repeat (2 * tmp_ipgt) @(posedge mtx_clk);
10283
            repeat (2) @(posedge wb_clk);
10284
            repeat (2) @(posedge mtx_clk);
10285
            wait_for_frame = 0;
10286
          end
10287
        end
10288
        begin: check_fr1
10289
          // wait for frame to start
10290
          @(posedge MTxEn);
10291
          frame_started = 1;
10292
$display("  Under-run (on %0d. byte) frame started", (num_of_frames + 1));
10293
          // wait for frame to end due to under-run
10294
          @(negedge MTxEn);
10295
          frame_ended = 1;
10296
$display("  Under-run frame ended");
10297
        end
10298
      join
10299
      // wait for first transmit to end, if under-run didn't happen
10300
      if (frame_ended == 0)
10301
      begin
10302
        // WAIT FOR FIRST TRANSMIT
10303
        check_tx_bd(num_of_bd, data);
10304
        wait (MTxEn === 1'b1); // start first transmit
10305
        if (data[15] !== 1)
10306
        begin
10307
          test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10308
          fail = fail + 1;
10309
        end
10310
        wait (MTxEn === 1'b0); // end first transmit
10311
        while (data[15] === 1)
10312
        begin
10313
          check_tx_bd(num_of_bd, data);
10314
          @(posedge wb_clk);
10315
        end
10316
        repeat (1) @(posedge wb_clk);
10317
        // CHECK FIRST FRAME
10318
        // check length of a first PACKET
10319
        tmp_len = eth_phy.tx_len;
10320
        #1;
10321
        if (tmp_len != (i_length + 4))
10322
        begin
10323
          test_fail("Wrong length of second packet out from MAC");
10324
          fail = fail + 1;
10325
        end
10326
        // checking first packet
10327
        check_tx_packet((`MEMORY_BASE + i_data[1:0]), 0, (i_length), tmp);
10328
        if (tmp > 0)
10329
        begin
10330
          test_fail("Wrong data of second transmitted packet");
10331
          fail = fail + 1;
10332
        end
10333
        // check first transmited TX packet CRC
10334
        check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10335
        if (tmp > 0)
10336
        begin
10337
          test_fail("Wrong CRC of second transmitted packet");
10338
          fail = fail + 1;
10339
        end
10340
        // check WB INT signal
10341
        if (wb_int !== 1'b1)
10342
        begin
10343
          `TIME; $display("*E WB INT signal should be set");
10344
          test_fail("WB INT signal should be set");
10345
          fail = fail + 1;
10346
        end
10347
        // check TX buffer descriptor of a packet
10348
        check_tx_bd(num_of_bd, data);
10349
        if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10350
             ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10351
        begin
10352
          `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10353
          test_fail("TX buffer descriptor status is not correct");
10354
          fail = fail + 1;
10355
        end
10356
        // check interrupts
10357
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10358
        if ((data & `ETH_INT_TXB) !== 1'b1)
10359
        begin
10360
          `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10361
          test_fail("Interrupt Transmit Buffer was not set");
10362
          fail = fail + 1;
10363
        end
10364
        if ((data & (~`ETH_INT_TXB)) !== 0)
10365
        begin
10366
          `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10367
          test_fail("Other interrupts (except Transmit Buffer) were set");
10368
          fail = fail + 1;
10369
        end
10370
        // clear interrupts
10371
        wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10372
        // check WB INT signal
10373
        if (wb_int !== 1'b0)
10374
        begin
10375
          test_fail("WB INT signal should not be set");
10376
          fail = fail + 1;
10377
        end
10378
      end
10379
      num_of_bd = num_of_bd + 1;
10380
      // destination address on ethernet PHY
10381
      eth_phy.set_tx_mem_addr(0);
10382
      // WAIT FOR FIRST TRANSMIT
10383
      check_tx_bd(num_of_bd, data);
10384
      wait (MTxEn === 1'b1); // start first transmit
10385
      if (data[15] !== 1)
10386
      begin
10387
        test_fail("Wrong buffer descriptor's ready bit read out from MAC");
10388
        fail = fail + 1;
10389
      end
10390
      wait (MTxEn === 1'b0); // end first transmit
10391
      while (data[15] === 1)
10392
      begin
10393
        check_tx_bd(num_of_bd, data);
10394
        @(posedge wb_clk);
10395
      end
10396
      repeat (1) @(posedge wb_clk);
10397
      // CHECK SECOND FRAME
10398
      // check length of a second PACKET
10399
      tmp_len = eth_phy.tx_len;
10400
      #1;
10401
      if (tmp_len != (i_length + 4))
10402
      begin
10403
        test_fail("Wrong length of second packet out from MAC");
10404
        fail = fail + 1;
10405
      end
10406
      // checking second packet
10407
      check_tx_packet(`MEMORY_BASE, 0, (i_length), tmp);
10408
      if (tmp > 0)
10409
      begin
10410
        test_fail("Wrong data of second transmitted packet");
10411
        fail = fail + 1;
10412
      end
10413
      // check second transmited TX packet CRC
10414
      check_tx_crc(0, (i_length), 1'b0, tmp); // length without CRC
10415
      if (tmp > 0)
10416
      begin
10417
        test_fail("Wrong CRC of second transmitted packet");
10418
        fail = fail + 1;
10419
      end
10420
      // check WB INT signal
10421
      if (wb_int !== 1'b1)
10422
      begin
10423
        `TIME; $display("*E WB INT signal should be set");
10424
        test_fail("WB INT signal should be set");
10425
        fail = fail + 1;
10426
      end
10427
      // check TX buffer descriptor of a packet
10428
      check_tx_bd(num_of_bd, data);
10429
      if ( ((data[15:0] !== 16'h7800) && (num_of_bd == 1)) || // wrap bit
10430
           ((data[15:0] !== 16'h5800) && (num_of_bd < 1)) )   // without wrap bit
10431
      begin
10432
        `TIME; $display("*E TX buffer descriptor status is not correct: %0h", data[15:0]);
10433
        test_fail("TX buffer descriptor status is not correct");
10434
        fail = fail + 1;
10435
      end
10436
      // check interrupts
10437
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10438
      if ((data & `ETH_INT_TXB) !== 1'b1)
10439
      begin
10440
        `TIME; $display("*E Interrupt Transmit Buffer was not set, interrupt reg: %0h", data);
10441
        test_fail("Interrupt Transmit Buffer was not set");
10442
        fail = fail + 1;
10443
      end
10444
      if ((data & (~`ETH_INT_TXB)) !== 0)
10445
      begin
10446
        `TIME; $display("*E Other interrupts (except Transmit Buffer) were set, interrupt reg: %0h", data);
10447
        test_fail("Other interrupts (except Transmit Buffer) were set");
10448
        fail = fail + 1;
10449
      end
10450
      // clear interrupts
10451
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10452
      // check WB INT signal
10453
      if (wb_int !== 1'b0)
10454
      begin
10455
        test_fail("WB INT signal should not be set");
10456
        fail = fail + 1;
10457
      end
10458
      // set initial value
10459
      i_data = i_data - 1;
10460
      // the number of frame transmitted
10461
      num_of_frames = num_of_frames + 1;
10462
      num_of_bd = 0;
10463
      // set length (LOOP variable)
10464
      if (num_of_frames == i_length + 4) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
10465
        i_length = (max_tmp - 4);
10466
      @(posedge wb_clk);
10467
    end
10468
    // disable TX
10469
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
10470
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10471
    @(posedge wb_clk);
10472
    if(fail == 0)
10473
      test_ok;
10474
    else
10475
      fail = 0;
10476
  end
10477
 
10478 194 tadej
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
10479 169 mohor
 
10480
end
10481
endtask // test_mac_full_duplex_transmit
10482
 
10483
 
10484 209 tadejm
task test_mac_full_duplex_receive;
10485
  input  [31:0]  start_task;
10486
  input  [31:0]  end_task;
10487
  integer        bit_start_1;
10488
  integer        bit_end_1;
10489
  integer        bit_start_2;
10490
  integer        bit_end_2;
10491
  integer        num_of_reg;
10492
  integer        num_of_frames;
10493
  integer        num_of_bd;
10494
  integer        i_addr;
10495
  integer        i_data;
10496
  integer        i_length;
10497
  integer        tmp_len;
10498
  integer        tmp_bd;
10499
  integer        tmp_bd_num;
10500
  integer        tmp_data;
10501
  integer        tmp_ipgt;
10502
  integer        test_num;
10503
  reg    [31:0]  tx_bd_num;
10504
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
10505
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
10506
  integer        i;
10507
  integer        i1;
10508
  integer        i2;
10509
  integer        i3;
10510
  integer        fail;
10511
  integer        speed;
10512
  reg            frame_started;
10513
  reg            frame_ended;
10514
  reg            wait_for_frame;
10515 243 tadejm
  reg            check_frame;
10516
  reg            stop_checking_frame;
10517
  reg            first_fr_received;
10518 209 tadejm
  reg    [31:0]  addr;
10519
  reg    [31:0]  data;
10520
  reg    [31:0]  tmp;
10521
  reg    [ 7:0]  st_data;
10522
  reg    [15:0]  max_tmp;
10523
  reg    [15:0]  min_tmp;
10524
begin
10525
// MAC FULL DUPLEX RECEIVE TEST
10526
test_heading("MAC FULL DUPLEX RECEIVE TEST");
10527
$display(" ");
10528
$display("MAC FULL DUPLEX RECEIVE TEST");
10529
fail = 0;
10530
 
10531
// reset MAC registers
10532
hard_reset;
10533
// reset MAC and MII LOGIC with soft reset
10534
reset_mac;
10535
reset_mii;
10536
// set wb slave response
10537
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
10538
 
10539
  /*
10540
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
10541
  -------------------------------------------------------------------------------------
10542
  set_tx_bd
10543
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
10544
  set_tx_bd_wrap
10545
    (tx_bd_num_end[6:0]);
10546
  set_tx_bd_ready
10547
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
10548
  check_tx_bd
10549
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
10550
  clear_tx_bd
10551
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
10552
 
10553
  TASKS for set and control RX buffer descriptors:
10554
  ------------------------------------------------
10555
  set_rx_bd
10556
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
10557
  set_rx_bd_wrap
10558
    (rx_bd_num_end[6:0]);
10559
  set_rx_bd_empty
10560
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
10561
  check_rx_bd
10562
    (rx_bd_num_end[6:0], rx_bd_status);
10563
  clear_rx_bd
10564
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
10565
 
10566
  TASKS for set and check TX packets:
10567
  -----------------------------------
10568
  set_tx_packet
10569
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
10570
  check_tx_packet
10571
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
10572
 
10573
  TASKS for set and check RX packets:
10574
  -----------------------------------
10575
  set_rx_packet
10576
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
10577
  check_rx_packet
10578
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
10579
 
10580
  TASKS for append and check CRC to/of TX packet:
10581
  -----------------------------------------------
10582
  append_tx_crc
10583
    (txpnt_wb[31:0], len[15:0], negated_crc);
10584
  check_tx_crc
10585
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
10586
 
10587
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
10588
  --------------------------------------------------------------------------------
10589
  append_rx_crc
10590
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
10591
  */
10592
 
10593
//////////////////////////////////////////////////////////////////////
10594
////                                                              ////
10595
////  test_mac_full_duplex_receive:                               ////
10596
////                                                              ////
10597
////  0: Test no receive when all buffers are TX ( 10Mbps ).      ////
10598
////  1: Test no receive when all buffers are TX ( 100Mbps ).     ////
10599 243 tadejm
////  2: Test receive packet synchronization with receive         ////
10600
////     disable/enable ( 10Mbps ).                               ////
10601
////  3: Test receive packet synchronization with receive         ////
10602
////     disable/enable ( 100Mbps ).                              ////
10603
////  4: Test receive packets form MINFL to MAXFL sizes at        ////
10604 209 tadejm
////     one RX buffer decriptor ( 10Mbps ).                      ////
10605 243 tadejm
////  5: Test receive packets form MINFL to MAXFL sizes at        ////
10606 209 tadejm
////     one RX buffer decriptor ( 100Mbps ).                     ////
10607
////                                                              ////
10608
//////////////////////////////////////////////////////////////////////
10609
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
10610
begin
10611
 
10612
  ////////////////////////////////////////////////////////////////////
10613
  ////                                                            ////
10614
  ////  Test no receive when all buffers are TX ( 10Mbps ).       ////
10615
  ////                                                            ////
10616
  ////////////////////////////////////////////////////////////////////
10617
  if (test_num == 0) // Test no receive when all buffers are TX ( 10Mbps ).
10618
  begin
10619
    // TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
10620
    test_name   = "TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )";
10621
    `TIME; $display("  TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )");
10622
 
10623
    // unmask interrupts
10624
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
10625
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10626
    // set all buffer descriptors to TX - must be set before RX enable
10627
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10628 223 tadejm
    // enable RX, set full-duplex mode, receive small, NO correct IFG
10629 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
10630
              `ETH_MODER_PRO | `ETH_MODER_BRO,
10631
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10632
 
10633
    // write to phy's control register for 10Mbps
10634
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
10635
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
10636
    speed = 10;
10637
 
10638
    i = 0;
10639
    while (i < 128)
10640
    begin
10641
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
10642
      begin
10643
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
10644
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
10645
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
10646
      end
10647
      set_rx_bd_wrap(i);
10648
      set_rx_bd_empty(0, i);
10649
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
10650
      begin
10651
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
10652
        repeat(10) @(posedge mrx_clk);
10653
      end
10654
      @(posedge mrx_clk);
10655
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
10656
      begin
10657
        check_rx_bd(0, tmp);
10658
        #1;
10659
        if (tmp[15] === 1'b0)
10660
        begin
10661
          test_fail("Receive should not start at all");
10662
          fail = fail + 1;
10663
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
10664
        end
10665
        if (tmp[7:0] !== 0)
10666
        begin
10667
          test_fail("Receive should not be finished since it should not start at all");
10668
          fail = fail + 1;
10669
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
10670
        end
10671
        @(posedge wb_clk);
10672
      end
10673
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10674
      if (tmp[6:0] !== 0)
10675
      begin
10676
        test_fail("Receive should not get INT since it should not start at all");
10677
        fail = fail + 1;
10678
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
10679
      end
10680
      clear_rx_bd(0, i);
10681
      if ((i < 5) || (i > 124))
10682
        i = i + 1;
10683
      else
10684
        i = i + 120;
10685
    end
10686
    // disable RX
10687
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
10688
              `ETH_MODER_PRO | `ETH_MODER_BRO,
10689
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10690
    if(fail == 0)
10691
      test_ok;
10692
    else
10693
      fail = 0;
10694
  end
10695
 
10696
 
10697
  ////////////////////////////////////////////////////////////////////
10698
  ////                                                            ////
10699
  ////  Test no receive when all buffers are TX ( 100Mbps ).      ////
10700
  ////                                                            ////
10701
  ////////////////////////////////////////////////////////////////////
10702
  if (test_num == 1) // Test no receive when all buffers are TX ( 100Mbps ).
10703
  begin
10704
    // TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
10705
    test_name   = "TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )";
10706
    `TIME; $display("  TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )");
10707
 
10708
    // unmask interrupts
10709
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
10710
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10711
    // set all buffer descriptors to TX - must be set before RX enable
10712
    wbm_write(`ETH_TX_BD_NUM, 32'h80, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10713 223 tadejm
    // enable RX, set full-duplex mode, receive small, NO correct IFG
10714 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
10715
              `ETH_MODER_PRO | `ETH_MODER_BRO,
10716
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10717
 
10718
    // write to phy's control register for 100Mbps
10719
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
10720
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
10721
    speed = 100;
10722
 
10723
    i = 0;
10724
    while (i < 128)
10725
    begin
10726
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
10727
      begin
10728
        set_rx_packet((i1 * 50), 10, 1'b0, 48'h1234_5678_8765, 48'h0011_2233_4455, 16'h0101, 8'h0);
10729
        append_rx_crc((i1 * 50), 10, 1'b0, 1'b0);
10730
        set_rx_bd(i1, i1, 1'b1, (`MEMORY_BASE + (i1 * 50)));
10731
      end
10732
      set_rx_bd_wrap(i);
10733
      set_rx_bd_empty(0, i);
10734
      for (i1 = 0; i1 <= i; i1 = i1 + 1)
10735
      begin
10736
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, (i1 * 50), 14, 1'b0);
10737
        repeat(10) @(posedge mrx_clk);
10738
      end
10739
      @(posedge mrx_clk);
10740
      for (i2 = 0; i2 < 20; i2 = i2 + 1)
10741
      begin
10742
        check_rx_bd(0, tmp);
10743
        #1;
10744
        if (tmp[15] === 1'b0)
10745
        begin
10746
          test_fail("Receive should not start at all");
10747
          fail = fail + 1;
10748
          `TIME; $display("*E Receive of %d packets should not start at all - empty is 0", i);
10749
        end
10750
        if (tmp[7:0] !== 0)
10751
        begin
10752
          test_fail("Receive should not be finished since it should not start at all");
10753
          fail = fail + 1;
10754
          `TIME; $display("*E Receive of should not be finished since it should not start at all");
10755
        end
10756
        @(posedge wb_clk);
10757
      end
10758
      wbm_read(`ETH_INT, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10759
      if (tmp[6:0] !== 0)
10760
      begin
10761
        test_fail("Receive should not get INT since it should not start at all");
10762
        fail = fail + 1;
10763
        `TIME; $display("*E Receive of should not get INT since it should not start at all");
10764
      end
10765
      clear_rx_bd(0, i);
10766
      if ((i < 5) || (i > 124))
10767
        i = i + 1;
10768
      else
10769
        i = i + 120;
10770
    end
10771
    // disable RX
10772
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
10773
              `ETH_MODER_PRO | `ETH_MODER_BRO,
10774
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10775
    if(fail == 0)
10776
      test_ok;
10777
    else
10778
      fail = 0;
10779
  end
10780
 
10781
 
10782
  ////////////////////////////////////////////////////////////////////
10783
  ////                                                            ////
10784 243 tadejm
  ////  Test receive packet synchronization with receive          ////
10785
  ////  disable/enable ( 10Mbps ).                                ////
10786
  ////                                                            ////
10787
  ////////////////////////////////////////////////////////////////////
10788
  if (test_num == 2) // Test no receive when all buffers are TX ( 10Mbps ).
10789
  begin
10790
    // TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
10791
    test_name   = "TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
10792
    `TIME; $display("  TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
10793
 
10794
    // unmask interrupts
10795
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
10796
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10797
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
10798
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10799
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
10800
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
10801
              `ETH_MODER_PRO | `ETH_MODER_BRO,
10802
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10803
    // prepare two packets of MAXFL length
10804
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
10805
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
10806
    min_tmp = tmp[31:16];
10807
    st_data = 8'h0F;
10808
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
10809
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
10810
    st_data = 8'h1A;
10811
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
10812
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
10813
    // check WB INT signal
10814
    if (wb_int !== 1'b0)
10815
    begin
10816
      test_fail("WB INT signal should not be set");
10817
      fail = fail + 1;
10818
    end
10819
 
10820
    // write to phy's control register for 10Mbps
10821
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
10822
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
10823
    speed = 10;
10824
 
10825
    frame_started = 0;
10826
    frame_ended = 0;
10827
    wait_for_frame = 0;
10828
    check_frame = 0;
10829
    stop_checking_frame = 0;
10830
    first_fr_received = 1; // at the beginning the first frame of each two will be received!
10831
 
10832
    num_of_frames = 0; // 
10833
    num_of_bd = 0;
10834
    i_length = (min_tmp + 1); // 5 bytes longer than MINFL
10835
    while (i_length < (max_tmp - 4))
10836
    begin
10837
      // choose generating carrier sense and collision 
10838
      case (num_of_frames[1:0])
10839
      2'h0: // Interrupt is generated
10840
      begin
10841
        // enable interrupt generation
10842
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
10843
        // not detect carrier sense in FD and no collision
10844
        eth_phy.no_carrier_sense_rx_fd_detect(0);
10845
        eth_phy.collision(0);
10846
      end
10847
      2'h1: // Interrupt is generated
10848
      begin
10849
        // enable interrupt generation
10850
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
10851
        // detect carrier sense in FD and no collision
10852
        eth_phy.no_carrier_sense_rx_fd_detect(1);
10853
        eth_phy.collision(0);
10854
      end
10855
      2'h2: // Interrupt is generated
10856
      begin
10857
        // disable interrupt generation
10858
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
10859
        // not detect carrier sense in FD and set collision
10860
        eth_phy.no_carrier_sense_rx_fd_detect(0);
10861
        eth_phy.collision(1);
10862
      end
10863
      default: // 2'h3: // Interrupt is generated
10864
      begin
10865
        // disable interrupt generation
10866
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
10867
        // detect carrier sense in FD and set collision
10868
        eth_phy.no_carrier_sense_rx_fd_detect(1);
10869
        eth_phy.collision(1);
10870
      end
10871
      endcase
10872
      // set wrap bit
10873
      set_rx_bd_wrap(118);
10874
      set_rx_bd_empty(118, 118);
10875
      check_frame = 0;
10876
      stop_checking_frame = 0;
10877
      tmp_data = 0;
10878
      fork
10879
        begin // enable RX MAC on first of each two packets - every second should be recived normaly
10880
          if (num_of_frames[0] == 1'b0)
10881
          begin
10882
            repeat(1) @(posedge wb_clk);
10883
            if (num_of_frames[1] == 1'b0)
10884
            begin
10885
              repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
10886
            end
10887
            else
10888
            begin
10889
              @(posedge mrx_clk);
10890
              repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
10891
            end
10892
            // enable RX, set full-duplex mode, NO receive small, NO correct IFG
10893
            wbm_init_waits = 4'h0;
10894
            wbm_subseq_waits = 4'h0;
10895
            #1 wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
10896
                      `ETH_MODER_PRO | `ETH_MODER_BRO,
10897
                      4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
10898
          end
10899
        end
10900
        begin // send a packet from PHY RX
10901
          repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
10902
          if (num_of_frames[1] == 1'b0)
10903
          begin
10904
            set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
10905
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
10906
          end
10907
          else
10908
          begin
10909
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
10910
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
10911
          end
10912
        end
10913
        begin: send_packet0
10914
          wait (MRxDV === 1'b1); // start transmit
10915
          wait (MRxDV === 1'b0); // end transmit
10916
          check_frame = 1;
10917
          repeat(10) @(posedge mrx_clk);
10918
          repeat(15) @(posedge wb_clk);
10919
          stop_checking_frame = 1;
10920
        end
10921
        begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
10922
          @(posedge eth_sl_wb_ack_o or posedge MRxDV);
10923
          if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
10924
          begin
10925
            tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
10926
          end
10927
          else if (MRxDV === 1'b1)
10928
          begin
10929
            while (eth_sl_wb_ack_o === 1'b0)
10930
            begin
10931
              @(posedge wb_clk);
10932
              tmp_data = tmp_data + 1;
10933
            end
10934
            tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
10935
          end
10936
          else if (eth_sl_wb_ack_o === 1'b1)
10937
          begin
10938
            @(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
10939
            while (MRxDV === 1'b0)
10940
            begin
10941
              @(posedge wb_clk);
10942
              tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
10943
            end
10944
          end
10945
        end
10946
        begin // check packet
10947
          wait (check_frame == 1);
10948
          check_rx_bd(118, tmp_bd);
10949
          while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
10950
          begin
10951
            #1 check_rx_bd(118, tmp_bd);
10952
            @(posedge wb_clk);
10953
          end
10954
          if (num_of_frames[0] == 1'b0)
10955
          begin
10956
            if (tmp_bd[15] === 1)
10957
            begin
10958
              if (first_fr_received == 1)
10959
              begin
10960
                first_fr_received = 0;
10961
                $display("    %0d packets (without this one) are checked - packets are received by two in a set",
10962
                         num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
10963
                $display("    From this moment:");
10964
                $display("    first one of two packets (including this one) is not accepted due to late RX enable");
10965
                if (tmp_data[31])
10966
                  $display("    ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
10967
                else
10968
                  $display("    ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
10969
              end
10970
            end
10971
          end
10972
          if (stop_checking_frame == 0)
10973
            disable send_packet0;
10974
        end
10975
      join
10976
      // ONLY IF packet was received!
10977
      if (tmp_bd[15] === 0)
10978
      begin
10979
        // check length of a PACKET
10980
        if (tmp_bd[31:16] != (i_length + 4))
10981
        begin
10982
          `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
10983
                          tmp_bd[31:16], (i_length + 4));
10984
          test_fail("Wrong length of the packet out from PHY");
10985
          fail = fail + 1;
10986
        end
10987
        // check received RX packet data and CRC
10988
        if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
10989
        begin
10990
          if (num_of_frames[1] == 1'b0)
10991
          begin
10992
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
10993
          end
10994
          else
10995
          begin
10996
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
10997
          end
10998
          if (tmp > 0)
10999
          begin
11000
            `TIME; $display("*E Wrong data of the received packet");
11001
            test_fail("Wrong data of the received packet");
11002
            fail = fail + 1;
11003
          end
11004
        end
11005
        else // if PREVIOUS RX buffer descriptor was ready
11006
        begin
11007
          if (num_of_frames[1] == 1'b0)
11008
          begin
11009
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11010
          end
11011
          else
11012
          begin
11013
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11014
          end
11015
          if (tmp > 0)
11016
          begin
11017
            `TIME; $display("*E Wrong data of the received packet");
11018
            test_fail("Wrong data of the received packet");
11019
            fail = fail + 1;
11020
          end
11021
        end
11022
      end
11023
      // check WB INT signal
11024
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11025
      begin
11026
        if (wb_int !== 1'b0)
11027
        begin
11028
          `TIME; $display("*E WB INT signal should not be set");
11029
          test_fail("WB INT signal should not be set");
11030
          fail = fail + 1;
11031
        end
11032
      end
11033
      else
11034
      begin
11035
        if (wb_int !== 1'b1)
11036
        begin
11037
          `TIME; $display("*E WB INT signal should be set");
11038
          test_fail("WB INT signal should be set");
11039
          fail = fail + 1;
11040
        end
11041
      end
11042
      // check RX buffer descriptor of a packet - only 15 LSBits
11043
      check_rx_bd(118, data);
11044
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11045
      begin
11046
        if (data[15:0] !== 16'hE000)
11047
        begin
11048
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11049
          test_fail("RX buffer descriptor status is not correct");
11050
          fail = fail + 1;
11051
        end
11052
      end
11053
      else // interrupt enabled
11054
      begin
11055
        if (data[15:0] !== 16'h6000)
11056
        begin
11057
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11058
          test_fail("RX buffer descriptor status is not correct");
11059
          fail = fail + 1;
11060
        end
11061
      end
11062
      // check interrupts
11063
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11064
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11065
      begin
11066
        if (data !== 0)
11067
        begin
11068
          `TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
11069
          test_fail("Any of interrupts was set");
11070
          fail = fail + 1;
11071
        end
11072
      end
11073
      else
11074
      begin
11075
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
11076
        begin
11077
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
11078
          test_fail("Interrupt Receive Buffer was not set");
11079
          fail = fail + 1;
11080
        end
11081
        if ((data & (~`ETH_INT_RXB)) !== 0)
11082
        begin
11083
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
11084
          test_fail("Other interrupts (except Receive Buffer) were set");
11085
          fail = fail + 1;
11086
        end
11087
      end
11088
      // clear interrupts
11089
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11090
      // check WB INT signal
11091
      if (wb_int !== 1'b0)
11092
      begin
11093
        test_fail("WB INT signal should not be set");
11094
        fail = fail + 1;
11095
      end
11096
      // disable RX after two packets
11097
      if (num_of_frames[0] == 1'b1)
11098
      begin
11099
        // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11100
        wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11101
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
11102
                  4'hF, 1, 4'h0, 4'h0); // write ASAP
11103
      end
11104
      // the number of frame transmitted
11105
      num_of_frames = num_of_frames + 1;
11106
      num_of_bd = 0;
11107
      // set length (LOOP variable)
11108
      if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
11109
        i_length = (max_tmp - 4);
11110
      @(posedge wb_clk);
11111
    end
11112
    // disable RX
11113
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11114
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11115
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11116
    if(fail == 0)
11117
      test_ok;
11118
    else
11119
      fail = 0;
11120
  end
11121
 
11122
 
11123
  ////////////////////////////////////////////////////////////////////
11124
  ////                                                            ////
11125
  ////  Test receive packet synchronization with receive          ////
11126
  ////  disable/enable ( 100Mbps ).                               ////
11127
  ////                                                            ////
11128
  ////////////////////////////////////////////////////////////////////
11129
  if (test_num == 3) // Test no receive when all buffers are TX ( 100Mbps ).
11130
  begin
11131
    // TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
11132
    test_name   = "TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )";
11133
    `TIME; $display("  TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )");
11134
 
11135
    // unmask interrupts
11136
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11137
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11138
    // set 10 RX buffer descriptor (8'h80 - 8'hA) - must be set before RX enable
11139
    wbm_write(`ETH_TX_BD_NUM, 32'h76, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11140
    // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11141
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11142
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11143
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11144
    // prepare two packets of MAXFL length
11145
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11146
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
11147
    min_tmp = tmp[31:16];
11148
    st_data = 8'h0F;
11149
    set_rx_packet(0, (min_tmp + 1), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
11150
    append_rx_crc(0, (min_tmp + 1), 1'b0, 1'b0);
11151
    st_data = 8'h1A;
11152
    set_rx_packet(max_tmp, (min_tmp + 1), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
11153
    append_rx_crc(max_tmp, (min_tmp + 1), 1'b0, 1'b0);
11154
    // check WB INT signal
11155
    if (wb_int !== 1'b0)
11156
    begin
11157
      test_fail("WB INT signal should not be set");
11158
      fail = fail + 1;
11159
    end
11160
 
11161
    // write to phy's control register for 100Mbps
11162
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
11163
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
11164
    speed = 100;
11165
 
11166
    frame_started = 0;
11167
    frame_ended = 0;
11168
    wait_for_frame = 0;
11169
    check_frame = 0;
11170
    stop_checking_frame = 0;
11171
    first_fr_received = 1; // at the beginning the first frame of each two will be received!
11172
 
11173
    num_of_frames = 0; // 
11174
    num_of_bd = 0;
11175
    i_length = (min_tmp + 1); // 5 bytes longer than MINFL
11176
    while (i_length < (max_tmp - 4))
11177
    begin
11178
      // choose generating carrier sense and collision 
11179
      case (num_of_frames[1:0])
11180
      2'h0: // Interrupt is generated
11181
      begin
11182
        // enable interrupt generation
11183
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11184
        // not detect carrier sense in FD and no collision
11185
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11186
        eth_phy.collision(0);
11187
      end
11188
      2'h1: // Interrupt is generated
11189
      begin
11190
        // enable interrupt generation
11191
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11192
        // detect carrier sense in FD and no collision
11193
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11194
        eth_phy.collision(0);
11195
      end
11196
      2'h2: // Interrupt is generated
11197
      begin
11198
        // disable interrupt generation
11199
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11200
        // not detect carrier sense in FD and set collision
11201
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11202
        eth_phy.collision(1);
11203
      end
11204
      default: // 2'h3: // Interrupt is generated
11205
      begin
11206
        // disable interrupt generation
11207
        set_rx_bd(118, 118, 1'b1, (`MEMORY_BASE + num_of_frames[1:0]));
11208
        // detect carrier sense in FD and set collision
11209
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11210
        eth_phy.collision(1);
11211
      end
11212
      endcase
11213
//if (first_fr_received == 0)
11214
//begin
11215
//  check_rx_bd(118, data);
11216
//  wbm_read((`TX_BD_BASE + (118 * 8) + 4), tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11217
//  $display("RX BD set : %h, %h", data, tmp);
11218
//end
11219
      // set wrap bit
11220
      set_rx_bd_wrap(118);
11221
      set_rx_bd_empty(118, 118);
11222
      check_frame = 0;
11223
      stop_checking_frame = 0;
11224
      tmp_data = 0;
11225
$display("mama 1");
11226
      fork
11227
        begin // enable RX MAC on first of each two packets - every second should be recived normaly
11228
          if (num_of_frames[0] == 1'b0)
11229
          begin
11230
            repeat(1) @(posedge wb_clk);
11231
            if (num_of_frames[1] == 1'b0)
11232
            begin
11233
              repeat (num_of_frames[31:2]) @(posedge mrx_clk); // for every (second) frame enable receiver one clock later
11234
            end
11235
            else
11236
            begin
11237
              @(posedge mrx_clk);
11238
              repeat (num_of_frames[31:2]) @(negedge mrx_clk); // for every (second) frame enable receiver one clock later
11239
            end
11240
            // enable RX, set full-duplex mode, NO receive small, NO correct IFG
11241
            wbm_init_waits = 4'h0;
11242
            wbm_subseq_waits = 4'h0;
11243
            #1 wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11244
                      `ETH_MODER_PRO | `ETH_MODER_BRO,
11245
                      4'hF, 1, wbm_init_waits, wbm_subseq_waits); // write ASAP
11246
$display("mama 2, num_of_frames=%0h", num_of_frames);
11247
          end
11248
        end
11249
        begin // send a packet from PHY RX
11250
          repeat(1) @(posedge wb_clk); // wait for WB write when it is without delays
11251
          if (num_of_frames[1] == 1'b0)
11252
          begin
11253
            set_rx_addr_type(0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E);
11254
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
11255
          end
11256
          else
11257
          begin
11258
            set_rx_addr_type((max_tmp), 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E);
11259
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
11260
          end
11261
        end
11262
        begin: send_packet1
11263
          wait (MRxDV === 1'b1); // start transmit
11264
          wait (MRxDV === 1'b0); // end transmit
11265
          check_frame = 1;
11266
$display("mama 3");
11267
          repeat(10) @(posedge mrx_clk);
11268
          repeat(15) @(posedge wb_clk);
11269
          stop_checking_frame = 1;
11270
        end
11271
        begin // count WB clocks between ACK (negedge) and RX_DV (posedge) or vice-versa
11272
          @(posedge eth_sl_wb_ack_o or posedge MRxDV);
11273
$display("mama 4");
11274
          if ((eth_sl_wb_ack_o === 1'b1) && (MRxDV === 1'b1))
11275
          begin
11276
            tmp_data = 32'h8000_0001; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11277
$display("mama 4_1");
11278
          end
11279
          else if (MRxDV === 1'b1)
11280
          begin
11281
            while (eth_sl_wb_ack_o === 1'b0)
11282
            begin
11283
              @(posedge wb_clk);
11284
              tmp_data = tmp_data + 1;
11285
            end
11286
            tmp_data = tmp_data | 32'h8000_0000; // bit[31]==1 => 'posedge MRxDV' was before 'negedge eth_sl_wb_ack_o'
11287
$display("mama 4_2");
11288
          end
11289
          else if (eth_sl_wb_ack_o === 1'b1)
11290
          begin
11291
            @(posedge wb_clk); // wait for one clock => tmp_data 'becomes' 0
11292
            while (MRxDV === 1'b0)
11293
            begin
11294
              @(posedge wb_clk);
11295
              tmp_data = tmp_data + 1; // bit[31]==0 => 'negedge eth_sl_wb_ack_o' was equal or before 'posedge MRxDV'
11296
            end
11297
$display("mama 4_3");
11298
          end
11299
        end
11300
        begin // check packet
11301
          wait (check_frame == 1);
11302
          check_rx_bd(118, tmp_bd);
11303
          while ((tmp_bd[15] === 1) && (stop_checking_frame == 0))
11304
          begin
11305
            #1 check_rx_bd(118, tmp_bd);
11306
            @(posedge wb_clk);
11307
          end
11308
$display("mama 5, tmp_bd=%0h", tmp_bd);
11309
          if (num_of_frames[0] == 1'b0)
11310
          begin
11311
            if (tmp_bd[15] === 1)
11312
            begin
11313
              if (first_fr_received == 1)
11314
              begin
11315
                first_fr_received = 0;
11316
                $display("    %0d packets (without this one) are checked - packets are received by two in a set",
11317
                         num_of_frames); // +1 due to start with 0 AND -1 because this packet is excluded
11318
                $display("    From this moment:");
11319
                $display("    first one of two packets (including this one) is not accepted due to late RX enable");
11320
                if (tmp_data[31])
11321
                  $display("    ->RX enable set %0d WB clks after RX_DV", tmp_data[30:0]);
11322
                else
11323
                  $display("    ->RX enable set %0d WB clks before RX_DV", tmp_data[30:0]);
11324
              end
11325
              // check FB, etc.
11326
 
11327
            end
11328
            else // (tmp_bd[15] === 0)
11329
            begin // check FB, packet, etc.
11330
 
11331
            end
11332
$display("mama 5_1");
11333
          end
11334
          else // (num_of_frames[0] == 1'b1)
11335
          begin
11336
            if (tmp_bd[15] === 1) // ERROR, because second packet of each two frames should be received
11337
            begin // check NOTHING
11338
 
11339
            end
11340
            else // (tmp_bd[15] === 0)
11341
            begin // check FB, packet, etc.
11342
 
11343
            end
11344
$display("mama 5_2");
11345
          end
11346
          if (stop_checking_frame == 0)
11347
            disable send_packet1;
11348
        end
11349
      join
11350
      // ONLY IF packet was received!
11351
$display("mama 6");
11352
      if (tmp_bd[15] === 0)
11353
      begin
11354
        // check length of a PACKET
11355
        if (tmp_bd[31:16] != (i_length + 4))
11356
        begin
11357
          `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
11358
                          tmp_bd[31:16], (i_length + 4));
11359
          test_fail("Wrong length of the packet out from PHY");
11360
          fail = fail + 1;
11361
        end
11362
        // check received RX packet data and CRC
11363
        if (first_fr_received == 0) // if PREVIOUS RX buffer descriptor was not ready, pointer address is -1
11364
        begin
11365
          if (num_of_frames[1] == 1'b0)
11366
          begin
11367
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11368
          end
11369
          else
11370
          begin
11371
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0] - 1'b1), (i_length + 4), 1'b0, 1'b0, tmp);
11372
          end
11373
          if (tmp > 0)
11374
          begin
11375
            `TIME; $display("*E Wrong data of the received packet");
11376
            test_fail("Wrong data of the received packet");
11377
            fail = fail + 1;
11378
          end
11379
        end
11380
        else // if PREVIOUS RX buffer descriptor was ready
11381
        begin
11382
          if (num_of_frames[1] == 1'b0)
11383
          begin
11384
            check_rx_packet(0, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11385
          end
11386
          else
11387
          begin
11388
            check_rx_packet(max_tmp, (`MEMORY_BASE + num_of_frames[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11389
          end
11390
          if (tmp > 0)
11391
          begin
11392
            `TIME; $display("*E Wrong data of the received packet");
11393
            test_fail("Wrong data of the received packet");
11394
            fail = fail + 1;
11395
          end
11396
        end
11397
      end
11398
      // check WB INT signal
11399
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11400
      begin
11401
        if (wb_int !== 1'b0)
11402
        begin
11403
          `TIME; $display("*E WB INT signal should not be set");
11404
          test_fail("WB INT signal should not be set");
11405
          fail = fail + 1;
11406
        end
11407
      end
11408
      else
11409
      begin
11410
        if (wb_int !== 1'b1)
11411
        begin
11412
          `TIME; $display("*E WB INT signal should be set");
11413
          test_fail("WB INT signal should be set");
11414
          fail = fail + 1;
11415
        end
11416
      end
11417
      // check RX buffer descriptor of a packet - only 15 LSBits
11418
      check_rx_bd(118, data);
11419
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11420
      begin
11421
        if (data[15:0] !== 16'hE000)
11422
        begin
11423
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11424
          test_fail("RX buffer descriptor status is not correct");
11425
          fail = fail + 1;
11426
        end
11427
      end
11428
      else // interrupt enabled
11429
      begin
11430
        if (data[15:0] !== 16'h6000)
11431
        begin
11432
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11433
          test_fail("RX buffer descriptor status is not correct");
11434
          fail = fail + 1;
11435
        end
11436
      end
11437
      // check interrupts
11438
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11439
      if ((num_of_frames[0] == 1'b0) && (first_fr_received == 0)) // interrupt enabled but no receive
11440
      begin
11441
        if (data !== 0)
11442
        begin
11443
          `TIME; $display("*E Any of interrupts was set, interrupt reg: %0h, len: %0h", data, num_of_frames[1:0]);
11444
          test_fail("Any of interrupts was set");
11445
          fail = fail + 1;
11446
        end
11447
      end
11448
      else
11449
      begin
11450
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
11451
        begin
11452
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
11453
          test_fail("Interrupt Receive Buffer was not set");
11454
          fail = fail + 1;
11455
        end
11456
        if ((data & (~`ETH_INT_RXB)) !== 0)
11457
        begin
11458
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
11459
          test_fail("Other interrupts (except Receive Buffer) were set");
11460
          fail = fail + 1;
11461
        end
11462
      end
11463
      // clear interrupts
11464
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11465
      // check WB INT signal
11466
      if (wb_int !== 1'b0)
11467
      begin
11468
        test_fail("WB INT signal should not be set");
11469
        fail = fail + 1;
11470
      end
11471
      // disable RX after two packets
11472
      if (num_of_frames[0] == 1'b1)
11473
      begin
11474
        // disable RX, set full-duplex mode, NO receive small, NO correct IFG
11475
        wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_IFG |
11476
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
11477
                  4'hF, 1, 4'h0, 4'h0); // write ASAP
11478
      end
11479
      // the number of frame transmitted
11480
      num_of_frames = num_of_frames + 1;
11481
      num_of_bd = 0;
11482
      // set length (LOOP variable)
11483
      if (num_of_frames[31:2] == (i_length * 2 + 16)) // 64 => this vas last Byte (1st .. 64th) when i_length = min_tmp - 4
11484
        i_length = (max_tmp - 4);
11485
      @(posedge wb_clk);
11486
    end
11487
    // disable RX
11488
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11489
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11490
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11491
    if(fail == 0)
11492
      test_ok;
11493
    else
11494
      fail = 0;
11495
  end
11496
 
11497
 
11498
  ////////////////////////////////////////////////////////////////////
11499
  ////                                                            ////
11500 209 tadejm
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
11501
  ////  one RX buffer decriptor ( 10Mbps ).                       ////
11502
  ////                                                            ////
11503
  ////////////////////////////////////////////////////////////////////
11504 243 tadejm
  if (test_num == 4) // 
11505 209 tadejm
  begin
11506 243 tadejm
    // TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )
11507
    test_name   = "TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )";
11508
    `TIME; $display("  TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )");
11509 209 tadejm
 
11510
    // unmask interrupts
11511
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11512
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11513
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
11514
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11515
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
11516
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11517
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11518
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11519
    // prepare two packets of MAXFL length
11520
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11521
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
11522
    min_tmp = tmp[31:16];
11523
    st_data = 8'h0F;
11524
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
11525
    st_data = 8'h1A;
11526
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
11527
    // check WB INT signal
11528
    if (wb_int !== 1'b0)
11529
    begin
11530
      test_fail("WB INT signal should not be set");
11531
      fail = fail + 1;
11532
    end
11533
 
11534
    // write to phy's control register for 10Mbps
11535
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
11536
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
11537
    speed = 10;
11538
 
11539
    i_length = (min_tmp - 4);
11540
    while (i_length <= (max_tmp - 4))
11541
    begin
11542
      // choose generating carrier sense and collision for first and last 64 lengths of frames
11543
      case (i_length[1:0])
11544
      2'h0: // Interrupt is generated
11545
      begin
11546
        // enable interrupt generation
11547
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
11548
        // unmask interrupts
11549
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11550
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11551
        // not detect carrier sense in FD and no collision
11552
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11553
        eth_phy.collision(0);
11554
      end
11555
      2'h1: // Interrupt is not generated
11556
      begin
11557
        // enable interrupt generation
11558
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
11559
        // mask interrupts
11560
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11561
        // detect carrier sense in FD and no collision
11562
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11563
        eth_phy.collision(0);
11564
      end
11565
      2'h2: // Interrupt is not generated
11566
      begin
11567
        // disable interrupt generation
11568
        set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i_length[1:0]));
11569
        // unmask interrupts
11570
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11571
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11572
        // not detect carrier sense in FD and set collision
11573
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11574
        eth_phy.collision(1);
11575
      end
11576
      default: // 2'h3: // Interrupt is not generated
11577
      begin
11578
        // disable interrupt generation
11579
        set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
11580
        // mask interrupts
11581
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11582
        // detect carrier sense in FD and set collision
11583
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11584
        eth_phy.collision(1);
11585
      end
11586
      endcase
11587
      if (i_length[0] == 1'b0)
11588
        append_rx_crc (0, i_length, 1'b0, 1'b0);
11589
      else
11590
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
11591
      // set wrap bit
11592
      set_rx_bd_wrap(127);
11593
      set_rx_bd_empty(127, 127);
11594
      fork
11595
        begin
11596
          if (i_length[0] == 1'b0)
11597
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
11598
          else
11599
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
11600
          repeat(10) @(posedge mrx_clk);
11601
        end
11602
        begin
11603
          #1 check_rx_bd(127, data);
11604
          if (i_length < min_tmp) // just first four
11605
          begin
11606
            while (data[15] === 1)
11607
            begin
11608
              #1 check_rx_bd(127, data);
11609
              @(posedge wb_clk);
11610
            end
11611
            repeat (1) @(posedge wb_clk);
11612
          end
11613
          else
11614
          begin
11615
            wait (MRxDV === 1'b1); // start transmit
11616
            #1 check_rx_bd(127, data);
11617
            if (data[15] !== 1)
11618
            begin
11619
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
11620
              fail = fail + 1;
11621
            end
11622
            wait (MRxDV === 1'b0); // end transmit
11623
            while (data[15] === 1)
11624
            begin
11625
              #1 check_rx_bd(127, data);
11626
              @(posedge wb_clk);
11627
            end
11628
            repeat (1) @(posedge wb_clk);
11629
          end
11630
        end
11631
      join
11632
      // check length of a PACKET
11633
      if (data[31:16] != (i_length + 4))
11634
      begin
11635
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
11636
                        data[31:16], (i_length + 4));
11637
        test_fail("Wrong length of the packet out from PHY");
11638
        fail = fail + 1;
11639
      end
11640
      // checking in the following if statement is performed only for first and last 64 lengths
11641
      // check received RX packet data and CRC
11642
      if (i_length[0] == 1'b0)
11643
      begin
11644
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11645
      end
11646
      else
11647
      begin
11648
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
11649
      end
11650
      if (tmp > 0)
11651
      begin
11652
        `TIME; $display("*E Wrong data of the received packet");
11653
        test_fail("Wrong data of the received packet");
11654
        fail = fail + 1;
11655
      end
11656
      // check WB INT signal
11657
      if (i_length[1:0] == 2'h0)
11658
      begin
11659
        if (wb_int !== 1'b1)
11660
        begin
11661
          `TIME; $display("*E WB INT signal should be set");
11662
          test_fail("WB INT signal should be set");
11663
          fail = fail + 1;
11664
        end
11665
      end
11666
      else
11667
      begin
11668
        if (wb_int !== 1'b0)
11669
        begin
11670
          `TIME; $display("*E WB INT signal should not be set");
11671
          test_fail("WB INT signal should not be set");
11672
          fail = fail + 1;
11673
        end
11674
      end
11675
      // check RX buffer descriptor of a packet
11676
      check_rx_bd(127, data);
11677
      if (i_length[1] == 1'b0) // interrupt enabled no_carrier_sense_rx_fd_detect
11678
      begin
11679
        if ( ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b0)) ||
11680
             ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b1)) )
11681
        begin
11682
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11683
          test_fail("RX buffer descriptor status is not correct");
11684
          fail = fail + 1;
11685
        end
11686
      end
11687
      else // interrupt not enabled
11688
      begin
11689
        if ( ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b0)) ||
11690
             ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b1)) )
11691
        begin
11692
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11693
          test_fail("RX buffer descriptor status is not correct");
11694
          fail = fail + 1;
11695
        end
11696
      end
11697
      // clear RX buffer descriptor for first 4 frames
11698
      if (i_length < min_tmp)
11699
        clear_rx_bd(127, 127);
11700
      // check interrupts
11701
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11702
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
11703
      begin
11704
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
11705
        begin
11706
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
11707
          test_fail("Interrupt Receive Buffer was not set");
11708
          fail = fail + 1;
11709
        end
11710
        if ((data & (~`ETH_INT_RXB)) !== 0)
11711
        begin
11712
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
11713
          test_fail("Other interrupts (except Receive Buffer) were set");
11714
          fail = fail + 1;
11715
        end
11716
      end
11717
      else
11718
      begin
11719
        if (data !== 0)
11720
        begin
11721
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
11722
          test_fail("Any of interrupts (except Receive Buffer) was set");
11723
          fail = fail + 1;
11724
        end
11725
      end
11726
      // clear interrupts
11727
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11728
      // check WB INT signal
11729
      if (wb_int !== 1'b0)
11730
      begin
11731
        test_fail("WB INT signal should not be set");
11732
        fail = fail + 1;
11733
      end
11734
      // INTERMEDIATE DISPLAYS
11735
      if ((i_length + 4) == (min_tmp + 64))
11736
      begin
11737
        // starting length is min_tmp, ending length is (min_tmp + 64)
11738
        $display("    receive small packets is NOT selected");
11739
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
11740
                 min_tmp, (min_tmp + 64));
11741
        // set receive small, remain the rest
11742
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11743
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
11744
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11745
      end
11746
      else if ((i_length + 4) == (max_tmp - 16))
11747
      begin
11748
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
11749
        $display("    receive small packets is selected");
11750
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
11751
                 (min_tmp + 64 + 128), tmp_data);
11752
        // reset receive small, remain the rest
11753
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11754
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
11755
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11756
      end
11757
      else if ((i_length + 4) == max_tmp)
11758
      begin
11759
        $display("    receive small packets is NOT selected");
11760
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
11761
                 (max_tmp - (4 + 16)), max_tmp);
11762
      end
11763
      // set length (loop variable)
11764
      if ((i_length + 4) < (min_tmp + 64))
11765
        i_length = i_length + 1;
11766
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
11767
      begin
11768
        i_length = i_length + 128;
11769
        tmp_data = i_length + 4; // last tmp_data is ending length
11770
      end
11771
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
11772
        i_length = max_tmp - (4 + 16);
11773
      else if ((i_length + 4) >= (max_tmp - 16))
11774
        i_length = i_length + 1;
11775
      else
11776
      begin
11777
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
11778
        #10 $stop;
11779
      end
11780
    end
11781
    // disable RX
11782
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
11783
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11784
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11785
    if(fail == 0)
11786
      test_ok;
11787
    else
11788
      fail = 0;
11789
  end
11790
 
11791
 
11792
  ////////////////////////////////////////////////////////////////////
11793
  ////                                                            ////
11794
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
11795
  ////  one RX buffer decriptor ( 100Mbps ).                      ////
11796
  ////                                                            ////
11797
  ////////////////////////////////////////////////////////////////////
11798 243 tadejm
  if (test_num == 5) // Test no receive when all buffers are TX ( 100Mbps ).
11799 209 tadejm
  begin
11800 243 tadejm
    // TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
11801
    test_name   = "TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )";
11802
    `TIME; $display("  TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )");
11803 209 tadejm
 
11804
    // unmask interrupts
11805
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11806
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11807
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
11808
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11809
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
11810
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
11811
              `ETH_MODER_PRO | `ETH_MODER_BRO,
11812
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11813
    // prepare two packets of MAXFL length
11814
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11815
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
11816
    min_tmp = tmp[31:16];
11817
    st_data = 8'h0F;
11818
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
11819
    st_data = 8'h1A;
11820
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
11821
    // check WB INT signal
11822
    if (wb_int !== 1'b0)
11823
    begin
11824
      test_fail("WB INT signal should not be set");
11825
      fail = fail + 1;
11826
    end
11827
 
11828
    // write to phy's control register for 100Mbps
11829
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
11830
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
11831
    speed = 100;
11832
 
11833
    i_length = (min_tmp - 4);
11834
    while (i_length <= (max_tmp - 4))
11835
    begin
11836
      // choose generating carrier sense and collision for first and last 64 lengths of frames
11837
      case (i_length[1:0])
11838
      2'h0: // Interrupt is generated
11839
      begin
11840
        // enable interrupt generation
11841
        set_rx_bd(127, 127, 1'b1, (`MEMORY_BASE + i_length[1:0]));
11842
        // unmask interrupts
11843
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11844
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11845
        // not detect carrier sense in FD and no collision
11846
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11847
        eth_phy.collision(0);
11848
      end
11849
      2'h1: // Interrupt is not generated
11850
      begin
11851
        // enable interrupt generation
11852
        set_rx_bd(127, 127, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
11853
        // mask interrupts
11854
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11855
        // detect carrier sense in FD and no collision
11856
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11857
        eth_phy.collision(0);
11858
      end
11859
      2'h2: // Interrupt is not generated
11860
      begin
11861
        // disable interrupt generation
11862
        set_rx_bd(127, 127, 1'b0, (`MEMORY_BASE + i_length[1:0]));
11863
        // unmask interrupts
11864
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
11865
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11866
        // not detect carrier sense in FD and set collision
11867
        eth_phy.no_carrier_sense_rx_fd_detect(0);
11868
        eth_phy.collision(1);
11869
      end
11870
      default: // 2'h3: // Interrupt is not generated
11871
      begin
11872
        // disable interrupt generation
11873
        set_rx_bd(127, 127, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
11874
        // mask interrupts
11875
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11876
        // detect carrier sense in FD and set collision
11877
        eth_phy.no_carrier_sense_rx_fd_detect(1);
11878
        eth_phy.collision(1);
11879
      end
11880
      endcase
11881
      if (i_length[0] == 1'b0)
11882
        append_rx_crc (0, i_length, 1'b0, 1'b0);
11883
      else
11884
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
11885
      // set wrap bit
11886
      set_rx_bd_wrap(127);
11887
      set_rx_bd_empty(127, 127);
11888
      fork
11889
        begin
11890
          if (i_length[0] == 1'b0)
11891
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
11892
          else
11893
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
11894
          repeat(10) @(posedge mrx_clk);
11895
        end
11896
        begin
11897
          #1 check_rx_bd(127, data);
11898
          if (i_length < min_tmp) // just first four
11899
          begin
11900
            while (data[15] === 1)
11901
            begin
11902
              #1 check_rx_bd(127, data);
11903
              @(posedge wb_clk);
11904
            end
11905
            repeat (1) @(posedge wb_clk);
11906
          end
11907
          else
11908
          begin
11909
            wait (MRxDV === 1'b1); // start transmit
11910
            #1 check_rx_bd(127, data);
11911
            if (data[15] !== 1)
11912
            begin
11913
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
11914
              fail = fail + 1;
11915
            end
11916
            wait (MRxDV === 1'b0); // end transmit
11917
            while (data[15] === 1)
11918
            begin
11919
              #1 check_rx_bd(127, data);
11920
              @(posedge wb_clk);
11921
            end
11922
            repeat (1) @(posedge wb_clk);
11923
          end
11924
        end
11925
      join
11926
      // check length of a PACKET
11927
      if (data[31:16] != (i_length + 4))
11928
      begin
11929
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
11930
                        data[31:16], (i_length + 4));
11931
        test_fail("Wrong length of the packet out from PHY");
11932
        fail = fail + 1;
11933
      end
11934
      // checking in the following if statement is performed only for first and last 64 lengths
11935
      // check received RX packet data and CRC
11936
      if (i_length[0] == 1'b0)
11937
      begin
11938
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
11939
      end
11940
      else
11941
      begin
11942
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
11943
      end
11944
      if (tmp > 0)
11945
      begin
11946
        `TIME; $display("*E Wrong data of the received packet");
11947
        test_fail("Wrong data of the received packet");
11948
        fail = fail + 1;
11949
      end
11950
      // check WB INT signal
11951
      if (i_length[1:0] == 2'h0)
11952
      begin
11953
        if (wb_int !== 1'b1)
11954
        begin
11955
          `TIME; $display("*E WB INT signal should be set");
11956
          test_fail("WB INT signal should be set");
11957
          fail = fail + 1;
11958
        end
11959
      end
11960
      else
11961
      begin
11962
        if (wb_int !== 1'b0)
11963
        begin
11964
          `TIME; $display("*E WB INT signal should not be set");
11965
          test_fail("WB INT signal should not be set");
11966
          fail = fail + 1;
11967
        end
11968
      end
11969
      // check RX buffer descriptor of a packet
11970
      check_rx_bd(127, data);
11971
      if (i_length[1] == 1'b0) // interrupt enabled 
11972
      begin
11973
        if ( ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b0)) ||
11974
             ((data[15:0] !== 16'h6000) && (i_length[0] == 1'b1)) )
11975
        begin
11976
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11977
          test_fail("RX buffer descriptor status is not correct");
11978
          fail = fail + 1;
11979
        end
11980
      end
11981
      else // interrupt not enabled
11982
      begin
11983
        if ( ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b0)) ||
11984
             ((data[15:0] !== 16'h2000) && (i_length[0] == 1'b1)) )
11985
        begin
11986
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
11987
          test_fail("RX buffer descriptor status is not correct");
11988
          fail = fail + 1;
11989
        end
11990
      end
11991
      // clear RX buffer descriptor for first 4 frames
11992
      if (i_length < min_tmp)
11993
        clear_rx_bd(127, 127);
11994
      // check interrupts
11995
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
11996
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
11997
      begin
11998
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
11999
        begin
12000
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
12001
          test_fail("Interrupt Receive Buffer was not set");
12002
          fail = fail + 1;
12003
        end
12004
        if ((data & (~`ETH_INT_RXB)) !== 0)
12005
        begin
12006
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
12007
          test_fail("Other interrupts (except Receive Buffer) were set");
12008
          fail = fail + 1;
12009
        end
12010
      end
12011
      else
12012
      begin
12013
        if (data !== 0)
12014
        begin
12015
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
12016
          test_fail("Any of interrupts (except Receive Buffer) was set");
12017
          fail = fail + 1;
12018
        end
12019
      end
12020
      // clear interrupts
12021
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12022
      // check WB INT signal
12023
      if (wb_int !== 1'b0)
12024
      begin
12025
        test_fail("WB INT signal should not be set");
12026
        fail = fail + 1;
12027
      end
12028
      // INTERMEDIATE DISPLAYS
12029
      if ((i_length + 4) == (min_tmp + 64))
12030
      begin
12031
        // starting length is min_tmp, ending length is (min_tmp + 64)
12032
        $display("    receive small packets is NOT selected");
12033
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
12034
                 min_tmp, (min_tmp + 64));
12035
        // set receive small, remain the rest
12036
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12037
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12038
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12039
      end
12040
      else if ((i_length + 4) == (max_tmp - 16))
12041
      begin
12042
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
12043
        $display("    receive small packets is selected");
12044
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
12045
                 (min_tmp + 64 + 128), tmp_data);
12046
        // reset receive small, remain the rest
12047
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12048
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12049
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12050
      end
12051
      else if ((i_length + 4) == max_tmp)
12052
      begin
12053
        $display("    receive small packets is NOT selected");
12054
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
12055
                 (max_tmp - (4 + 16)), max_tmp);
12056
      end
12057
      // set length (loop variable)
12058
      if ((i_length + 4) < (min_tmp + 64))
12059
        i_length = i_length + 1;
12060
      else if ( ((i_length + 4) >= (min_tmp + 64)) && ((i_length + 4) <= (max_tmp - 256)) )
12061
      begin
12062
        i_length = i_length + 128;
12063
        tmp_data = i_length + 4; // last tmp_data is ending length
12064
      end
12065
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
12066
        i_length = max_tmp - (4 + 16);
12067
      else if ((i_length + 4) >= (max_tmp - 16))
12068
        i_length = i_length + 1;
12069
      else
12070
      begin
12071
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
12072
        #10 $stop;
12073
      end
12074
    end
12075
    // disable RX
12076
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12077
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12078
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12079
    if(fail == 0)
12080
      test_ok;
12081
    else
12082
      fail = 0;
12083
  end
12084
 
12085
 
12086
  ////////////////////////////////////////////////////////////////////
12087
  ////                                                            ////
12088
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
12089
  ////  maximum RX buffer decriptors ( 10Mbps ).                  ////
12090
  ////                                                            ////
12091
  ////////////////////////////////////////////////////////////////////
12092 243 tadejm
  if (test_num == 6) // 
12093 209 tadejm
  begin
12094 243 tadejm
    // TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
12095
    test_name = "TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )";
12096
    `TIME; $display("  TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )");
12097 209 tadejm
 
12098
    // reset MAC registers
12099
    hard_reset;
12100
    // reset MAC and MII LOGIC with soft reset
12101
    reset_mac;
12102
    reset_mii;
12103
    // set wb slave response
12104
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
12105
 
12106
    max_tmp = 0;
12107
    min_tmp = 0;
12108
    num_of_frames = 0;
12109
    num_of_bd = 0;
12110
    // set maximum RX buffer descriptors (128) - must be set before RX enable
12111
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12112
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
12113
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12114
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12115
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12116
    // prepare two packets of MAXFL length
12117
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12118
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
12119
    min_tmp = tmp[31:16];
12120
    st_data = 8'hAC;
12121
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
12122
    st_data = 8'h35;
12123
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
12124
    // check WB INT signal
12125
    if (wb_int !== 1'b0)
12126
    begin
12127
      test_fail("WB INT signal should not be set");
12128
      fail = fail + 1;
12129
    end
12130
 
12131
    // write to phy's control register for 10Mbps
12132
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
12133
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
12134
    speed = 10;
12135
 
12136
    i_length = (min_tmp - 4);
12137
    while (i_length <= (max_tmp - 4))
12138
    begin
12139
      // append CRC to packet
12140
      if (i_length[0] == 1'b0)
12141
        append_rx_crc (0, i_length, 1'b0, 1'b0);
12142
      else
12143
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
12144
      // choose generating carrier sense and collision
12145
      case (i_length[1:0])
12146
      2'h0: // Interrupt is generated
12147
      begin
12148
        // Reset_tx_bd nable interrupt generation
12149
        // unmask interrupts
12150
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12151
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12152
        // not detect carrier sense in FD and no collision
12153
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12154
        eth_phy.collision(0);
12155
      end
12156
      2'h1: // Interrupt is not generated
12157
      begin
12158
        // set_tx_bd enable interrupt generation
12159
        // mask interrupts
12160
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12161
        // detect carrier sense in FD and no collision
12162
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12163
        eth_phy.collision(0);
12164
      end
12165
      2'h2: // Interrupt is not generated
12166
      begin
12167
        // set_tx_bd disable the interrupt generation
12168
        // unmask interrupts
12169
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12170
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12171
        // not detect carrier sense in FD and set collision
12172
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12173
        eth_phy.collision(1);
12174
      end
12175
      default: // 2'h3: // Interrupt is not generated
12176
      begin
12177
        // set_tx_bd disable the interrupt generation
12178
        // mask interrupts
12179
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12180
        // detect carrier sense in FD and set collision
12181
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12182
        eth_phy.collision(1);
12183
      end
12184
      endcase
12185
      // first 8 frames are received with RX BD 0 (wrap bit on RX BD 0)
12186
      // number of all frames is 154 (146 without first 8)
12187
      if (num_of_frames < 8)
12188
      begin
12189
        case (i_length[1:0])
12190
        2'h0: // Interrupt is generated
12191
        begin
12192
          // enable interrupt generation
12193
          set_rx_bd(0, 0, 1'b1, (`MEMORY_BASE + i_length[1:0]));
12194
          // interrupts are unmasked
12195
        end
12196
        2'h1: // Interrupt is not generated
12197
        begin
12198
          // enable interrupt generation
12199
          set_rx_bd(0, 0, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12200
          // interrupts are masked
12201
        end
12202
        2'h2: // Interrupt is not generated
12203
        begin
12204
          // disable interrupt generation
12205
          set_rx_bd(0, 0, 1'b0, (`MEMORY_BASE + i_length[1:0]));
12206
          // interrupts are unmasked
12207
        end
12208
        default: // 2'h3: // Interrupt is not generated
12209
        begin
12210
          // disable interrupt generation
12211
          set_rx_bd(0, 0, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12212
          // interrupts are masked
12213
        end
12214
        endcase
12215
        // set wrap bit
12216
        set_rx_bd_wrap(0);
12217
      end
12218
      // after first 8 number of frames, 128 frames form RX BD 0 to 127 will be received
12219
      else if ((num_of_frames - 8) == 0)
12220
      begin
12221
        tmp_len = i_length; // length of frame
12222
        tmp_bd_num = 0; // RX BD number
12223
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
12224
        begin
12225
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
12226
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
12227
          if (tmp_len[0] == 0)
12228
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
12229
          else
12230
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
12231
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
12232
          if ((tmp_len + 4) < (min_tmp + 128))
12233
            tmp_len = tmp_len + 1;
12234
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12235
            tmp_len = 256;
12236
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12237
            tmp_len = tmp_len + 128;
12238
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
12239
            tmp_len = max_tmp - (4 + 16);
12240
          else if ((tmp_len + 4) >= (max_tmp - 16))
12241
            tmp_len = tmp_len + 1;
12242
          // set RX BD number
12243
          tmp_bd_num = tmp_bd_num + 1;
12244
        end
12245
        // set wrap bit
12246
        set_rx_bd_wrap(127);
12247
      end
12248
      // after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
12249
      else if ((num_of_frames - 8) == 20) // 128
12250
      begin
12251
        tmp_len = tmp_len; // length of frame remaines from previous settings
12252
        tmp_bd_num = 0; // TX BD number
12253
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
12254
        begin
12255
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
12256
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
12257
          if (tmp_len[0] == 0)
12258
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
12259
          else
12260
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
12261
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
12262
          if ((tmp_len + 4) < (min_tmp + 128))
12263
            tmp_len = tmp_len + 1;
12264
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12265
            tmp_len = 256;
12266
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12267
            tmp_len = tmp_len + 128;
12268
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
12269
            tmp_len = max_tmp - (4 + 16);
12270
          else if ((tmp_len + 4) >= (max_tmp - 16))
12271
            tmp_len = tmp_len + 1;
12272
          // set TX BD number
12273
          tmp_bd_num = tmp_bd_num + 1;
12274
        end
12275
      end
12276
      // set empty bit
12277
      if (num_of_frames < 8)
12278
        set_rx_bd_empty(0, 0);
12279
      else if ((num_of_frames - 8) < 128)
12280
        set_rx_bd_empty((num_of_frames - 8), (num_of_frames - 8));
12281
      else if ((num_of_frames - 136) < 19)
12282
        set_rx_bd_empty((num_of_frames - 136), (num_of_frames - 136));
12283
      // CHECK END OF RECEIVE
12284
      fork
12285
        begin
12286
          if (i_length[0] == 1'b0)
12287
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
12288
          else
12289
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
12290
          repeat(10) @(posedge mrx_clk);
12291
        end
12292
        begin
12293
          #1 check_rx_bd(num_of_bd, data);
12294
          if (i_length < min_tmp) // just first four
12295
          begin
12296
            while (data[15] === 1)
12297
            begin
12298
              #1 check_rx_bd(num_of_bd, data);
12299
              @(posedge wb_clk);
12300
            end
12301
            repeat (1) @(posedge wb_clk);
12302
          end
12303
          else
12304
          begin
12305
            wait (MRxDV === 1'b1); // start transmit
12306
            #1 check_rx_bd(num_of_bd, data);
12307
            if (data[15] !== 1)
12308
            begin
12309
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
12310
              fail = fail + 1;
12311
            end
12312
            wait (MRxDV === 1'b0); // end transmit
12313
            while (data[15] === 1)
12314
            begin
12315
              #1 check_rx_bd(num_of_bd, data);
12316
              @(posedge wb_clk);
12317
            end
12318
            repeat (1) @(posedge wb_clk);
12319
          end
12320
        end
12321
      join
12322
      // check length of a PACKET
12323
      if (data[31:16] != (i_length + 4))
12324
      begin
12325
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
12326
                        data[31:16], (i_length + 4));
12327
        test_fail("Wrong length of the packet out from PHY");
12328
        fail = fail + 1;
12329
      end
12330
      // checking in the following if statement is performed only for first and last 64 lengths
12331
      // check received RX packet data and CRC
12332
      if (i_length[0] == 1'b0)
12333
      begin
12334
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
12335
      end
12336
      else
12337
      begin
12338
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
12339
      end
12340
      if (tmp > 0)
12341
      begin
12342
        `TIME; $display("*E Wrong data of the received packet");
12343
        test_fail("Wrong data of the received packet");
12344
        fail = fail + 1;
12345
      end
12346
      // check WB INT signal
12347
      if (i_length[1:0] == 2'h0)
12348
      begin
12349
        if (wb_int !== 1'b1)
12350
        begin
12351
          `TIME; $display("*E WB INT signal should be set");
12352
          test_fail("WB INT signal should be set");
12353
          fail = fail + 1;
12354
        end
12355
      end
12356
      else
12357
      begin
12358
        if (wb_int !== 1'b0)
12359
        begin
12360
          `TIME; $display("*E WB INT signal should not be set");
12361
          test_fail("WB INT signal should not be set");
12362
          fail = fail + 1;
12363
        end
12364
      end
12365
      // check RX buffer descriptor of a packet
12366
      check_rx_bd(num_of_bd, data);
12367
      if (i_length[1] == 1'b0) // interrupt enabled
12368
      begin
12369
        if ( ((data[15:0] !== 16'h6000) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
12370
             ((data[15:0] !== 16'h4000) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
12371
        begin
12372
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12373
          test_fail("RX buffer descriptor status is not correct");
12374
          fail = fail + 1;
12375
        end
12376
      end
12377
      else // interrupt not enabled
12378
      begin
12379
        if ( ((data[15:0] !== 16'h2000)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
12380
             ((data[15:0] !== 16'h0000) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
12381
        begin
12382
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12383
          test_fail("RX buffer descriptor status is not correct");
12384
          fail = fail + 1;
12385
        end
12386
      end
12387
      // clear first half of 8 frames from RX buffer descriptor 0
12388
      if (num_of_frames < 4)
12389
        clear_rx_bd(num_of_bd, num_of_bd);
12390
      // clear BD with wrap bit
12391
      if (num_of_frames == 140)
12392
        clear_rx_bd(127, 127);
12393
      // check interrupts
12394
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12395
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
12396
      begin
12397
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
12398
        begin
12399
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
12400
          test_fail("Interrupt Receive Buffer was not set");
12401
          fail = fail + 1;
12402
        end
12403
        if ((data & (~`ETH_INT_RXB)) !== 0)
12404
        begin
12405
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
12406
          test_fail("Other interrupts (except Receive Buffer) were set");
12407
          fail = fail + 1;
12408
        end
12409
      end
12410
      else
12411
      begin
12412
        if (data !== 0)
12413
        begin
12414
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
12415
          test_fail("Any of interrupts (except Receive Buffer) was set");
12416
          fail = fail + 1;
12417
        end
12418
      end
12419
      // clear interrupts
12420
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12421
      // check WB INT signal
12422
      if (wb_int !== 1'b0)
12423
      begin
12424
        test_fail("WB INT signal should not be set");
12425
        fail = fail + 1;
12426
      end
12427
      // INTERMEDIATE DISPLAYS
12428
      if ((i_length + 4) == (min_tmp + 7))
12429
      begin
12430
        // starting length is min_tmp, ending length is (min_tmp + 128)
12431
        $display("    receive small packets is NOT selected");
12432
        $display("    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)");
12433
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
12434
                 min_tmp, (min_tmp + 7));
12435
        $display("    ->all packets were received on RX BD 0");
12436
        // reset receive small, remain the rest
12437
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12438
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12439
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12440
      end
12441
      else if ((i_length + 4) == (min_tmp + 128))
12442
      begin
12443
        // starting length is min_tmp, ending length is (min_tmp + 128)
12444
        $display("    receive small packets is NOT selected");
12445
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12446
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
12447
                 (min_tmp + 8), (min_tmp + 128));
12448
        $display("    ->packets were received on RX BD %0d to RX BD %0d respectively",
12449
                 1'b0, num_of_bd);
12450
        tmp_bd = num_of_bd + 1;
12451
        // set receive small, remain the rest
12452
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12453
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12454
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12455
      end
12456
      else if ((i_length + 4) == (max_tmp - 16))
12457
      begin
12458
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
12459
        $display("    receive small packets is selected");
12460
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12461
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
12462
                 (min_tmp + 64 + 128), tmp_data);
12463
        if (tmp_bd > num_of_bd)
12464
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
12465
                   tmp_bd, num_of_bd);
12466
        else
12467
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
12468
                   tmp_bd, num_of_bd);
12469
        tmp_bd = num_of_bd + 1;
12470
        // reset receive small, remain the rest
12471
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12472
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12473
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12474
      end
12475
      else if ((i_length + 4) == max_tmp)
12476
      begin
12477
        $display("    receive small packets is NOT selected");
12478
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12479
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
12480
                 (max_tmp - (4 + 16)), max_tmp);
12481
        if (tmp_bd > num_of_bd)
12482
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
12483
                   tmp_bd, num_of_bd);
12484
        else
12485
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
12486
                   tmp_bd, num_of_bd);
12487
      end
12488
      // set length (loop variable)
12489
      if ((i_length + 4) < (min_tmp + 128))
12490
        i_length = i_length + 1;
12491
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
12492
        i_length = 256;
12493
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
12494
      begin
12495
        i_length = i_length + 128;
12496
        tmp_data = i_length + 4; // last tmp_data is ending length
12497
      end
12498
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
12499
        i_length = max_tmp - (4 + 16);
12500
      else if ((i_length + 4) >= (max_tmp - 16))
12501
        i_length = i_length + 1;
12502
      else
12503
      begin
12504
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
12505
        #10 $stop;
12506
      end
12507
      // the number of frame transmitted
12508
      num_of_frames = num_of_frames + 1;
12509
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
12510
        num_of_bd = 0;
12511
      else
12512
        num_of_bd = num_of_bd + 1;
12513
    end
12514
    // disable RX
12515
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12516
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12517
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12518
    @(posedge wb_clk);
12519
    if(fail == 0)
12520
      test_ok;
12521
    else
12522
      fail = 0;
12523
  end
12524
 
12525
 
12526
  ////////////////////////////////////////////////////////////////////
12527
  ////                                                            ////
12528
  ////  Test receive packets form MINFL to MAXFL sizes at         ////
12529
  ////  maximum RX buffer decriptors ( 100Mbps ).                 ////
12530
  ////                                                            ////
12531
  ////////////////////////////////////////////////////////////////////
12532 243 tadejm
  if (test_num == 7) // 
12533 209 tadejm
  begin
12534 243 tadejm
    // TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )
12535
    test_name = "TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )";
12536
    `TIME; $display("  TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )");
12537 209 tadejm
 
12538
    // reset MAC registers
12539
    hard_reset;
12540
    // reset MAC and MII LOGIC with soft reset
12541
    reset_mac;
12542
    reset_mii;
12543
    // set wb slave response
12544
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
12545
 
12546
    max_tmp = 0;
12547
    min_tmp = 0;
12548
    num_of_frames = 0;
12549
    num_of_bd = 0;
12550
    // set maximum RX buffer descriptors (128) - must be set before RX enable
12551
    wbm_write(`ETH_TX_BD_NUM, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12552
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
12553
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12554
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12555
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12556
    // prepare two packets of MAXFL length
12557
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12558
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
12559
    min_tmp = tmp[31:16];
12560
    st_data = 8'hAC;
12561
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
12562
    st_data = 8'h35;
12563
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
12564
    // check WB INT signal
12565
    if (wb_int !== 1'b0)
12566
    begin
12567
      test_fail("WB INT signal should not be set");
12568
      fail = fail + 1;
12569
    end
12570
 
12571
    // write to phy's control register for 100Mbps
12572
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
12573
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
12574
    speed = 100;
12575
 
12576
    i_length = (min_tmp - 4);
12577
    while (i_length <= (max_tmp - 4))
12578
    begin
12579
      // append CRC to packet
12580
      if (i_length[0] == 1'b0)
12581
        append_rx_crc (0, i_length, 1'b0, 1'b0);
12582
      else
12583
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
12584
      // choose generating carrier sense and collision
12585
      case (i_length[1:0])
12586
      2'h0: // Interrupt is generated
12587
      begin
12588
        // Reset_tx_bd nable interrupt generation
12589
        // unmask interrupts
12590
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12591
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12592
        // not detect carrier sense in FD and no collision
12593
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12594
        eth_phy.collision(0);
12595
      end
12596
      2'h1: // Interrupt is not generated
12597
      begin
12598
        // set_tx_bd enable interrupt generation
12599
        // mask interrupts
12600
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12601
        // detect carrier sense in FD and no collision
12602
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12603
        eth_phy.collision(0);
12604
      end
12605
      2'h2: // Interrupt is not generated
12606
      begin
12607
        // set_tx_bd disable the interrupt generation
12608
        // unmask interrupts
12609
        wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
12610
                                 `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12611
        // not detect carrier sense in FD and set collision
12612
        eth_phy.no_carrier_sense_rx_fd_detect(0);
12613
        eth_phy.collision(1);
12614
      end
12615
      default: // 2'h3: // Interrupt is not generated
12616
      begin
12617
        // set_tx_bd disable the interrupt generation
12618
        // mask interrupts
12619
        wbm_write(`ETH_INT_MASK, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12620
        // detect carrier sense in FD and set collision
12621
        eth_phy.no_carrier_sense_rx_fd_detect(1);
12622
        eth_phy.collision(1);
12623
      end
12624
      endcase
12625
      // first 8 frames are received with RX BD 0 (wrap bit on RX BD 0)
12626
      // number of all frames is 154 (146 without first 8)
12627
      if (num_of_frames < 8)
12628
      begin
12629
        case (i_length[1:0])
12630
        2'h0: // Interrupt is generated
12631
        begin
12632
          // enable interrupt generation
12633
          set_rx_bd(0, 0, 1'b1, (`MEMORY_BASE + i_length[1:0]));
12634
          // interrupts are unmasked
12635
        end
12636
        2'h1: // Interrupt is not generated
12637
        begin
12638
          // enable interrupt generation
12639
          set_rx_bd(0, 0, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12640
          // interrupts are masked
12641
        end
12642
        2'h2: // Interrupt is not generated
12643
        begin
12644
          // disable interrupt generation
12645
          set_rx_bd(0, 0, 1'b0, (`MEMORY_BASE + i_length[1:0]));
12646
          // interrupts are unmasked
12647
        end
12648
        default: // 2'h3: // Interrupt is not generated
12649
        begin
12650
          // disable interrupt generation
12651
          set_rx_bd(0, 0, 1'b0, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
12652
          // interrupts are masked
12653
        end
12654
        endcase
12655
        // set wrap bit
12656
        set_rx_bd_wrap(0);
12657
      end
12658
      // after first 8 number of frames, 128 frames form RX BD 0 to 127 will be received
12659
      else if ((num_of_frames - 8) == 0)
12660
      begin
12661
        tmp_len = i_length; // length of frame
12662
        tmp_bd_num = 0; // RX BD number
12663
        while (tmp_bd_num < 128) // (tmp_len <= (max_tmp - 4)) - this is the last frame
12664
        begin
12665
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
12666
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
12667
          if (tmp_len[0] == 0)
12668
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
12669
          else
12670
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
12671
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
12672
          if ((tmp_len + 4) < (min_tmp + 128))
12673
            tmp_len = tmp_len + 1;
12674
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12675
            tmp_len = 256;
12676
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12677
            tmp_len = tmp_len + 128;
12678
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
12679
            tmp_len = max_tmp - (4 + 16);
12680
          else if ((tmp_len + 4) >= (max_tmp - 16))
12681
            tmp_len = tmp_len + 1;
12682
          // set RX BD number
12683
          tmp_bd_num = tmp_bd_num + 1;
12684
        end
12685
        // set wrap bit
12686
        set_rx_bd_wrap(127);
12687
      end
12688
      // after 128 + first 8 number of frames, 19 frames form RX BD 0 to 18 will be received
12689
      else if ((num_of_frames - 8) == 20) // 128
12690
      begin
12691
        tmp_len = tmp_len; // length of frame remaines from previous settings
12692
        tmp_bd_num = 0; // TX BD number
12693
        while (tmp_bd_num < 19) // (tmp_len <= (max_tmp - 4)) - this is the last frame
12694
        begin
12695
          // if i_length[1] == 0 then enable interrupt generation otherwise disable it
12696
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
12697
          if (tmp_len[0] == 0)
12698
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], (`MEMORY_BASE + tmp_len[1:0]));
12699
          else
12700
            set_rx_bd(tmp_bd_num, tmp_bd_num, !tmp_len[1], ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
12701
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
12702
          if ((tmp_len + 4) < (min_tmp + 128))
12703
            tmp_len = tmp_len + 1;
12704
          else if ( ((tmp_len + 4) == (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12705
            tmp_len = 256;
12706
          else if ( ((tmp_len + 4) > (min_tmp + 128)) && ((tmp_len + 4) <= (max_tmp - 256)) )
12707
            tmp_len = tmp_len + 128;
12708
          else if ( ((tmp_len + 4) > (max_tmp - 256)) && ((tmp_len + 4) < (max_tmp - 16)) )
12709
            tmp_len = max_tmp - (4 + 16);
12710
          else if ((tmp_len + 4) >= (max_tmp - 16))
12711
            tmp_len = tmp_len + 1;
12712
          // set TX BD number
12713
          tmp_bd_num = tmp_bd_num + 1;
12714
        end
12715
      end
12716
      // set empty bit
12717
      if (num_of_frames < 8)
12718
        set_rx_bd_empty(0, 0);
12719
      else if ((num_of_frames - 8) < 128)
12720
        set_rx_bd_empty((num_of_frames - 8), (num_of_frames - 8));
12721
      else if ((num_of_frames - 136) < 19)
12722
        set_rx_bd_empty((num_of_frames - 136), (num_of_frames - 136));
12723
      // CHECK END OF RECEIVE
12724
      fork
12725
        begin
12726
          if (i_length[0] == 1'b0)
12727
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
12728
          else
12729
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
12730
          repeat(10) @(posedge mrx_clk);
12731
        end
12732
        begin
12733
          #1 check_rx_bd(num_of_bd, data);
12734
          if (i_length < min_tmp) // just first four
12735
          begin
12736
            while (data[15] === 1)
12737
            begin
12738
              #1 check_rx_bd(num_of_bd, data);
12739
              @(posedge wb_clk);
12740
            end
12741
            repeat (1) @(posedge wb_clk);
12742
          end
12743
          else
12744
          begin
12745
            wait (MRxDV === 1'b1); // start transmit
12746
            #1 check_rx_bd(num_of_bd, data);
12747
            if (data[15] !== 1)
12748
            begin
12749
              test_fail("Wrong buffer descriptor's ready bit read out from MAC");
12750
              fail = fail + 1;
12751
            end
12752
            wait (MRxDV === 1'b0); // end transmit
12753
            while (data[15] === 1)
12754
            begin
12755
              #1 check_rx_bd(num_of_bd, data);
12756
              @(posedge wb_clk);
12757
            end
12758
            repeat (1) @(posedge wb_clk);
12759
          end
12760
        end
12761
      join
12762
      // check length of a PACKET
12763
      if (data[31:16] != (i_length + 4))
12764
      begin
12765
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
12766
                        data[31:16], (i_length + 4));
12767
        test_fail("Wrong length of the packet out from PHY");
12768
        fail = fail + 1;
12769
      end
12770
      // check received RX packet data and CRC
12771
      if (i_length[0] == 1'b0)
12772
      begin
12773
        check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
12774
      end
12775
      else
12776
      begin
12777
        check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
12778
      end
12779
      if (tmp > 0)
12780
      begin
12781
        `TIME; $display("*E Wrong data of the received packet");
12782
        test_fail("Wrong data of the received packet");
12783
        fail = fail + 1;
12784
      end
12785
      // check WB INT signal
12786
      if (i_length[1:0] == 2'h0)
12787
      begin
12788
        if (wb_int !== 1'b1)
12789
        begin
12790
          `TIME; $display("*E WB INT signal should be set");
12791
          test_fail("WB INT signal should be set");
12792
          fail = fail + 1;
12793
        end
12794
      end
12795
      else
12796
      begin
12797
        if (wb_int !== 1'b0)
12798
        begin
12799
          `TIME; $display("*E WB INT signal should not be set");
12800
          test_fail("WB INT signal should not be set");
12801
          fail = fail + 1;
12802
        end
12803
      end
12804
      // check RX buffer descriptor of a packet
12805
      check_rx_bd(num_of_bd, data);
12806
      if (i_length[1] == 1'b0) // interrupt enabled
12807
      begin
12808
        if ( ((data[15:0] !== 16'h6000) && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
12809
             ((data[15:0] !== 16'h4000) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
12810
        begin
12811
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12812
          test_fail("RX buffer descriptor status is not correct");
12813
          fail = fail + 1;
12814
        end
12815
      end
12816
      else // interrupt not enabled
12817
      begin
12818
        if ( ((data[15:0] !== 16'h2000)  && ((num_of_frames < 8) || ((num_of_frames - 8) == 127))) || // wrap bit
12819
             ((data[15:0] !== 16'h0000) && (num_of_frames >= 8) && ((num_of_frames - 8) != 127)) ) // without wrap bit
12820
        begin
12821
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h", data[15:0]);
12822
          test_fail("RX buffer descriptor status is not correct");
12823
          fail = fail + 1;
12824
        end
12825
      end
12826
      // clear first half of 8 frames from RX buffer descriptor 0
12827
      if (num_of_frames < 4)
12828
        clear_rx_bd(num_of_bd, num_of_bd);
12829
      // clear BD with wrap bit
12830
      if (num_of_frames == 140)
12831
        clear_rx_bd(127, 127);
12832
      // check interrupts
12833
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12834
      if ((i_length[1:0] == 2'h0) || (i_length[1:0] == 2'h1))
12835
      begin
12836
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
12837
        begin
12838
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
12839
          test_fail("Interrupt Receive Buffer was not set");
12840
          fail = fail + 1;
12841
        end
12842
        if ((data & (~`ETH_INT_RXB)) !== 0)
12843
        begin
12844
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
12845
          test_fail("Other interrupts (except Receive Buffer) were set");
12846
          fail = fail + 1;
12847
        end
12848
      end
12849
      else
12850
      begin
12851
        if (data !== 0)
12852
        begin
12853
          `TIME; $display("*E Any of interrupts (except Receive Buffer) was set, interrupt reg: %0h, len: %0h", data, i_length[1:0]);
12854
          test_fail("Any of interrupts (except Receive Buffer) was set");
12855
          fail = fail + 1;
12856
        end
12857
      end
12858
      // clear interrupts
12859
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12860
      // check WB INT signal
12861
      if (wb_int !== 1'b0)
12862
      begin
12863
        test_fail("WB INT signal should not be set");
12864
        fail = fail + 1;
12865
      end
12866
      // INTERMEDIATE DISPLAYS
12867
      if ((i_length + 4) == (min_tmp + 7))
12868
      begin
12869
        // starting length is min_tmp, ending length is (min_tmp + 128)
12870
        $display("    receive small packets is NOT selected");
12871
        $display("    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)");
12872
        $display("    ->packets with lengths from %0d (MINFL) to %0d are checked (length increasing by 1 byte)",
12873
                 min_tmp, (min_tmp + 7));
12874
        $display("    ->all packets were received on RX BD 0");
12875
        // reset receive small, remain the rest
12876
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12877
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12878
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12879
      end
12880
      else if ((i_length + 4) == (min_tmp + 128))
12881
      begin
12882
        // starting length is min_tmp, ending length is (min_tmp + 128)
12883
        $display("    receive small packets is NOT selected");
12884
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12885
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
12886
                 (min_tmp + 8), (min_tmp + 128));
12887
        $display("    ->packets were received on RX BD %0d to RX BD %0d respectively",
12888
                 1'b0, num_of_bd);
12889
        tmp_bd = num_of_bd + 1;
12890
        // set receive small, remain the rest
12891
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12892
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12893
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12894
      end
12895
      else if ((i_length + 4) == (max_tmp - 16))
12896
      begin
12897
        // starting length is for +128 longer than previous ending length, while ending length is tmp_data
12898
        $display("    receive small packets is selected");
12899
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12900
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 128 bytes)",
12901
                 (min_tmp + 64 + 128), tmp_data);
12902
        if (tmp_bd > num_of_bd)
12903
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
12904
                   tmp_bd, num_of_bd);
12905
        else
12906
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
12907
                   tmp_bd, num_of_bd);
12908
        tmp_bd = num_of_bd + 1;
12909
        // reset receive small, remain the rest
12910
        wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
12911
                  `ETH_MODER_PRO | `ETH_MODER_BRO,
12912
                  4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12913
      end
12914
      else if ((i_length + 4) == max_tmp)
12915
      begin
12916
        $display("    receive small packets is NOT selected");
12917
        $display("    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)");
12918
        $display("    ->packets with lengths from %0d to %0d (MAXFL) are checked (length increasing by 1 byte)",
12919
                 (max_tmp - (4 + 16)), max_tmp);
12920
        if (tmp_bd > num_of_bd)
12921
          $display("    ->packets were received from RX BD %0d to RX BD 127 and from RX BD 0 to RX BD %0d respectively",
12922
                   tmp_bd, num_of_bd);
12923
        else
12924
          $display("    ->packets were received from RX BD %0d to RX BD %0d respectively",
12925
                   tmp_bd, num_of_bd);
12926
      end
12927
      // set length (loop variable)
12928
      if ((i_length + 4) < (min_tmp + 128))
12929
        i_length = i_length + 1;
12930
      else if ( ((i_length + 4) == (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
12931
        i_length = 256;
12932
      else if ( ((i_length + 4) > (min_tmp + 128)) && ((i_length + 4) <= (max_tmp - 256)) )
12933
      begin
12934
        i_length = i_length + 128;
12935
        tmp_data = i_length + 4; // last tmp_data is ending length
12936
      end
12937
      else if ( ((i_length + 4) > (max_tmp - 256)) && ((i_length + 4) < (max_tmp - 16)) )
12938
        i_length = max_tmp - (4 + 16);
12939
      else if ((i_length + 4) >= (max_tmp - 16))
12940
        i_length = i_length + 1;
12941
      else
12942
      begin
12943
        $display("*E TESTBENCH ERROR - WRONG PARAMETERS IN TESTBENCH");
12944
        #10 $stop;
12945
      end
12946
      // the number of frame transmitted
12947
      num_of_frames = num_of_frames + 1;
12948
      if ((num_of_frames <= 8) || ((num_of_frames - 8) == 128))
12949
        num_of_bd = 0;
12950
      else
12951
        num_of_bd = num_of_bd + 1;
12952
    end
12953
    // disable RX
12954
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12955
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12956
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12957
    @(posedge wb_clk);
12958
    if(fail == 0)
12959
      test_ok;
12960
    else
12961
      fail = 0;
12962
  end
12963
 
12964
 
12965
  ////////////////////////////////////////////////////////////////////
12966
  ////                                                            ////
12967 243 tadejm
  ////  Test receive packets form 0 to (MINFL + 12) sizes at       ////
12968 209 tadejm
  ////  8 RX buffer decriptors ( 10Mbps ).                        ////
12969
  ////                                                            ////
12970
  ////////////////////////////////////////////////////////////////////
12971 243 tadejm
  if (test_num == 8) // 
12972 209 tadejm
  begin
12973 243 tadejm
    // TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )
12974
    test_name = "TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )";
12975
    `TIME; $display("  TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 10Mbps )");
12976 209 tadejm
 
12977
    // reset MAC registers
12978
    hard_reset;
12979
    // reset MAC and MII LOGIC with soft reset
12980
    reset_mac;
12981
    reset_mii;
12982
    // set wb slave response
12983
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
12984
 
12985
    max_tmp = 0;
12986
    min_tmp = 0;
12987
    // set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
12988
    wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12989
    // enable RX, set full-duplex mode, receive small, NO correct IFG
12990
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
12991
              `ETH_MODER_PRO | `ETH_MODER_BRO,
12992
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12993
    // prepare two packets of MAXFL length
12994
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
12995
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
12996
    min_tmp = tmp[31:16];
12997
    st_data = 8'hAC;
12998
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
12999
    st_data = 8'h35;
13000
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
13001
    // check WB INT signal
13002
    if (wb_int !== 1'b0)
13003
    begin
13004
      test_fail("WB INT signal should not be set");
13005
      fail = fail + 1;
13006
    end
13007 243 tadejm
    // unmask interrupts
13008
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
13009
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13010 209 tadejm
 
13011
    // write to phy's control register for 10Mbps
13012
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
13013
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
13014
    speed = 10;
13015
 
13016 243 tadejm
    frame_ended = 0;
13017
    num_of_frames = 0;// 0; // 10;
13018
    num_of_bd = 120;
13019
    i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
13020
    while ((i_length + 4) < 78) // (min_tmp - 4))
13021 209 tadejm
    begin
13022 243 tadejm
      // append CRC to packet
13023
      if ((i_length[0] == 1'b0) && (num_of_frames > 4))
13024
        append_rx_crc (0, i_length, 1'b0, 1'b0);
13025
      else if (num_of_frames > 4)
13026
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
13027 209 tadejm
      // choose generating carrier sense and collision
13028
      case (i_length[1:0])
13029 243 tadejm
      2'h0:
13030 209 tadejm
      begin
13031
        // not detect carrier sense in FD and no collision
13032 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13033 209 tadejm
        eth_phy.collision(0);
13034
      end
13035 243 tadejm
      2'h1:
13036 209 tadejm
      begin
13037
        // detect carrier sense in FD and no collision
13038 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13039 209 tadejm
        eth_phy.collision(0);
13040
      end
13041 243 tadejm
      2'h2:
13042 209 tadejm
      begin
13043
        // not detect carrier sense in FD and set collision
13044 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13045 209 tadejm
        eth_phy.collision(1);
13046
      end
13047 243 tadejm
      default: // 2'h3:
13048 209 tadejm
      begin
13049
        // detect carrier sense in FD and set collision
13050 243 tadejm
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13051 209 tadejm
        eth_phy.collision(1);
13052
      end
13053
      endcase
13054
      #1;
13055 243 tadejm
      // first 10 frames are received with RX BD 120 (wrap bit on RX BD 120)
13056 209 tadejm
      if (num_of_frames <= 9)
13057
      begin
13058 243 tadejm
        case (i_length[1:0])
13059
        2'h0: // Interrupt is generated
13060
        begin
13061
          // enable interrupt generation
13062
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13063
        end
13064
        2'h1: // Interrupt is generated
13065
        begin
13066
          // enable interrupt generation
13067
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13068
        end
13069
        2'h2: // Interrupt is generated
13070
        begin
13071
          // enable interrupt generation
13072
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13073
        end
13074
        default: // 2'h3: // Interrupt is generated
13075
        begin
13076
          // enable interrupt generation
13077
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13078
        end
13079
        endcase
13080 209 tadejm
        // set wrap bit
13081 243 tadejm
        set_rx_bd_wrap(120);
13082 209 tadejm
      end
13083 243 tadejm
      // 10 <= num_of_frames < 18 => wrap set to TX BD 123
13084 209 tadejm
      else if ((num_of_frames == 10) || (num_of_frames == 14))
13085
      begin
13086
        tmp_len = i_length; // length of frame
13087 243 tadejm
        tmp_bd_num = 120; // RX BD number
13088
        while (tmp_bd_num < 124) // 
13089 209 tadejm
        begin
13090
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13091
          if (tmp_len[0] == 0)
13092 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13093 209 tadejm
          else
13094 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13095
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13096 209 tadejm
          tmp_len = tmp_len + 1;
13097 243 tadejm
          // set RX BD number
13098 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13099
        end
13100
        // set wrap bit
13101 243 tadejm
        set_rx_bd_wrap(123);
13102 209 tadejm
      end
13103 243 tadejm
      // 18 <= num_of_frames < 28 => wrap set to RX BD 124
13104 209 tadejm
      else if ((num_of_frames == 18) || (num_of_frames == 23))
13105
      begin
13106
        tmp_len = i_length; // length of frame
13107 243 tadejm
        tmp_bd_num = 120; // RX BD number
13108
        while (tmp_bd_num < 125) // 
13109 209 tadejm
        begin
13110
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13111
          if (tmp_len[0] == 0)
13112 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13113 209 tadejm
          else
13114 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13115
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13116 209 tadejm
          tmp_len = tmp_len + 1;
13117 243 tadejm
          // set RX BD number
13118 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13119
        end
13120
        // set wrap bit
13121 243 tadejm
        set_rx_bd_wrap(124);
13122 209 tadejm
      end
13123 243 tadejm
      // 28 <= num_of_frames < 40 => wrap set to RX BD 125
13124 209 tadejm
      else if ((num_of_frames == 28) || (num_of_frames == 34))
13125
      begin
13126
        tmp_len = i_length; // length of frame
13127 243 tadejm
        tmp_bd_num = 120; // RX BD number
13128
        while (tmp_bd_num < 126) // 
13129 209 tadejm
        begin
13130
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13131
          if (tmp_len[0] == 0)
13132 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13133 209 tadejm
          else
13134 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13135
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13136 209 tadejm
          tmp_len = tmp_len + 1;
13137 243 tadejm
          // set RX BD number
13138 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13139
        end
13140
        // set wrap bit
13141 243 tadejm
        set_rx_bd_wrap(125);
13142 209 tadejm
      end
13143 243 tadejm
      // 40 <= num_of_frames < 54 => wrap set to RX BD 126
13144 209 tadejm
      else if ((num_of_frames == 40) || (num_of_frames == 47))
13145
      begin
13146
        tmp_len = i_length; // length of frame
13147 243 tadejm
        tmp_bd_num = 120; // RX BD number
13148
        while (tmp_bd_num < 127) // 
13149 209 tadejm
        begin
13150
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13151
          if (tmp_len[0] == 0)
13152 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13153 209 tadejm
          else
13154 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13155
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13156 209 tadejm
          tmp_len = tmp_len + 1;
13157 243 tadejm
          // set RX BD number
13158 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13159
        end
13160
        // set wrap bit
13161 243 tadejm
        set_rx_bd_wrap(126);
13162 209 tadejm
      end
13163 243 tadejm
      // 54 <= num_of_frames < 70 => wrap set to RX BD 127
13164 209 tadejm
      else if ((num_of_frames == 54) || (num_of_frames == 62))
13165
      begin
13166
        tmp_len = i_length; // length of frame
13167 243 tadejm
        tmp_bd_num = 120; // RX BD number
13168
        while (tmp_bd_num < 128) // 
13169 209 tadejm
        begin
13170
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13171
          if (tmp_len[0] == 0)
13172 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13173 209 tadejm
          else
13174 243 tadejm
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13175
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13176 209 tadejm
          tmp_len = tmp_len + 1;
13177 243 tadejm
          // set RX BD number
13178 209 tadejm
          tmp_bd_num = tmp_bd_num + 1;
13179
        end
13180
        // set wrap bit
13181 243 tadejm
        set_rx_bd_wrap(127);
13182 209 tadejm
      end
13183 243 tadejm
      // 70 <= num_of_frames < 78 => wrap set to RX BD 127
13184
      else if (num_of_frames == 70)
13185
      begin
13186
        tmp_len = i_length; // length of frame
13187
        tmp_bd_num = 120; // RX BD number
13188
        while (tmp_bd_num < 128) // 
13189
        begin
13190
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13191
          if (tmp_len[0] == 0)
13192
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13193
          else
13194
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13195
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13196
          tmp_len = tmp_len + 1;
13197
          // set RX BD number
13198
          tmp_bd_num = tmp_bd_num + 1;
13199
        end
13200
        // set wrap bit
13201
        set_rx_bd_wrap(127);
13202
      end
13203 209 tadejm
      #1;
13204 243 tadejm
      // SET empty bit
13205 209 tadejm
      if (num_of_frames < 10)
13206 243 tadejm
        set_rx_bd_empty(120, 120);
13207 209 tadejm
      else if (num_of_frames < 14)
13208 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 10), (120 + num_of_frames - 10));
13209 209 tadejm
      else if (num_of_frames < 18)
13210 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 14), (120 + num_of_frames - 14));
13211 209 tadejm
      else if (num_of_frames < 23)
13212 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 18), (120 + num_of_frames - 18));
13213 209 tadejm
      else if (num_of_frames < 28)
13214 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 23), (120 + num_of_frames - 23));
13215 209 tadejm
      else if (num_of_frames < 34)
13216 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 28), (120 + num_of_frames - 28));
13217 209 tadejm
      else if (num_of_frames < 40)
13218 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 34), (120 + num_of_frames - 34));
13219 209 tadejm
      else if (num_of_frames < 47)
13220 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 40), (120 + num_of_frames - 40));
13221 209 tadejm
      else if (num_of_frames < 54)
13222 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 47), (120 + num_of_frames - 47));
13223 209 tadejm
      else if (num_of_frames < 62)
13224 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 54), (120 + num_of_frames - 54));
13225 209 tadejm
      else if (num_of_frames < 70)
13226 243 tadejm
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
13227
      else if (num_of_frames < 78)
13228
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
13229
      // CHECK END OF RECEIVE
13230 252 tadejm
      // receive just preamble between some packets
13231
      if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
13232
      begin
13233
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
13234
        @(posedge mrx_clk);
13235
        wait (MRxDV === 1'b0); // end receive
13236
        repeat(10) @(posedge mrx_clk);
13237
        repeat(15) @(posedge wb_clk);
13238
      end
13239
      // receiving frames and checking end of them
13240 243 tadejm
      frame_ended = 0;
13241
      check_frame = 0;
13242 209 tadejm
      fork
13243
        begin
13244 243 tadejm
          if (i_length[0] == 1'b0)
13245
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
13246
          else
13247
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
13248
          repeat(10) @(posedge mrx_clk);
13249
        end
13250
        begin: fr_end1
13251
          wait (MRxDV === 1'b1); // start receive
13252
          #1 check_rx_bd(num_of_bd, data);
13253
          if (data[15] !== 1)
13254 209 tadejm
          begin
13255 243 tadejm
            test_fail("Wrong buffer descriptor's empty bit read out from MAC");
13256
            fail = fail + 1;
13257 209 tadejm
          end
13258 243 tadejm
          wait (MRxDV === 1'b0); // end receive
13259
          while ((data[15] === 1) && (check_frame == 0))
13260
          begin
13261
            #1 check_rx_bd(num_of_bd, data);
13262
            @(posedge wb_clk);
13263
          end
13264
          if (data[15] === 0)
13265
            frame_ended = 1;
13266
          repeat (1) @(posedge wb_clk);
13267 209 tadejm
        end
13268 243 tadejm
        begin
13269
          wait (MRxDV === 1'b1); // start receive
13270
          wait (MRxDV === 1'b0); // end receive
13271
          repeat(10) @(posedge mrx_clk);
13272
          repeat(15) @(posedge wb_clk);
13273
          check_frame = 1;
13274
        end
13275
      join
13276
      // check length of a PACKET
13277
      if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
13278
           ((data[31:16] != 0) && (num_of_frames < 3)) )
13279
      begin
13280
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
13281
                        data[31:16], (i_length + 4));
13282
        test_fail("Wrong length of the packet out from PHY");
13283
        fail = fail + 1;
13284
      end
13285
      // check received RX packet data and CRC
13286
      if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
13287
      begin                                           // CRC has 4 bytes for itself
13288
        if (i_length[0] == 1'b0)
13289
        begin
13290
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
13291
        end
13292 209 tadejm
        else
13293
        begin
13294 243 tadejm
          check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
13295 209 tadejm
        end
13296 243 tadejm
        if (tmp > 0)
13297
        begin
13298
          `TIME; $display("*E Wrong data of the received packet");
13299
          test_fail("Wrong data of the received packet");
13300
          fail = fail + 1;
13301
        end
13302 209 tadejm
      end
13303 243 tadejm
      // check WB INT signal
13304
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
13305
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
13306
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
13307
        begin
13308
          `TIME; $display("*E WB INT signal should be set");
13309
          test_fail("WB INT signal should be set");
13310
          fail = fail + 1;
13311
        end
13312
      end
13313
      else
13314
      begin
13315
        if (wb_int !== 1'b0)
13316
        begin
13317
          `TIME; $display("*E WB INT signal should not be set");
13318
          test_fail("WB INT signal should not be set");
13319
          fail = fail + 1;
13320
        end
13321
      end
13322
      // check RX buffer descriptor of a packet
13323 254 mohor
      // check RX buffer descriptor of a packet
13324 243 tadejm
      if (num_of_frames >= min_tmp)
13325
      begin
13326 254 mohor
        if ( (data[15:0] !== 16'h6080) && // wrap bit
13327
             (data[15:0] !== 16'h4080) ) // without wrap bit
13328 243 tadejm
        begin
13329
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13330
          test_fail("RX buffer descriptor status is not correct");
13331
          fail = fail + 1;
13332
        end
13333
      end
13334 254 mohor
      else if (num_of_frames > 6)
13335 243 tadejm
      begin
13336 254 mohor
        if ( (data[15:0] !== 16'h6084) && // wrap bit
13337
             (data[15:0] !== 16'h4084) ) // without wrap bit
13338
        begin
13339
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13340
          test_fail("RX buffer descriptor status is not correct");
13341
          fail = fail + 1;
13342
        end
13343
      end
13344
      else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
13345
      begin
13346 243 tadejm
        if ( (data[15:0] !== 16'h6004) && // wrap bit
13347
             (data[15:0] !== 16'h4004) ) // without wrap bit
13348
        begin
13349
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13350
          test_fail("RX buffer descriptor status is not correct");
13351
          fail = fail + 1;
13352
        end
13353
      end
13354 254 mohor
      else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
13355 243 tadejm
      begin
13356
        if ( (data[15:0] !== 16'h6006) && // wrap bit
13357
             (data[15:0] !== 16'h4006) ) // without wrap bit
13358
        begin
13359
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13360
          test_fail("RX buffer descriptor status is not correct");
13361
          fail = fail + 1;
13362
        end
13363
      end
13364
      else
13365
      begin
13366
        if (data[15] !== 1'b1)
13367
        begin
13368
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13369
          test_fail("RX buffer descriptor status is not correct");
13370
          fail = fail + 1;
13371
        end
13372
      end
13373
      // check interrupts
13374
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13375 209 tadejm
      if (num_of_frames >= 5)
13376
      begin
13377 243 tadejm
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
13378 209 tadejm
        begin
13379 243 tadejm
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
13380
          test_fail("Interrupt Receive Buffer was not set");
13381
          fail = fail + 1;
13382 209 tadejm
        end
13383 243 tadejm
        if ((data & (~`ETH_INT_RXB)) !== 0)
13384 209 tadejm
        begin
13385 243 tadejm
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
13386
          test_fail("Other interrupts (except Receive Buffer) were set");
13387
          fail = fail + 1;
13388 209 tadejm
        end
13389 243 tadejm
      end
13390
      else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
13391
      begin
13392
        if (data) // Checking if any interrupt is pending)
13393 209 tadejm
        begin
13394 243 tadejm
          `TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
13395
          test_fail("Interrupts were set");
13396
          fail = fail + 1;
13397
        end
13398
      end
13399
      else
13400
      begin
13401
        if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
13402
        begin
13403
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
13404
          test_fail("Interrupt Receive Buffer Error was not set");
13405
          fail = fail + 1;
13406
        end
13407
        if ((data & (~`ETH_INT_RXE)) !== 0)
13408
        begin
13409
          `TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
13410
          test_fail("Other interrupts (except Receive Buffer Error) were set");
13411
          fail = fail + 1;
13412
        end
13413
      end
13414
      // clear interrupts
13415
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13416
      // check WB INT signal
13417
      if (wb_int !== 1'b0)
13418
      begin
13419
        test_fail("WB INT signal should not be set");
13420
        fail = fail + 1;
13421
      end
13422
      // INTERMEDIATE DISPLAYS
13423
      if (num_of_frames == 3)
13424
      begin
13425
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
13426
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
13427
                 0, 3);
13428
      end
13429
      else if (num_of_frames == 9)
13430
      begin
13431
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
13432
        $display("    ->packet with length 4 is not received (length increasing by 1 byte)");
13433
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13434
                 5, 9);
13435
      end
13436
      else if (num_of_frames == 17)
13437
      begin
13438
        $display("    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
13439
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13440
                 10, 17);
13441
      end
13442
      else if (num_of_frames == 27)
13443
      begin
13444
        $display("    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
13445
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13446
                 18, 27);
13447
      end
13448
      else if (num_of_frames == 40)
13449
      begin
13450
        $display("    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
13451
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13452
                 28, 40);
13453
      end
13454
      else if (num_of_frames == 54)
13455
      begin
13456
        $display("    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
13457
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13458
                 41, 54);
13459
      end
13460
      else if (num_of_frames == 69)
13461
      begin
13462
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13463
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13464
                 55, 69);
13465
      end
13466
      else if (num_of_frames == 69)
13467
      begin
13468
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13469
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13470
                 55, 69);
13471
      end
13472
      else if (num_of_frames == 77)
13473
      begin
13474
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13475
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13476
                 70, 77);
13477
      end
13478
      // set length (loop variable)
13479
      i_length = i_length + 1;
13480
      // the number of frame transmitted
13481
      num_of_frames = num_of_frames + 1;
13482
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
13483
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
13484
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
13485
          (num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
13486
        num_of_bd = 120;
13487
      else
13488
        num_of_bd = num_of_bd + 1;
13489
    end
13490
    // disable RX
13491
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
13492
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13493
    @(posedge wb_clk);
13494
    if(fail == 0)
13495
      test_ok;
13496
    else
13497
      fail = 0;
13498
  end
13499
 
13500
 
13501
  ////////////////////////////////////////////////////////////////////
13502
  ////                                                            ////
13503
  ////  Test receive packets form 0 to (MINFL + 12) sizes at      ////
13504
  ////  8 RX buffer decriptors ( 100Mbps ).                       ////
13505
  ////                                                            ////
13506
  ////////////////////////////////////////////////////////////////////
13507
  if (test_num == 9) // 
13508
  begin
13509
    // TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )
13510
    test_name = "TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )";
13511
    `TIME; $display("  TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 TX BD ( 100Mbps )");
13512
 
13513
    // reset MAC registers
13514
    hard_reset;
13515
    // reset MAC and MII LOGIC with soft reset
13516
    reset_mac;
13517
    reset_mii;
13518
    // set wb slave response
13519
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
13520
 
13521
    max_tmp = 0;
13522
    min_tmp = 0;
13523
    // set 8 RX buffer descriptors (120 - 127) - must be set before RX enable
13524
    wbm_write(`ETH_TX_BD_NUM, 32'h78, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13525
    // enable RX, set full-duplex mode, receive small, NO correct IFG
13526
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
13527
              `ETH_MODER_PRO | `ETH_MODER_BRO,
13528
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13529
    // prepare two packets of MAXFL length
13530
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13531
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
13532
    min_tmp = tmp[31:16];
13533
    st_data = 8'hAC;
13534
    set_rx_packet(0, (max_tmp - 4), 1'b0, 48'h0102_0304_0506, 48'h0708_090A_0B0C, 16'h0D0E, st_data); // length without CRC
13535
    st_data = 8'h35;
13536
    set_rx_packet((max_tmp), (max_tmp - 4), 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
13537
    // check WB INT signal
13538
    if (wb_int !== 1'b0)
13539
    begin
13540
      test_fail("WB INT signal should not be set");
13541
      fail = fail + 1;
13542
    end
13543
    // unmask interrupts
13544
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
13545
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13546
 
13547
    // write to phy's control register for 100Mbps
13548
    #Tp eth_phy.control_bit14_10 = 5'b01000; // bit 13 set - speed 100
13549
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset - (10/100), bit 8 set - FD
13550
    speed = 100;
13551
 
13552
    frame_ended = 0;
13553 252 tadejm
    num_of_frames = 0;// 0; // 10;
13554 243 tadejm
    num_of_bd = 120;
13555
    i_length = 0 - 4;// (0 - 4); // 6; // 4 less due to CRC
13556
    while ((i_length + 4) < 78) // (min_tmp - 4))
13557
    begin
13558
      // append CRC to packet
13559 252 tadejm
      if ((i_length[0] == 1'b0) && (num_of_frames > 4))
13560 243 tadejm
        append_rx_crc (0, i_length, 1'b0, 1'b0);
13561 252 tadejm
      else if (num_of_frames > 4)
13562 243 tadejm
        append_rx_crc (max_tmp, i_length, 1'b0, 1'b0);
13563
      // choose generating carrier sense and collision
13564
      case (i_length[1:0])
13565
      2'h0:
13566
      begin
13567
        // not detect carrier sense in FD and no collision
13568
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13569
        eth_phy.collision(0);
13570
      end
13571
      2'h1:
13572
      begin
13573
        // detect carrier sense in FD and no collision
13574
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13575
        eth_phy.collision(0);
13576
      end
13577
      2'h2:
13578
      begin
13579
        // not detect carrier sense in FD and set collision
13580
        eth_phy.no_carrier_sense_rx_fd_detect(0);
13581
        eth_phy.collision(1);
13582
      end
13583
      default: // 2'h3:
13584
      begin
13585
        // detect carrier sense in FD and set collision
13586
        eth_phy.no_carrier_sense_rx_fd_detect(1);
13587
        eth_phy.collision(1);
13588
      end
13589
      endcase
13590
      #1;
13591
      // first 10 frames are received with RX BD 120 (wrap bit on RX BD 120)
13592
      if (num_of_frames <= 9)
13593
      begin
13594
        case (i_length[1:0])
13595
        2'h0: // Interrupt is generated
13596
        begin
13597
          // enable interrupt generation
13598
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13599
        end
13600
        2'h1: // Interrupt is generated
13601
        begin
13602
          // enable interrupt generation
13603
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13604
        end
13605
        2'h2: // Interrupt is generated
13606
        begin
13607
          // enable interrupt generation
13608
          set_rx_bd(120, 120, 1'b1, (`MEMORY_BASE + i_length[1:0]));
13609
        end
13610
        default: // 2'h3: // Interrupt is generated
13611
        begin
13612
          // enable interrupt generation
13613
          set_rx_bd(120, 120, 1'b1, ((`MEMORY_BASE + i_length[1:0]) + max_tmp));
13614
        end
13615
        endcase
13616
        // set wrap bit
13617
        set_rx_bd_wrap(120);
13618
      end
13619
      // 10 <= num_of_frames < 18 => wrap set to TX BD 123
13620
      else if ((num_of_frames == 10) || (num_of_frames == 14))
13621
      begin
13622
        tmp_len = i_length; // length of frame
13623
        tmp_bd_num = 120; // RX BD number
13624
        while (tmp_bd_num < 124) // 
13625
        begin
13626
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13627
          if (tmp_len[0] == 0)
13628
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13629
          else
13630
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13631
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13632
          tmp_len = tmp_len + 1;
13633
          // set RX BD number
13634
          tmp_bd_num = tmp_bd_num + 1;
13635
        end
13636
        // set wrap bit
13637
        set_rx_bd_wrap(123);
13638
      end
13639
      // 18 <= num_of_frames < 28 => wrap set to RX BD 124
13640
      else if ((num_of_frames == 18) || (num_of_frames == 23))
13641
      begin
13642
        tmp_len = i_length; // length of frame
13643
        tmp_bd_num = 120; // RX BD number
13644
        while (tmp_bd_num < 125) // 
13645
        begin
13646
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13647
          if (tmp_len[0] == 0)
13648
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13649
          else
13650
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13651
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13652
          tmp_len = tmp_len + 1;
13653
          // set RX BD number
13654
          tmp_bd_num = tmp_bd_num + 1;
13655
        end
13656
        // set wrap bit
13657
        set_rx_bd_wrap(124);
13658
      end
13659
      // 28 <= num_of_frames < 40 => wrap set to RX BD 125
13660
      else if ((num_of_frames == 28) || (num_of_frames == 34))
13661
      begin
13662
        tmp_len = i_length; // length of frame
13663
        tmp_bd_num = 120; // RX BD number
13664
        while (tmp_bd_num < 126) // 
13665
        begin
13666
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13667
          if (tmp_len[0] == 0)
13668
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13669
          else
13670
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13671
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13672
          tmp_len = tmp_len + 1;
13673
          // set RX BD number
13674
          tmp_bd_num = tmp_bd_num + 1;
13675
        end
13676
        // set wrap bit
13677
        set_rx_bd_wrap(125);
13678
      end
13679
      // 40 <= num_of_frames < 54 => wrap set to RX BD 126
13680
      else if ((num_of_frames == 40) || (num_of_frames == 47))
13681
      begin
13682
        tmp_len = i_length; // length of frame
13683
        tmp_bd_num = 120; // RX BD number
13684
        while (tmp_bd_num < 127) // 
13685
        begin
13686
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13687
          if (tmp_len[0] == 0)
13688
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13689
          else
13690
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13691
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13692
          tmp_len = tmp_len + 1;
13693
          // set RX BD number
13694
          tmp_bd_num = tmp_bd_num + 1;
13695
        end
13696
        // set wrap bit
13697
        set_rx_bd_wrap(126);
13698
      end
13699
      // 54 <= num_of_frames < 70 => wrap set to RX BD 127
13700
      else if ((num_of_frames == 54) || (num_of_frames == 62))
13701
      begin
13702
        tmp_len = i_length; // length of frame
13703
        tmp_bd_num = 120; // RX BD number
13704
        while (tmp_bd_num < 128) // 
13705
        begin
13706
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13707
          if (tmp_len[0] == 0)
13708
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13709
          else
13710
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13711
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13712
          tmp_len = tmp_len + 1;
13713
          // set RX BD number
13714
          tmp_bd_num = tmp_bd_num + 1;
13715
        end
13716
        // set wrap bit
13717
        set_rx_bd_wrap(127);
13718
      end
13719
      // 70 <= num_of_frames < 78 => wrap set to RX BD 127
13720
      else if (num_of_frames == 70)
13721
      begin
13722
        tmp_len = i_length; // length of frame
13723
        tmp_bd_num = 120; // RX BD number
13724
        while (tmp_bd_num < 128) // 
13725
        begin
13726
          // if i_length[0] == 0 then base address is `MEMORY_BASE otherwise it is `MEMORY_BASE + max_tmp
13727
          if (tmp_len[0] == 0)
13728
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, (`MEMORY_BASE + tmp_len[1:0]));
13729
          else
13730
            set_rx_bd(tmp_bd_num, tmp_bd_num, 1'b1, ((`MEMORY_BASE + tmp_len[1:0]) + max_tmp));
13731
          // set length (loop variable) - THE SAME AS AT THE END OF THIS TASK !!!
13732
          tmp_len = tmp_len + 1;
13733
          // set RX BD number
13734
          tmp_bd_num = tmp_bd_num + 1;
13735
        end
13736
        // set wrap bit
13737
        set_rx_bd_wrap(127);
13738
      end
13739
      #1;
13740
      // SET empty bit
13741
      if (num_of_frames < 10)
13742
        set_rx_bd_empty(120, 120);
13743
      else if (num_of_frames < 14)
13744
        set_rx_bd_empty((120 + num_of_frames - 10), (120 + num_of_frames - 10));
13745
      else if (num_of_frames < 18)
13746
        set_rx_bd_empty((120 + num_of_frames - 14), (120 + num_of_frames - 14));
13747
      else if (num_of_frames < 23)
13748
        set_rx_bd_empty((120 + num_of_frames - 18), (120 + num_of_frames - 18));
13749
      else if (num_of_frames < 28)
13750
        set_rx_bd_empty((120 + num_of_frames - 23), (120 + num_of_frames - 23));
13751
      else if (num_of_frames < 34)
13752
        set_rx_bd_empty((120 + num_of_frames - 28), (120 + num_of_frames - 28));
13753
      else if (num_of_frames < 40)
13754
        set_rx_bd_empty((120 + num_of_frames - 34), (120 + num_of_frames - 34));
13755
      else if (num_of_frames < 47)
13756
        set_rx_bd_empty((120 + num_of_frames - 40), (120 + num_of_frames - 40));
13757
      else if (num_of_frames < 54)
13758
        set_rx_bd_empty((120 + num_of_frames - 47), (120 + num_of_frames - 47));
13759
      else if (num_of_frames < 62)
13760
        set_rx_bd_empty((120 + num_of_frames - 54), (120 + num_of_frames - 54));
13761
      else if (num_of_frames < 70)
13762
        set_rx_bd_empty((120 + num_of_frames - 62), (120 + num_of_frames - 62));
13763
      else if (num_of_frames < 78)
13764
        set_rx_bd_empty((120 + num_of_frames - 70), (120 + num_of_frames - 70));
13765
      // CHECK END OF RECEIVE
13766 252 tadejm
      // receive just preamble between some packets
13767
      if ((num_of_frames == 0) || (num_of_frames == 4) || (num_of_frames == 9))
13768
      begin
13769
        #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h6, 8'h55, 0, 0, 1'b0);
13770
        @(posedge mrx_clk);
13771
        wait (MRxDV === 1'b0); // end receive
13772
        repeat(10) @(posedge mrx_clk);
13773
        repeat(15) @(posedge wb_clk);
13774
      end
13775
      // receiving frames and checking end of them
13776 243 tadejm
      frame_ended = 0;
13777
      check_frame = 0;
13778
      fork
13779
        begin
13780
          if (i_length[0] == 1'b0)
13781
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, (i_length + 4), 1'b0);
13782
          else
13783
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, max_tmp, (i_length + 4), 1'b0);
13784
          repeat(10) @(posedge mrx_clk);
13785
        end
13786 254 mohor
        begin: fr_end2
13787 243 tadejm
          wait (MRxDV === 1'b1); // start receive
13788
          #1 check_rx_bd(num_of_bd, data);
13789
          if (data[15] !== 1)
13790 209 tadejm
          begin
13791 243 tadejm
            test_fail("Wrong buffer descriptor's empty bit read out from MAC");
13792 209 tadejm
            fail = fail + 1;
13793
          end
13794 243 tadejm
          wait (MRxDV === 1'b0); // end receive
13795
          while ((data[15] === 1) && (check_frame == 0))
13796
          begin
13797
            #1 check_rx_bd(num_of_bd, data);
13798
            @(posedge wb_clk);
13799
          end
13800
          if (data[15] === 0)
13801
            frame_ended = 1;
13802
          repeat (1) @(posedge wb_clk);
13803 209 tadejm
        end
13804
        begin
13805 243 tadejm
          wait (MRxDV === 1'b1); // start receive
13806
          wait (MRxDV === 1'b0); // end receive
13807
          repeat(10) @(posedge mrx_clk);
13808
          repeat(15) @(posedge wb_clk);
13809
          check_frame = 1;
13810 209 tadejm
        end
13811 243 tadejm
      join
13812
      // check length of a PACKET
13813 252 tadejm
      if ( ((data[31:16] != (i_length + 4)) && (num_of_frames >= 3)) ||
13814
           ((data[31:16] != 0) && (num_of_frames < 3)) )
13815 243 tadejm
      begin
13816
        `TIME; $display("*E Wrong length of the packet out from PHY (%0d instead of %0d)",
13817
                        data[31:16], (i_length + 4));
13818
        test_fail("Wrong length of the packet out from PHY");
13819
        fail = fail + 1;
13820
      end
13821
      // check received RX packet data and CRC
13822 252 tadejm
      if ((frame_ended == 1) && (num_of_frames >= 5)) // 5 bytes is minimum size without CRC error, since
13823
      begin                                           // CRC has 4 bytes for itself
13824 243 tadejm
        if (i_length[0] == 1'b0)
13825 209 tadejm
        begin
13826 243 tadejm
          check_rx_packet(0, (`MEMORY_BASE + i_length[1:0]), (i_length + 4), 1'b0, 1'b0, tmp);
13827 209 tadejm
        end
13828 243 tadejm
        else
13829 209 tadejm
        begin
13830 243 tadejm
          check_rx_packet(max_tmp, ((`MEMORY_BASE + i_length[1:0]) + max_tmp), (i_length + 4), 1'b0, 1'b0, tmp);
13831 209 tadejm
        end
13832
        if (tmp > 0)
13833
        begin
13834 243 tadejm
          `TIME; $display("*E Wrong data of the received packet");
13835
          test_fail("Wrong data of the received packet");
13836 209 tadejm
          fail = fail + 1;
13837
        end
13838
      end
13839
      // check WB INT signal
13840 252 tadejm
      if (num_of_frames >= 3) // Frames smaller than 3 are not received.
13841
      begin                   // Frames greater then 5 always cause an interrupt (Frame received)
13842
        if (wb_int !== 1'b1)  // Frames with length 3 or 4 always cause an interrupt (CRC error)
13843 209 tadejm
        begin
13844
          `TIME; $display("*E WB INT signal should be set");
13845
          test_fail("WB INT signal should be set");
13846
          fail = fail + 1;
13847
        end
13848
      end
13849 252 tadejm
      else
13850 209 tadejm
      begin
13851
        if (wb_int !== 1'b0)
13852
        begin
13853
          `TIME; $display("*E WB INT signal should not be set");
13854
          test_fail("WB INT signal should not be set");
13855
          fail = fail + 1;
13856
        end
13857
      end
13858 243 tadejm
      // check RX buffer descriptor of a packet
13859
      if (num_of_frames >= min_tmp)
13860
      begin
13861 254 mohor
        if ( (data[15:0] !== 16'h6080) && // wrap bit
13862
             (data[15:0] !== 16'h4080) ) // without wrap bit
13863 209 tadejm
        begin
13864 243 tadejm
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13865
          test_fail("RX buffer descriptor status is not correct");
13866
          fail = fail + 1;
13867 209 tadejm
        end
13868 243 tadejm
      end
13869 254 mohor
      else if (num_of_frames > 6)
13870 243 tadejm
      begin
13871 254 mohor
        if ( (data[15:0] !== 16'h6084) && // wrap bit
13872
             (data[15:0] !== 16'h4084) ) // without wrap bit
13873
        begin
13874
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13875
          test_fail("RX buffer descriptor status is not correct");
13876
          fail = fail + 1;
13877
        end
13878
      end
13879
      else if (num_of_frames > 4) // MAC does not recognize Dest. ADDR. for lengths 5, 6 => no MISS
13880
      begin
13881 243 tadejm
        if ( (data[15:0] !== 16'h6004) && // wrap bit
13882
             (data[15:0] !== 16'h4004) ) // without wrap bit
13883 209 tadejm
        begin
13884 243 tadejm
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13885
          test_fail("RX buffer descriptor status is not correct");
13886
          fail = fail + 1;
13887 209 tadejm
        end
13888
      end
13889 254 mohor
      else if (num_of_frames > 2) // MAC does not recognize Dest. ADDR. for length 3, 4 => no MISS, CRC ERROR
13890 243 tadejm
      begin
13891
        if ( (data[15:0] !== 16'h6006) && // wrap bit
13892
             (data[15:0] !== 16'h4006) ) // without wrap bit
13893
        begin
13894
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13895
          test_fail("RX buffer descriptor status is not correct");
13896
          fail = fail + 1;
13897
        end
13898
      end
13899 209 tadejm
      else
13900
      begin
13901
        if (data[15] !== 1'b1)
13902
        begin
13903 243 tadejm
          `TIME; $display("*E RX buffer descriptor status is not correct: %0h - len: %0d", data[15:0], num_of_frames);
13904
          test_fail("RX buffer descriptor status is not correct");
13905 209 tadejm
          fail = fail + 1;
13906
        end
13907
      end
13908
      // check interrupts
13909
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13910 252 tadejm
      if (num_of_frames >= 5)
13911 209 tadejm
      begin
13912 252 tadejm
        if ((data & `ETH_INT_RXB) !== `ETH_INT_RXB)
13913 209 tadejm
        begin
13914 243 tadejm
          `TIME; $display("*E Interrupt Receive Buffer was not set, interrupt reg: %0h", data);
13915
          test_fail("Interrupt Receive Buffer was not set");
13916 209 tadejm
          fail = fail + 1;
13917
        end
13918 243 tadejm
        if ((data & (~`ETH_INT_RXB)) !== 0)
13919 209 tadejm
        begin
13920 243 tadejm
          `TIME; $display("*E Other interrupts (except Receive Buffer) were set, interrupt reg: %0h", data);
13921
          test_fail("Other interrupts (except Receive Buffer) were set");
13922 209 tadejm
          fail = fail + 1;
13923
        end
13924
      end
13925 252 tadejm
      else if ((num_of_frames < 3)) // Frames smaller than 3 are not received.
13926
      begin
13927
        if (data) // Checking if any interrupt is pending)
13928
        begin
13929
          `TIME; $display("*E Interrupt(s) is(are) pending although frame was ignored, interrupt reg: %0h", data);
13930
          test_fail("Interrupts were set");
13931
          fail = fail + 1;
13932
        end
13933
      end
13934 209 tadejm
      else
13935
      begin
13936 252 tadejm
        if ((data & `ETH_INT_RXE) !== `ETH_INT_RXE)
13937 209 tadejm
        begin
13938 243 tadejm
          `TIME; $display("*E Interrupt Receive Buffer Error was not set, interrupt reg: %0h", data);
13939
          test_fail("Interrupt Receive Buffer Error was not set");
13940 209 tadejm
          fail = fail + 1;
13941
        end
13942 243 tadejm
        if ((data & (~`ETH_INT_RXE)) !== 0)
13943
        begin
13944
          `TIME; $display("*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: %0h", data);
13945
          test_fail("Other interrupts (except Receive Buffer Error) were set");
13946
          fail = fail + 1;
13947
        end
13948 209 tadejm
      end
13949
      // clear interrupts
13950
      wbm_write(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
13951
      // check WB INT signal
13952
      if (wb_int !== 1'b0)
13953
      begin
13954
        test_fail("WB INT signal should not be set");
13955
        fail = fail + 1;
13956
      end
13957
      // INTERMEDIATE DISPLAYS
13958 243 tadejm
      if (num_of_frames == 3)
13959 209 tadejm
      begin
13960 243 tadejm
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
13961
        $display("    ->packets with lengths from %0d to %0d are not received (length increasing by 1 byte)",
13962 209 tadejm
                 0, 3);
13963
      end
13964 243 tadejm
      else if (num_of_frames == 9)
13965 209 tadejm
      begin
13966 243 tadejm
        $display("    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)");
13967
        $display("    ->packet with length 4 is not received (length increasing by 1 byte)");
13968 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13969
                 5, 9);
13970
      end
13971 243 tadejm
      else if (num_of_frames == 17)
13972 209 tadejm
      begin
13973 243 tadejm
        $display("    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)");
13974 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13975
                 10, 17);
13976
      end
13977 243 tadejm
      else if (num_of_frames == 27)
13978 209 tadejm
      begin
13979 243 tadejm
        $display("    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)");
13980 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13981
                 18, 27);
13982
      end
13983 243 tadejm
      else if (num_of_frames == 40)
13984 209 tadejm
      begin
13985 243 tadejm
        $display("    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)");
13986 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13987
                 28, 40);
13988
      end
13989 243 tadejm
      else if (num_of_frames == 54)
13990 209 tadejm
      begin
13991 243 tadejm
        $display("    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)");
13992 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13993
                 41, 54);
13994
      end
13995 243 tadejm
      else if (num_of_frames == 69)
13996 209 tadejm
      begin
13997 243 tadejm
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
13998 209 tadejm
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
13999
                 55, 69);
14000
      end
14001 243 tadejm
      else if (num_of_frames == 69)
14002
      begin
14003
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
14004
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14005
                 55, 69);
14006
      end
14007
      else if (num_of_frames == 77)
14008
      begin
14009
        $display("    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)");
14010
        $display("    ->packets with lengths from %0d to %0d are checked (length increasing by 1 byte)",
14011
                 70, 77);
14012
      end
14013 209 tadejm
      // set length (loop variable)
14014
      i_length = i_length + 1;
14015
      // the number of frame transmitted
14016
      num_of_frames = num_of_frames + 1;
14017
      if (/*(num_of_frames == 2) || (num_of_frames == 4) || (num_of_frames == 7) ||*/ (num_of_frames <= 10) ||
14018
          (num_of_frames == 14) || (num_of_frames == 18) || (num_of_frames == 23) || (num_of_frames == 28) ||
14019
          (num_of_frames == 34) || (num_of_frames == 40) || (num_of_frames == 47) ||
14020 243 tadejm
          (num_of_frames == 54) || (num_of_frames == 62) || (num_of_frames == 70))
14021
        num_of_bd = 120;
14022 209 tadejm
      else
14023
        num_of_bd = num_of_bd + 1;
14024
    end
14025 243 tadejm
    // disable RX
14026 209 tadejm
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_PAD | `ETH_MODER_CRCEN,
14027
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14028
    @(posedge wb_clk);
14029
    if(fail == 0)
14030
      test_ok;
14031
    else
14032
      fail = 0;
14033
  end
14034
 
14035
 
14036 243 tadejm
  ////////////////////////////////////////////////////////////////////
14037
  ////                                                            ////
14038
  ////  Test receive packet synchronization with receive          ////
14039
  ////  disable/enable ( 10Mbps ).                                ////
14040
  ////                                                            ////
14041
  ////////////////////////////////////////////////////////////////////
14042
  if (test_num == 10) // Test no receive when all buffers are TX ( 10Mbps ).
14043
  begin
14044
    // TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14045
    test_name   = "TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14046
    `TIME; $display("  TEST 10: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14047 209 tadejm
 
14048 243 tadejm
 
14049
 
14050
 
14051
 
14052
 
14053
  end
14054
 
14055
 
14056
  ////////////////////////////////////////////////////////////////////
14057
  ////                                                            ////
14058
  ////  Test receive packet synchronization with receive          ////
14059
  ////  disable/enable ( 10Mbps ).                                ////
14060
  ////                                                            ////
14061
  ////////////////////////////////////////////////////////////////////
14062
  if (test_num == 12) // Test no receive when all buffers are TX ( 10Mbps ).
14063
  begin
14064
    // TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14065
    test_name   = "TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14066
    `TIME; $display("  TEST 12: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14067
 
14068
 
14069
 
14070
 
14071
 
14072
 
14073
  end
14074
 
14075
 
14076
  ////////////////////////////////////////////////////////////////////
14077
  ////                                                            ////
14078
  ////  Test receive packet synchronization with receive          ////
14079
  ////  disable/enable ( 10Mbps ).                                ////
14080
  ////                                                            ////
14081
  ////////////////////////////////////////////////////////////////////
14082
  if (test_num == 14) // Test no receive when all buffers are TX ( 10Mbps ).
14083
  begin
14084
    // TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14085
    test_name   = "TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14086
    `TIME; $display("  TEST 14: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14087
 
14088
 
14089
 
14090
 
14091
 
14092
 
14093
  end
14094
 
14095
 
14096
  ////////////////////////////////////////////////////////////////////
14097
  ////                                                            ////
14098
  ////  Test receive packet synchronization with receive          ////
14099
  ////  disable/enable ( 10Mbps ).                                ////
14100
  ////                                                            ////
14101
  ////////////////////////////////////////////////////////////////////
14102
  if (test_num == 16) // Test no receive when all buffers are TX ( 10Mbps ).
14103
  begin
14104
    // TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
14105
    test_name   = "TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )";
14106
    `TIME; $display("  TEST 16: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )");
14107
 
14108
 
14109
 
14110
 
14111
 
14112
 
14113
  end
14114
 
14115
 
14116
 
14117 209 tadejm
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
14118
 
14119
end
14120
endtask // test_mac_full_duplex_receive
14121
 
14122
 
14123 263 mohor
task test_mac_full_duplex_flow_control;
14124 209 tadejm
  input  [31:0]  start_task;
14125
  input  [31:0]  end_task;
14126
  integer        bit_start_1;
14127
  integer        bit_end_1;
14128
  integer        bit_start_2;
14129
  integer        bit_end_2;
14130
  integer        num_of_reg;
14131
  integer        num_of_frames;
14132
  integer        num_of_bd;
14133
  integer        i_addr;
14134
  integer        i_data;
14135
  integer        i_length;
14136
  integer        tmp_len;
14137
  integer        tmp_bd;
14138
  integer        tmp_bd_num;
14139
  integer        tmp_data;
14140
  integer        tmp_ipgt;
14141
  integer        test_num;
14142
  reg    [31:0]  tx_bd_num;
14143
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
14144
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
14145
  integer        i;
14146
  integer        i1;
14147
  integer        i2;
14148
  integer        i3;
14149
  integer        fail;
14150
  integer        speed;
14151 260 mohor
  integer        mac_hi_addr;
14152
  integer        mac_lo_addr;
14153 209 tadejm
  reg            frame_started;
14154
  reg            frame_ended;
14155
  reg            wait_for_frame;
14156
  reg    [31:0]  addr;
14157
  reg    [31:0]  data;
14158
  reg    [31:0]  tmp;
14159
  reg    [ 7:0]  st_data;
14160
  reg    [15:0]  max_tmp;
14161
  reg    [15:0]  min_tmp;
14162 263 mohor
  reg            PassAll;
14163
  reg            RxFlow;
14164 209 tadejm
begin
14165 263 mohor
// MAC FULL DUPLEX FLOW CONTROL TEST
14166
test_heading("MAC FULL DUPLEX FLOW CONTROL TEST");
14167 209 tadejm
$display(" ");
14168 263 mohor
$display("MAC FULL DUPLEX FLOW CONTROL TEST");
14169 209 tadejm
fail = 0;
14170
 
14171
// reset MAC registers
14172
hard_reset;
14173
// reset MAC and MII LOGIC with soft reset
14174
reset_mac;
14175
reset_mii;
14176
// set wb slave response
14177
wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
14178
 
14179
  /*
14180
  TASKS for set and control TX buffer descriptors (also send packet - set_tx_bd_ready):
14181
  -------------------------------------------------------------------------------------
14182
  set_tx_bd
14183
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0], len[15:0], irq, pad, crc, txpnt[31:0]);
14184
  set_tx_bd_wrap
14185
    (tx_bd_num_end[6:0]);
14186
  set_tx_bd_ready
14187
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
14188
  check_tx_bd
14189
    (tx_bd_num_start[6:0], tx_bd_status[31:0]);
14190
  clear_tx_bd
14191
    (tx_bd_num_start[6:0], tx_bd_num_end[6:0]);
14192
 
14193
  TASKS for set and control RX buffer descriptors:
14194
  ------------------------------------------------
14195
  set_rx_bd
14196
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0], irq, rxpnt[31:0]);
14197
  set_rx_bd_wrap
14198
    (rx_bd_num_end[6:0]);
14199
  set_rx_bd_empty
14200
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
14201
  check_rx_bd
14202
    (rx_bd_num_end[6:0], rx_bd_status);
14203
  clear_rx_bd
14204
    (rx_bd_num_strat[6:0], rx_bd_num_end[6:0]);
14205
 
14206
  TASKS for set and check TX packets:
14207
  -----------------------------------
14208
  set_tx_packet
14209
    (txpnt[31:0], len[15:0], eth_start_data[7:0]);
14210
  check_tx_packet
14211
    (txpnt_wb[31:0], txpnt_phy[31:0], len[15:0], failure[31:0]);
14212
 
14213
  TASKS for set and check RX packets:
14214
  -----------------------------------
14215
  set_rx_packet
14216
    (rxpnt[31:0], len[15:0], plus_nibble, d_addr[47:0], s_addr[47:0], type_len[15:0], start_data[7:0]);
14217
  check_rx_packet
14218
    (rxpnt_phy[31:0], rxpnt_wb[31:0], len[15:0], plus_nibble, successful_nibble, failure[31:0]);
14219
 
14220
  TASKS for append and check CRC to/of TX packet:
14221
  -----------------------------------------------
14222
  append_tx_crc
14223
    (txpnt_wb[31:0], len[15:0], negated_crc);
14224
  check_tx_crc
14225
    (txpnt_phy[31:0], len[15:0], negated_crc, failure[31:0]);
14226
 
14227
  TASK for append CRC to RX packet (CRC is checked together with check_rx_packet):
14228
  --------------------------------------------------------------------------------
14229
  append_rx_crc
14230
    (rxpnt_phy[31:0], len[15:0], plus_nibble, negated_crc);
14231
  */
14232
 
14233
//////////////////////////////////////////////////////////////////////
14234
////                                                              ////
14235 263 mohor
////  test_mac_full_duplex_flow_control:                          ////
14236 209 tadejm
////                                                              ////
14237
////  0: Test                                                     ////
14238
////                                                              ////
14239
//////////////////////////////////////////////////////////////////////
14240 260 mohor
 
14241 209 tadejm
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
14242
begin
14243
 
14244
  ////////////////////////////////////////////////////////////////////
14245
  ////                                                            ////
14246 254 mohor
  ////  Test inserts control frames while transmitting normal     ////
14247
  ////  frames. Using 4 TX buffer decriptors ( 10Mbps ).          ////
14248 209 tadejm
  ////                                                            ////
14249
  ////////////////////////////////////////////////////////////////////
14250 254 mohor
  if (test_num == 0) // 
14251 209 tadejm
  begin
14252 254 mohor
    // TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )
14253
    test_name = "TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )";
14254
    `TIME; $display("  TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )");
14255 260 mohor
 
14256 254 mohor
    // reset MAC completely
14257
    hard_reset;
14258
    // set wb slave response
14259
    wb_slave.cycle_response(`ACK_RESPONSE, wbs_waits, wbs_retries);
14260 209 tadejm
 
14261 254 mohor
    max_tmp = 0;
14262
    min_tmp = 0;
14263
    // set 4 TX buffer descriptors - must be set before TX enable
14264
    wbm_write(`ETH_TX_BD_NUM, 32'h4, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14265
    // enable TX, set full-duplex mode, padding and CRC appending
14266
    wbm_write(`ETH_MODER, `ETH_MODER_TXEN | `ETH_MODER_PAD | `ETH_MODER_FULLD | `ETH_MODER_CRCEN,
14267
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14268
    // enable TX flow control
14269
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_TXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14270 260 mohor
 
14271
    // Set MAC address
14272
    mac_hi_addr = 32'h00000001;
14273
    mac_lo_addr = 32'h02030405;
14274
    wbm_write(`ETH_MAC_ADDR1, mac_hi_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14275
    wbm_write(`ETH_MAC_ADDR0, mac_lo_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14276
 
14277 254 mohor
    // prepare two packets of MAXFL length
14278
    wbm_read(`ETH_PACKETLEN, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14279
    max_tmp = tmp[15:0]; // 18 bytes consists of 6B dest addr, 6B source addr, 2B type/len, 4B CRC
14280
    min_tmp = tmp[31:16];
14281 260 mohor
    st_data = 8'h34;
14282 254 mohor
    set_tx_packet(`MEMORY_BASE, (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
14283 260 mohor
    st_data = 8'h56;
14284 254 mohor
    set_tx_packet((`MEMORY_BASE + max_tmp), (max_tmp - 4), st_data); // length without CRC. Writing data to the memory
14285
    // check WB INT signal
14286
    if (wb_int !== 1'b0)
14287
    begin
14288
      test_fail("WB INT signal should not be set");
14289
      fail = fail + 1;
14290
    end
14291
 
14292
    // write to phy's control register for 10Mbps
14293
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
14294
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
14295
    speed = 10;
14296
 
14297
    frame_started = 0;
14298
    num_of_frames = 0;
14299
    num_of_bd = 0;
14300
    i_length = 0; // 0;
14301 209 tadejm
 
14302 254 mohor
 
14303 260 mohor
    // Initialize one part of memory with data of control packet
14304
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h0), 32'h0180c200, 4'hF);
14305
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h4), {16'h0001, mac_hi_addr[15:0]}, 4'hF);
14306
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h8), mac_lo_addr, 4'hF);
14307
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'hc), 32'h88080001, 4'hF);
14308
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h11110000, 4'hF);
14309
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h14), 32'h00000000, 4'hF);
14310
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h18), 32'h00000000, 4'hF);
14311
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h1c), 32'h00000000, 4'hF);
14312
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h20), 32'h00000000, 4'hF);
14313
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h24), 32'h00000000, 4'hF);
14314
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h28), 32'h00000000, 4'hF);
14315
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h2c), 32'h00000000, 4'hF);
14316
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h30), 32'h00000000, 4'hF);
14317
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h34), 32'h00000000, 4'hF);
14318
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h38), 32'h00000000, 4'hF);
14319
//    append_tx_crc(`MEMORY_BASE + 2 * max_tmp, 60, 0);       // CRC is appended after the data
14320
 
14321
 
14322 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14323
    // In the following section, control frame will be sent while no other transmission is in progress.//
14324
    // TXC interrupt won't be unmasked.                                                                //
14325
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14326
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14327
    if(data)
14328
      begin
14329
        test_fail("IRQ already pending!");
14330
        fail = fail + 1;
14331
        `TIME; $display("*E IRQ already pending!");
14332
      end
14333
 
14334
    if (wb_int)
14335
    begin
14336
      test_fail("WB INT signal should not be set!");
14337
      fail = fail + 1;
14338
      `TIME; $display("*E WB INT signal should not be set!");
14339
    end
14340
 
14341 260 mohor
    // first destination address on ethernet PHY
14342
    eth_phy.set_tx_mem_addr(0);
14343
    // Request sending the control frame with pause value = 0x1111
14344
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h1111, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14345 254 mohor
 
14346
    wait (MTxEn === 1'b1); // start transmit
14347
    wait (MTxEn === 1'b0); // end transmit
14348
    repeat(10) @ (posedge wb_clk);  // wait some time
14349
    repeat(10) @ (posedge mtx_clk); // wait some time
14350
 
14351
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14352
    if(data !== `ETH_INT_TXC)
14353
      begin
14354
        test_fail("TXC IRQ should be set!");
14355
        fail = fail + 1;
14356
        `TIME; $display("*E TXC IRQ should be set!");
14357
      end
14358
 
14359
    if (wb_int)
14360
    begin
14361
      test_fail("WB INT signal should not be set because TXC irq is masked!");
14362
      fail = fail + 1;
14363
      `TIME; $display("*E WB INT signal should not be set because TXC irq is masked!");
14364
    end
14365
 
14366
    // Clear TXC interrupt
14367
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14368
 
14369
    if (wb_int)
14370
    begin
14371
      test_fail("WB INT signal should not be set!");
14372
      fail = fail + 1;
14373
      `TIME; $display("*E WB INT signal should not be set!");
14374
    end
14375
 
14376 260 mohor
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
14377
    if (tmp > 0)
14378
    begin
14379
      $display("Wrong data of the transmitted packet");
14380
      test_fail("Wrong data of the transmitted packet");
14381
      fail = fail + 1;
14382
    end
14383
    // check transmited TX packet CRC
14384
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
14385
    if (tmp > 0)
14386
    begin
14387
      $display("Wrong CRC of the transmitted packet");
14388
      test_fail("Wrong CRC of the transmitted packet");
14389
      fail = fail + 1;
14390
    end
14391 254 mohor
 
14392
 
14393
 
14394
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14395
    // In the following section, control frame will be sent while no other transmission is in progress.//
14396
    // TXC interrupt is unmasked.                                                                      //
14397
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14398
 
14399
    // unmask all interrupts
14400
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14401
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14402
 
14403
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14404
    if(data)
14405
      begin
14406
        test_fail("IRQ already pending!");
14407
        fail = fail + 1;
14408
        `TIME; $display("*E IRQ already pending!");
14409
      end
14410
 
14411
    if (wb_int)
14412
    begin
14413
      test_fail("WB INT signal should not be set!");
14414
      fail = fail + 1;
14415
      `TIME; $display("*E WB INT signal should not be set!");
14416
    end
14417
 
14418
    // unmask only TXC interrupts
14419
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14420
 
14421 260 mohor
    // first destination address on ethernet PHY
14422
    eth_phy.set_tx_mem_addr(0);
14423
    // Request sending the control frame with pause value = 0x2222
14424
    wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), 32'h22220000, 4'hF);  // Just for data test
14425
    wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | 32'h2222, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14426 254 mohor
 
14427
    wait (MTxEn === 1'b1); // start transmit
14428
    wait (MTxEn === 1'b0); // end transmit
14429
    repeat(10) @ (posedge wb_clk);  // wait some time
14430
    repeat(10) @ (posedge mtx_clk); // wait some time
14431
 
14432
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14433
    if(data !== `ETH_INT_TXC)
14434
      begin
14435
        test_fail("TXC IRQ should be set!");
14436
        fail = fail + 1;
14437
        `TIME; $display("*E TXC IRQ should be set!");
14438
      end
14439
 
14440
    if (!wb_int)
14441
    begin
14442
      test_fail("WB INT signal should be set!");
14443
      fail = fail + 1;
14444
      `TIME; $display("*E WB INT signal should be set!");
14445
    end
14446
 
14447
    // Clear TXC interrupt
14448
    wbm_write(`ETH_INT, `ETH_INT_TXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14449
 
14450
    if (wb_int)
14451
    begin
14452
      test_fail("WB INT signal should not be set!");
14453
      fail = fail + 1;
14454
      `TIME; $display("*E WB INT signal should not be set!");
14455
    end
14456
 
14457
 
14458 260 mohor
    check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
14459
    if (tmp > 0)
14460
    begin
14461
      $display("Wrong data of the transmitted packet");
14462
      test_fail("Wrong data of the transmitted packet");
14463
      fail = fail + 1;
14464
    end
14465
    // check transmited TX packet CRC
14466
    #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
14467
    if (tmp > 0)
14468
    begin
14469
      $display("Wrong CRC of the transmitted packet");
14470
      test_fail("Wrong CRC of the transmitted packet");
14471
      fail = fail + 1;
14472
    end
14473 254 mohor
 
14474 260 mohor
 
14475 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14476 260 mohor
    // In the following section, control frame sending is requested while no other transmission        //
14477
    // is in progress. TXC interrupt is unmasked.                                                      //
14478 254 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14479
 
14480
    // unmask all interrupts
14481
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14482
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14483
 
14484
    wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14485
    if(data)
14486
      begin
14487
        test_fail("IRQ already pending!");
14488
        fail = fail + 1;
14489
        `TIME; $display("*E IRQ already pending!");
14490
      end
14491
 
14492
    if (wb_int)
14493
    begin
14494
      test_fail("WB INT signal should not be set!");
14495
      fail = fail + 1;
14496
      `TIME; $display("*E WB INT signal should not be set!");
14497
    end
14498
 
14499
 
14500 260 mohor
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14501
    // In the following section, control frame request and data send request are both set. At the      //
14502
    // beginning control frame request will be faster than data send request, later the opposite.      //
14503
    /////////////////////////////////////////////////////////////////////////////////////////////////////
14504
    for (i=0; i<32; i=i+1)
14505
    begin
14506
      // Request sending the control frame with pause value = 0x5678
14507
      set_tx_bd(0, 0, 16'h100, 1'b1, 1'b1, 1'b1, (`MEMORY_BASE)); // irq, pad, crc
14508
      set_tx_bd_wrap(0);
14509
      // first destination address on ethernet PHY
14510
      eth_phy.set_tx_mem_addr(0);
14511
      set_tx_bd_ready(0, 0);
14512
 
14513
      wait (MTxEn === 1'b1); // start transmit
14514
 
14515
      repeat(i) @ (posedge mtx_clk);  // We need to wait some time until TX module starts using the data (preamble stage is over)
14516
 
14517
      // Send control frame request
14518
      wb_slave.wr_mem((`MEMORY_BASE + 2 * max_tmp + 8'h10), {i[3:0], i[3:0], i[3:0], i[3:0], 16'h0}, 4'hF);  // Just for data test
14519
      wbm_write(`ETH_TX_CTRL, `ETH_TX_CTRL_TXPAUSERQ | {16'h0, i[3:0], i[3:0], i[3:0], i[3:0]}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14520
 
14521
      wait (MTxEn === 1'b0); // Wait until data frame transmission is over
14522
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
14523
      tmp_len = eth_phy.tx_len; // the length of a packet which was sent out first!!!
14524
      repeat(10) @ (posedge wb_clk);  // wait some time so status is written
14525
 
14526
      // first destination address on ethernet PHY
14527
      eth_phy.set_tx_mem_addr(0);
14528
 
14529
      if(tmp_len == 64)  // Control frame
14530 254 mohor
      begin
14531 260 mohor
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14532
        if(data !== `ETH_INT_TXC)
14533
        begin
14534
          test_fail("TXC IRQ should be set!");
14535
          fail = fail + 1;
14536
          `TIME; $display("*E TXC IRQ should be set!");
14537
          `TIME; $display("ETH_INT = 0x%0x", data);
14538
        end
14539
      end
14540
      else
14541
      begin
14542
        wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14543
        if(data !== `ETH_INT_TXB)
14544
        begin
14545
          test_fail("TXB IRQ should be set!");
14546
          fail = fail + 1;
14547
          `TIME; $display("*E TXB IRQ should be set!");
14548
          `TIME; $display("ETH_INT = 0x%0x", data);
14549
        end
14550
      end
14551
 
14552
      if(tmp_len == 64)  // Control frame
14553
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
14554
      else
14555
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
14556
 
14557
      if (tmp > 0)
14558
      begin
14559
        $display("Wrong data of the transmitted packet");
14560
        test_fail("Wrong data of the transmitted packet");
14561 254 mohor
        fail = fail + 1;
14562
      end
14563 260 mohor
 
14564
      // check transmited TX packet CRC
14565
      if(tmp_len == 64)  // Control frame
14566
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
14567
      else
14568
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
14569
 
14570
      if (tmp > 0)
14571 254 mohor
      begin
14572 260 mohor
        $display("Wrong CRC of the transmitted packet");
14573
        test_fail("Wrong CRC of the transmitted packet");
14574
        fail = fail + 1;
14575
      end
14576
 
14577
 
14578
      wait (MTxEn === 1'b1); // start transmit of the control frame
14579
      wait (MTxEn === 1'b0); // end transmit of the control frame
14580
      repeat(10) @ (posedge wb_clk);  // wait some time
14581
      repeat(10) @ (posedge mtx_clk); // wait some time so status is written
14582
 
14583
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14584
      if(data !== (`ETH_INT_TXC | `ETH_INT_TXB))
14585
      begin
14586 254 mohor
        test_fail("TXC and TXB IRQ should be set!");
14587
        fail = fail + 1;
14588 260 mohor
        `TIME; $display("*E TXC and TXB IRQ should be set! (ETH_INT=0x%0x)", data);
14589 254 mohor
      end
14590 260 mohor
 
14591
      if (!wb_int)
14592
      begin
14593
        test_fail("WB INT signal should be set!");
14594
        fail = fail + 1;
14595
        `TIME; $display("*E WB INT signal should be set!");
14596
      end
14597
 
14598
      // Clear TXC and TXB interrupt
14599
      wbm_write(`ETH_INT, `ETH_INT_TXC | `ETH_INT_TXB, 4'hF, 1, 4'h0, 4'h0);
14600
 
14601
      if (wb_int)
14602
      begin
14603
        test_fail("WB INT signal should not be set!");
14604
        fail = fail + 1;
14605
        `TIME; $display("*E WB INT signal should not be set!");
14606
      end
14607
 
14608
      if(tmp_len == 64)  // Control frame
14609
        check_tx_packet((`MEMORY_BASE), 0, 32'h100, tmp);
14610
      else
14611
        check_tx_packet((`MEMORY_BASE + 2 * max_tmp), 0, 60, tmp);
14612
 
14613
      if (tmp > 0)
14614
      begin
14615
        $display("Wrong data of the transmitted packet");
14616
        test_fail("Wrong data of the transmitted packet");
14617
        fail = fail + 1;
14618
      end
14619
 
14620
      // check transmited TX packet CRC
14621
      if(tmp_len == 64)  // Control frame
14622
        #1 check_tx_crc(0, 32'h100, 1'b0, tmp); // length without CRC
14623
      else
14624
        #1 check_tx_crc(0, 60, 1'b0, tmp); // length without CRC
14625
 
14626
      if (tmp > 0)
14627
      begin
14628
        $display("Wrong CRC of the transmitted packet");
14629
        test_fail("Wrong CRC of the transmitted packet");
14630
        fail = fail + 1;
14631
      end
14632
    end // for loop
14633 254 mohor
 
14634 260 mohor
    if(fail)
14635 254 mohor
    begin
14636 260 mohor
      test_name = "TEST 0: FINISHED WITH ERRORS";
14637
      `TIME; $display("  TEST 0: FINISHED WITH ERRORS");
14638 254 mohor
    end
14639 260 mohor
    else
14640 254 mohor
    begin
14641 260 mohor
      test_name = "TEST 0: SUCCESSFULLY FINISHED";
14642
      `TIME; $display("  TEST 0: SUCCESSFULLY FINISHED");
14643 254 mohor
    end
14644
 
14645 260 mohor
    if(fail == 0)
14646
      test_ok;
14647
    else
14648
      fail = 0;
14649 254 mohor
 
14650 260 mohor
  end
14651 254 mohor
 
14652
 
14653 263 mohor
  if (test_num == 1) // 
14654
  begin
14655
    #1;
14656
    // TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )
14657
    test_name = "TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )";
14658
    `TIME; $display("  TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )");
14659
  end
14660 254 mohor
 
14661 260 mohor
  ////////////////////////////////////////////////////////////////////
14662
  ////                                                            ////
14663
  ////  Receive control frames with PASSALL option turned off     ////
14664
  ////  Using only one RX buffer decriptor ( 10Mbps ).            ////
14665
  ////                                                            ////
14666
  ////////////////////////////////////////////////////////////////////
14667 263 mohor
  if (test_num == 2) // 
14668 260 mohor
  begin
14669 263 mohor
    // TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )
14670
    test_name   = "TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )";
14671
    `TIME; $display("  TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps )");
14672 254 mohor
 
14673 260 mohor
    // unmask interrupts
14674
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14675
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14676
    // set 1 RX buffer descriptor (8'h80 - 1) - must be set before RX enable
14677
    wbm_write(`ETH_TX_BD_NUM, 32'h7F, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14678
    // enable RX, set full-duplex mode, NO receive small, NO correct IFG
14679
    wbm_write(`ETH_MODER, `ETH_MODER_RXEN | `ETH_MODER_FULLD | `ETH_MODER_IFG |
14680
              `ETH_MODER_PRO | `ETH_MODER_BRO,
14681
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14682 263 mohor
    // enable RX_FLOW control
14683
    wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14684 260 mohor
    // prepare one control (PAUSE)packet
14685
    st_data = 8'h00;
14686
    set_rx_packet(0, 60, 1'b0, 48'h0180_c200_0001, 48'h0708_090A_0B0C, 16'h8808, st_data); // length without CRC
14687 263 mohor
    append_rx_crc (0, 60, 1'b0, 1'b0); // CRC for control packet
14688 260 mohor
    // prepare one packet of 100 bytes long
14689
    st_data = 8'h1A;
14690
    set_rx_packet(64, 100, 1'b0, 48'h1234_5678_8765, 48'hA1B2_C3D4_E5F6, 16'hE77E, st_data);
14691 263 mohor
    append_rx_crc (64, 100, 1'b0, 1'b0); // CRC for data packet
14692 260 mohor
    // check WB INT signal
14693
    if (wb_int !== 1'b0)
14694
    begin
14695
      test_fail("WB INT signal should not be set");
14696
      fail = fail + 1;
14697
    end
14698
 
14699
    // write to phy's control register for 10Mbps
14700
    #Tp eth_phy.control_bit14_10 = 5'b00000; // bit 13 reset - speed 10
14701
    #Tp eth_phy.control_bit8_0   = 9'h1_00;  // bit 6 reset  - (10/100), bit 8 set - FD
14702
    speed = 10;
14703 254 mohor
 
14704 263 mohor
    wbm_write(`ETH_INT_MASK, `ETH_INT_TXB | `ETH_INT_TXE | `ETH_INT_RXB | `ETH_INT_RXE | `ETH_INT_BUSY |
14705
                             `ETH_INT_TXC | `ETH_INT_RXC, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14706
 
14707 260 mohor
    for (i=0; i<4; i=i+1)
14708 263 mohor
//    i=3;
14709 254 mohor
    begin
14710 263 mohor
$display("i=%0d", i);
14711 260 mohor
      // choose generating carrier sense and collision for first and last 64 lengths of frames
14712
      case (i)
14713 263 mohor
      0: // PASSALL = 0, RXFLOW = 0
14714 254 mohor
      begin
14715 263 mohor
        PassAll=0; RxFlow=0;
14716 260 mohor
        // enable interrupt generation
14717 263 mohor
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
14718
        // Set PASSALL = 0 and RXFLOW = 0
14719
        wbm_write(`ETH_CTRLMODER, 0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14720 254 mohor
      end
14721 263 mohor
      1: // PASSALL = 0, RXFLOW = 1
14722 254 mohor
      begin
14723 263 mohor
        PassAll=0; RxFlow=1;
14724 260 mohor
        // enable interrupt generation
14725 263 mohor
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
14726
        // Set PASSALL = 0 and RXFLOW = 0
14727
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14728 254 mohor
      end
14729 263 mohor
      2: // PASSALL = 1, RXFLOW = 0
14730 254 mohor
      begin
14731 263 mohor
        PassAll=1; RxFlow=0;
14732
        // enable interrupt generation
14733
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
14734
        // Set PASSALL = 0 and RXFLOW = 0
14735
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14736 254 mohor
      end
14737 263 mohor
      default: // 3: PASSALL = 1, RXFLOW = 1
14738 254 mohor
      begin
14739 263 mohor
        PassAll=1; RxFlow=1;
14740
        // enable interrupt generation
14741
        set_rx_bd(127, 127, 1'b1, `MEMORY_BASE);
14742
        // Set PASSALL = 1 and RXFLOW = 1
14743
        wbm_write(`ETH_CTRLMODER, `ETH_CTRLMODER_PASSALL | `ETH_CTRLMODER_RXFLOW, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14744 254 mohor
      end
14745
      endcase
14746 260 mohor
 
14747 263 mohor
      // not detect carrier sense in FD and no collision
14748
      eth_phy.no_carrier_sense_rx_fd_detect(0);
14749
      eth_phy.collision(0);
14750
 
14751
      // set wrap bit and empty bit
14752 260 mohor
      set_rx_bd_wrap(127);
14753
      set_rx_bd_empty(127, 127);
14754 263 mohor
 
14755 260 mohor
      fork
14756 254 mohor
        begin
14757 260 mohor
            #1 eth_phy.send_rx_packet(64'h0055_5555_5555_5555, 4'h7, 8'hD5, 0, 64, 1'b0);
14758
          repeat(10) @(posedge mrx_clk);
14759 254 mohor
        end
14760
        begin
14761 260 mohor
          #1 check_rx_bd(127, data);
14762
          wait (MRxDV === 1'b1); // start transmit
14763 263 mohor
          #1 check_rx_bd(127, data);
14764 260 mohor
          if (data[15] !== 1)
14765
          begin
14766 263 mohor
            $display("*E Wrong buffer descriptor's ready bit read out from MAC");
14767 260 mohor
            test_fail("Wrong buffer descriptor's ready bit read out from MAC");
14768
            fail = fail + 1;
14769
          end
14770 263 mohor
 
14771 260 mohor
          wait (MRxDV === 1'b0); // end transmit
14772 263 mohor
          repeat(50) @(posedge mrx_clk);  // Wait some time so frame is received and
14773
          repeat (100) @(posedge wb_clk); // status/irq is written.
14774 254 mohor
        end
14775 260 mohor
      join
14776 263 mohor
 
14777
      #1 check_rx_bd(127, data);
14778
 
14779
      // Checking buffer descriptor
14780
      if(PassAll)
14781 254 mohor
      begin
14782 263 mohor
        if(data !== 32'h406100)    // Rx BD must not be marked as EMPTY (control frame is received)
14783
        begin
14784
          $display("*E Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
14785
          $display("RxBD = 0x%0x", data);
14786
          test_fail("Rx BD is not OK. Control frame should be received because PASSALL bit is 1");
14787
          fail = fail + 1;
14788
        end
14789 254 mohor
      end
14790 260 mohor
      else
14791 254 mohor
      begin
14792 263 mohor
        if(data !== 32'he000)    // Rx BD must be marked as EMPTY (no packet received)
14793
        begin
14794
          $display("*E Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
14795
          $display("RxBD = 0x%0x", data);
14796
          test_fail("Rx BD should be marked as EMPTY because a control frame was received while PASSALL bit is 0");
14797
          fail = fail + 1;
14798
        end
14799 254 mohor
      end
14800 263 mohor
 
14801
      // Checking if interrupt was generated
14802
      if(RxFlow || PassAll)
14803 254 mohor
      begin
14804 263 mohor
        if (!wb_int)
14805 254 mohor
        begin
14806
          `TIME; $display("*E WB INT signal should be set");
14807
          test_fail("WB INT signal should be set");
14808
          fail = fail + 1;
14809
        end
14810
      end
14811
      else
14812
      begin
14813 263 mohor
        if (wb_int)
14814 254 mohor
        begin
14815
          `TIME; $display("*E WB INT signal should not be set");
14816
          test_fail("WB INT signal should not be set");
14817
          fail = fail + 1;
14818
        end
14819
      end
14820 263 mohor
 
14821
      wbm_read(`ETH_INT, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14822
      if(RxFlow)
14823 254 mohor
      begin
14824 263 mohor
        if(data !== (`ETH_INT_RXC))
14825 254 mohor
        begin
14826 263 mohor
          test_fail("RXC is not set or multiple IRQs active!");
14827 260 mohor
          fail = fail + 1;
14828 263 mohor
          `TIME; $display("*E RXC is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
14829 254 mohor
        end
14830 263 mohor
        // Clear RXC interrupt
14831
        wbm_write(`ETH_INT, `ETH_INT_RXC, 4'hF, 1, 4'h0, 4'h0);
14832 254 mohor
      end
14833 263 mohor
      else if(PassAll)
14834 254 mohor
      begin
14835 263 mohor
        if(data !== (`ETH_INT_RXB))
14836 254 mohor
        begin
14837 263 mohor
          test_fail("RXB is not set or multiple IRQs active!");
14838 254 mohor
          fail = fail + 1;
14839 263 mohor
          `TIME; $display("*E RXB is not set or multiple IRQs active! (ETH_INT=0x%0x)", data);
14840 254 mohor
        end
14841 263 mohor
        // Clear RXB interrupt
14842
        wbm_write(`ETH_INT, `ETH_INT_RXB, 4'hF, 1, 4'h0, 4'h0);
14843 254 mohor
      end
14844
      else
14845
      begin
14846 263 mohor
        if(data !== 0)
14847 254 mohor
        begin
14848 263 mohor
          test_fail("No interrupt should be set!");
14849 254 mohor
          fail = fail + 1;
14850 263 mohor
          `TIME; $display("*E No interrupt should be set! (ETH_INT=0x%0x)", data);
14851 254 mohor
        end
14852
      end
14853
    end
14854 263 mohor
 
14855
 
14856 260 mohor
    // disable RX
14857
    wbm_write(`ETH_MODER, `ETH_MODER_FULLD | `ETH_MODER_RECSMALL | `ETH_MODER_IFG |
14858
              `ETH_MODER_PRO | `ETH_MODER_BRO,
14859 254 mohor
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14860
    if(fail == 0)
14861
      test_ok;
14862
    else
14863
      fail = 0;
14864 209 tadejm
  end
14865
 
14866
 
14867
end   //  for (test_num=start_task; test_num <= end_task; test_num=test_num+1)
14868
 
14869 260 mohor
 
14870 209 tadejm
end
14871 263 mohor
endtask // test_mac_full_duplex_flow_control
14872 209 tadejm
 
14873
 
14874 169 mohor
//////////////////////////////////////////////////////////////
14875
// WB Behavioral Models Basic tasks
14876
//////////////////////////////////////////////////////////////
14877
 
14878
task wbm_write;
14879
  input  [31:0] address_i;
14880
  input  [((`MAX_BLK_SIZE * 32) - 1):0] data_i;
14881
  input  [3:0]  sel_i;
14882
  input  [31:0] size_i;
14883
  input  [3:0]  init_waits_i;
14884
  input  [3:0]  subseq_waits_i;
14885
 
14886
  reg `WRITE_STIM_TYPE write_data;
14887
  reg `WB_TRANSFER_FLAGS flags;
14888
  reg `WRITE_RETURN_TYPE write_status;
14889
  integer i;
14890
begin
14891
  write_status = 0;
14892
 
14893
  flags                    = 0;
14894
  flags`WB_TRANSFER_SIZE   = size_i;
14895
  flags`INIT_WAITS         = init_waits_i;
14896
  flags`SUBSEQ_WAITS       = subseq_waits_i;
14897
 
14898
  write_data               = 0;
14899
  write_data`WRITE_DATA    = data_i[31:0];
14900
  write_data`WRITE_ADDRESS = address_i;
14901
  write_data`WRITE_SEL     = sel_i;
14902
 
14903
  for (i = 0; i < size_i; i = i + 1)
14904
  begin
14905
    wb_master.blk_write_data[i] = write_data;
14906
    data_i                      = data_i >> 32;
14907
    write_data`WRITE_DATA       = data_i[31:0];
14908
    write_data`WRITE_ADDRESS    = write_data`WRITE_ADDRESS + 4;
14909 116 mohor
  end
14910
 
14911 169 mohor
  wb_master.wb_block_write(flags, write_status);
14912 116 mohor
 
14913 169 mohor
  if (write_status`CYC_ACTUAL_TRANSFER !== size_i)
14914
  begin
14915
    `TIME;
14916
    $display("*E WISHBONE Master was unable to complete the requested write operation to MAC!");
14917
  end
14918
end
14919
endtask // wbm_write
14920 116 mohor
 
14921 169 mohor
task wbm_read;
14922
  input  [31:0] address_i;
14923
  output [((`MAX_BLK_SIZE * 32) - 1):0] data_o;
14924
  input  [3:0]  sel_i;
14925
  input  [31:0] size_i;
14926
  input  [3:0]  init_waits_i;
14927
  input  [3:0]  subseq_waits_i;
14928
 
14929
  reg `READ_RETURN_TYPE read_data;
14930
  reg `WB_TRANSFER_FLAGS flags;
14931
  reg `READ_RETURN_TYPE read_status;
14932
  integer i;
14933
begin
14934
  read_status = 0;
14935
  data_o      = 0;
14936
 
14937
  flags                  = 0;
14938
  flags`WB_TRANSFER_SIZE = size_i;
14939
  flags`INIT_WAITS       = init_waits_i;
14940
  flags`SUBSEQ_WAITS     = subseq_waits_i;
14941
 
14942
  read_data              = 0;
14943
  read_data`READ_ADDRESS = address_i;
14944
  read_data`READ_SEL     = sel_i;
14945
 
14946
  for (i = 0; i < size_i; i = i + 1)
14947 116 mohor
  begin
14948 169 mohor
    wb_master.blk_read_data_in[i] = read_data;
14949
    read_data`READ_ADDRESS        = read_data`READ_ADDRESS + 4;
14950
  end
14951
 
14952
  wb_master.wb_block_read(flags, read_status);
14953
 
14954
  if (read_status`CYC_ACTUAL_TRANSFER !== size_i)
14955
  begin
14956
    `TIME;
14957
    $display("*E WISHBONE Master was unable to complete the requested read operation from MAC!");
14958
  end
14959
 
14960
  for (i = 0; i < size_i; i = i + 1)
14961
  begin
14962
    data_o       = data_o << 32;
14963
    read_data    = wb_master.blk_read_data_out[(size_i - 1) - i]; // [31 - i];
14964
    data_o[31:0] = read_data`READ_DATA;
14965
  end
14966
end
14967
endtask // wbm_read
14968
 
14969
 
14970
//////////////////////////////////////////////////////////////
14971
// Ethernet Basic tasks
14972
//////////////////////////////////////////////////////////////
14973
 
14974
task hard_reset; //  MAC registers
14975
begin
14976
  // reset MAC registers
14977
  @(posedge wb_clk);
14978
  #2 wb_rst = 1'b1;
14979
  repeat(2) @(posedge wb_clk);
14980
  #2 wb_rst = 1'b0;
14981
end
14982
endtask // hard_reset
14983
 
14984
task reset_mac; //  MAC module
14985
  reg [31:0] tmp;
14986
  reg [31:0] tmp_no_rst;
14987
begin
14988
  // read MODER register first
14989
  wbm_read(`ETH_MODER, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14990
  // set reset bit - write back to MODER register with RESET bit
14991
  wbm_write(`ETH_MODER, (`ETH_MODER_RST | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14992
  // clear reset bit - write back to MODER register without RESET bit
14993
  tmp_no_rst = `ETH_MODER_RST;
14994
  tmp_no_rst = ~tmp_no_rst;
14995
  wbm_write(`ETH_MODER, (tmp_no_rst & tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
14996
end
14997
endtask // reset_mac
14998
 
14999
task set_tx_bd;
15000
  input  [6:0]  tx_bd_num_start;
15001
  input  [6:0]  tx_bd_num_end;
15002
  input  [15:0] len;
15003
  input         irq;
15004
  input         pad;
15005
  input         crc;
15006
  input  [31:0] txpnt;
15007
 
15008
  integer       i;
15009
  integer       bd_status_addr, bd_ptr_addr;
15010
//  integer       buf_addr;
15011
begin
15012
  for(i = tx_bd_num_start; i <= tx_bd_num_end; i = i + 1)
15013
  begin
15014
//    buf_addr = `TX_BUF_BASE + i * 32'h600;
15015
    bd_status_addr = `TX_BD_BASE + i * 8;
15016
    bd_ptr_addr = bd_status_addr + 4;
15017
    // initialize BD - status
15018
//    wbm_write(bd_status_addr, 32'h00005800, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
15019
    wbm_write(bd_status_addr, {len, 1'b0, irq, 1'b0, pad, crc, 11'h0},
15020
              4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
15021
    // initialize BD - pointer
15022
//    wbm_write(bd_ptr_addr, buf_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
15023
    wbm_write(bd_ptr_addr, txpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
15024
  end
15025
end
15026
endtask // set_tx_bd
15027
 
15028
task set_tx_bd_wrap;
15029
  input  [6:0]  tx_bd_num_end;
15030
  integer       bd_status_addr, tmp;
15031
begin
15032
  bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
15033
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15034
  // set wrap bit to this BD - this BD should be last-one
15035
  wbm_write(bd_status_addr, (`ETH_TX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15036
end
15037
endtask // set_tx_bd_wrap
15038
 
15039
task set_tx_bd_ready;
15040
  input  [6:0]  tx_nd_num_strat;
15041
  input  [6:0]  tx_bd_num_end;
15042
  integer       i;
15043
  integer       bd_status_addr, tmp;
15044
begin
15045
  for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
15046
  begin
15047
    bd_status_addr = `TX_BD_BASE + i * 8;
15048
    wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15049
    // set empty bit to this BD - this BD should be ready
15050
    wbm_write(bd_status_addr, (`ETH_TX_BD_READY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15051
  end
15052
end
15053
endtask // set_tx_bd_ready
15054
 
15055
task check_tx_bd;
15056
  input  [6:0]  tx_bd_num_end;
15057
  output [31:0] tx_bd_status;
15058
  integer       bd_status_addr, tmp;
15059
begin
15060
  bd_status_addr = `TX_BD_BASE + tx_bd_num_end * 8;
15061
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15062
  #1 tx_bd_status = tmp;
15063
  #1;
15064
end
15065
endtask // check_tx_bd
15066
 
15067
task clear_tx_bd;
15068
  input  [6:0]  tx_nd_num_strat;
15069
  input  [6:0]  tx_bd_num_end;
15070
  integer       i;
15071
  integer       bd_status_addr, bd_ptr_addr;
15072
begin
15073
  for(i = tx_nd_num_strat; i <= tx_bd_num_end; i = i + 1)
15074
  begin
15075
    bd_status_addr = `TX_BD_BASE + i * 8;
15076
    bd_ptr_addr = bd_status_addr + 4;
15077
    // clear BD - status
15078
    wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15079
    // clear BD - pointer
15080
    wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15081
  end
15082
end
15083
endtask // clear_tx_bd
15084
 
15085
task set_rx_bd;
15086
  input  [6:0]  rx_bd_num_strat;
15087
  input  [6:0]  rx_bd_num_end;
15088
  input         irq;
15089
  input  [31:0] rxpnt;
15090
//  input  [6:0]  rxbd_num;
15091
  integer       i;
15092
  integer       bd_status_addr, bd_ptr_addr;
15093
//  integer       buf_addr;
15094
begin
15095
  for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
15096
  begin
15097
//    buf_addr = `RX_BUF_BASE + i * 32'h600;
15098 209 tadejm
//    bd_status_addr = `RX_BD_BASE + i * 8;
15099
//    bd_ptr_addr = bd_status_addr + 4; 
15100
    bd_status_addr = `TX_BD_BASE + i * 8;
15101
    bd_ptr_addr = bd_status_addr + 4;
15102 116 mohor
 
15103 169 mohor
    // initialize BD - status
15104
//    wbm_write(bd_status_addr, 32'h0000c000, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // IRQ + PAD + CRC
15105
    wbm_write(bd_status_addr, {17'h0, irq, 14'h0},
15106
              4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15107
    // initialize BD - pointer
15108
//    wbm_write(bd_ptr_addr, buf_addr, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
15109
    wbm_write(bd_ptr_addr, rxpnt, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); // Initializing BD-pointer
15110
  end
15111
end
15112
endtask // set_rx_bd
15113 116 mohor
 
15114 169 mohor
task set_rx_bd_wrap;
15115
  input  [6:0]  rx_bd_num_end;
15116
  integer       bd_status_addr, tmp;
15117
begin
15118 209 tadejm
//  bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
15119
  bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
15120 169 mohor
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15121
  // set wrap bit to this BD - this BD should be last-one
15122
  wbm_write(bd_status_addr, (`ETH_RX_BD_WRAP | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15123
end
15124
endtask // set_rx_bd_wrap
15125 116 mohor
 
15126 169 mohor
task set_rx_bd_empty;
15127
  input  [6:0]  rx_bd_num_strat;
15128
  input  [6:0]  rx_bd_num_end;
15129
  integer       i;
15130
  integer       bd_status_addr, tmp;
15131
begin
15132
  for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
15133
  begin
15134 209 tadejm
//    bd_status_addr = `RX_BD_BASE + i * 8;
15135
    bd_status_addr = `TX_BD_BASE + i * 8;
15136 169 mohor
    wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15137
    // set empty bit to this BD - this BD should be ready
15138
    wbm_write(bd_status_addr, (`ETH_RX_BD_EMPTY | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15139 116 mohor
  end
15140 169 mohor
end
15141
endtask // set_rx_bd_empty
15142 116 mohor
 
15143 169 mohor
task check_rx_bd;
15144
  input  [6:0]  rx_bd_num_end;
15145
  output [31:0] rx_bd_status;
15146
  integer       bd_status_addr, tmp;
15147
begin
15148 209 tadejm
//  bd_status_addr = `RX_BD_BASE + rx_bd_num_end * 8;
15149
  bd_status_addr = `TX_BD_BASE + rx_bd_num_end * 8;
15150 169 mohor
  wbm_read(bd_status_addr, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15151
  #1 rx_bd_status = tmp;
15152
  #1;
15153
end
15154
endtask // check_rx_bd
15155 116 mohor
 
15156 169 mohor
task clear_rx_bd;
15157
  input  [6:0]  rx_bd_num_strat;
15158
  input  [6:0]  rx_bd_num_end;
15159
  integer       i;
15160
  integer       bd_status_addr, bd_ptr_addr;
15161
begin
15162
  for(i = rx_bd_num_strat; i <= rx_bd_num_end; i = i + 1)
15163
  begin
15164 209 tadejm
//    bd_status_addr = `RX_BD_BASE + i * 8;
15165
    bd_status_addr = `TX_BD_BASE + i * 8;
15166 169 mohor
    bd_ptr_addr = bd_status_addr + 4;
15167
    // clear BD - status
15168
    wbm_write(bd_status_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15169
    // clear BD - pointer
15170
    wbm_write(bd_ptr_addr, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
15171
  end
15172
end
15173
endtask // clear_rx_bd
15174 116 mohor
 
15175 169 mohor
task set_tx_packet;
15176
  input  [31:0] txpnt;
15177
  input  [15:0] len;
15178
  input  [7:0]  eth_start_data;
15179
  integer       i, sd;
15180
  integer       buffer;
15181
  reg           delta_t;
15182
begin
15183
  buffer = txpnt;
15184
  sd = eth_start_data;
15185
  delta_t = 0;
15186 116 mohor
 
15187 169 mohor
  // First write might not be word allign.
15188
  if(buffer[1:0] == 1)
15189
  begin
15190
    wb_slave.wr_mem(buffer - 1, {8'h0, sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2}, 4'h7);
15191
    sd = sd + 3;
15192
    i = 3;
15193
  end
15194
  else if(buffer[1:0] == 2)
15195
  begin
15196
    wb_slave.wr_mem(buffer - 2, {16'h0, sd[7:0], sd[7:0] + 3'h1}, 4'h3);
15197
    sd = sd + 2;
15198
    i = 2;
15199
  end
15200
  else if(buffer[1:0] == 3)
15201
  begin
15202
    wb_slave.wr_mem(buffer - 3, {24'h0, sd[7:0]}, 4'h1);
15203
    sd = sd + 1;
15204
    i = 1;
15205
  end
15206
  else
15207
    i = 0;
15208
  delta_t = !delta_t;
15209 116 mohor
 
15210 169 mohor
  for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not written
15211
  begin
15212
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2, sd[7:0] + 3'h3}, 4'hF);
15213
    sd = sd + 4;
15214
  end
15215
  delta_t = !delta_t;
15216
 
15217
  // Last word
15218
  if((len - i) == 3)
15219 116 mohor
  begin
15220 169 mohor
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2, 8'h0}, 4'hE);
15221
  end
15222
  else if((len - i) == 2)
15223
  begin
15224
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, 16'h0}, 4'hC);
15225
  end
15226
  else if((len - i) == 1)
15227
  begin
15228
    wb_slave.wr_mem(buffer + i, {sd[7:0], 24'h0}, 4'h8);
15229
  end
15230
  else if((len - i) == 4)
15231
  begin
15232
    wb_slave.wr_mem(buffer + i, {sd[7:0], sd[7:0] + 3'h1, sd[7:0] + 3'h2, sd[7:0] + 3'h3}, 4'hF);
15233
  end
15234
  else
15235
    $display("(%0t)(%m) ERROR", $time);
15236
  delta_t = !delta_t;
15237
end
15238
endtask // set_tx_packet
15239
 
15240
task check_tx_packet;
15241
  input  [31:0] txpnt_wb;  // source
15242
  input  [31:0] txpnt_phy; // destination
15243
  input  [15:0] len;
15244
  output [31:0] failure;
15245
  integer       i, data_wb, data_phy;
15246
  reg    [31:0] addr_wb, addr_phy;
15247
  reg    [31:0] failure;
15248
  reg           delta_t;
15249
begin
15250
  addr_wb = txpnt_wb;
15251
  addr_phy = txpnt_phy;
15252
  delta_t = 0;
15253
  failure = 0;
15254 209 tadejm
  #1;
15255 169 mohor
  // First write might not be word allign.
15256
  if(addr_wb[1:0] == 1)
15257
  begin
15258
    wb_slave.rd_mem(addr_wb - 1, data_wb, 4'h7);
15259
    data_phy[31:24] = 0;
15260
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0]];
15261
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + 1];
15262
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 2];
15263
    i = 3;
15264
    if (data_phy[23:0] !== data_wb[23:0])
15265
    begin
15266
      `TIME;
15267 209 tadejm
      $display("*E Wrong 1. word (3 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[23:0], data_wb[23:0]);
15268
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
15269 169 mohor
      failure = 1;
15270
    end
15271
  end
15272
  else if (addr_wb[1:0] == 2)
15273
  begin
15274
    wb_slave.rd_mem(addr_wb - 2, data_wb, 4'h3);
15275
    data_phy[31:16] = 0;
15276
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0]];
15277
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 1];
15278
    i = 2;
15279
    if (data_phy[15:0] !== data_wb[15:0])
15280
    begin
15281
      `TIME;
15282 209 tadejm
      $display("*E Wrong 1. word (2 bytes) of TX packet! phy: %0h, wb: %0h", data_phy[15:0], data_wb[15:0]);
15283
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
15284 169 mohor
      failure = 1;
15285
    end
15286
  end
15287
  else if (addr_wb[1:0] == 3)
15288
  begin
15289
    wb_slave.rd_mem(addr_wb - 3, data_wb, 4'h1);
15290
    data_phy[31: 8] = 0;
15291
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0]];
15292
    i = 1;
15293
    if (data_phy[7:0] !== data_wb[7:0])
15294
    begin
15295
      `TIME;
15296 209 tadejm
      $display("*E Wrong 1. word (1 byte) of TX packet! phy: %0h, wb: %0h", data_phy[7:0], data_wb[7:0]);
15297
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
15298 169 mohor
      failure = 1;
15299
    end
15300
  end
15301
  else
15302
    i = 0;
15303
  delta_t = !delta_t;
15304 209 tadejm
  #1;
15305 169 mohor
  for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not checked
15306
  begin
15307
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
15308
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
15309
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
15310
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
15311
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
15312
    if (data_phy[31:0] !== data_wb[31:0])
15313
    begin
15314
      `TIME;
15315 209 tadejm
      $display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
15316
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
15317 169 mohor
      failure = failure + 1;
15318
    end
15319
  end
15320
  delta_t = !delta_t;
15321 209 tadejm
  #1;
15322 169 mohor
  // Last word
15323
  if((len - i) == 3)
15324
  begin
15325
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hE);
15326
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
15327
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
15328
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
15329
    data_phy[ 7: 0] = 0;
15330
    if (data_phy[31:8] !== data_wb[31:8])
15331
    begin
15332
      `TIME;
15333 209 tadejm
      $display("*E Wrong %d. word (3 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
15334
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
15335 169 mohor
      failure = failure + 1;
15336
    end
15337
  end
15338
  else if((len - i) == 2)
15339
  begin
15340
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hC);
15341
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
15342
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
15343
    data_phy[15: 8] = 0;
15344
    data_phy[ 7: 0] = 0;
15345
    if (data_phy[31:16] !== data_wb[31:16])
15346
    begin
15347
      `TIME;
15348 209 tadejm
      $display("*E Wrong %d. word (2 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
15349
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
15350 169 mohor
      failure = failure + 1;
15351
    end
15352
  end
15353
  else if((len - i) == 1)
15354
  begin
15355
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'h8);
15356
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
15357
    data_phy[23:16] = 0;
15358
    data_phy[15: 8] = 0;
15359
    data_phy[ 7: 0] = 0;
15360
    if (data_phy[31:24] !== data_wb[31:24])
15361
    begin
15362
      `TIME;
15363 209 tadejm
      $display("*E Wrong %d. word (1 byte) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
15364
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
15365 169 mohor
      failure = failure + 1;
15366
    end
15367
  end
15368
  else if((len - i) == 4)
15369
  begin
15370
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
15371
    data_phy[31:24] = eth_phy.tx_mem[addr_phy[21:0] + i];
15372
    data_phy[23:16] = eth_phy.tx_mem[addr_phy[21:0] + i + 1];
15373
    data_phy[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + i + 2];
15374
    data_phy[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + i + 3];
15375
    if (data_phy[31:0] !== data_wb[31:0])
15376
    begin
15377
      `TIME;
15378 209 tadejm
      $display("*E Wrong %d. word (4 bytes) of TX packet! phy: %0h, wb: %0h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
15379
      $display("     address phy: %0h, address wb: %0h", addr_phy, addr_wb);
15380 169 mohor
      failure = failure + 1;
15381
    end
15382
  end
15383
  else
15384
    $display("(%0t)(%m) ERROR", $time);
15385
  delta_t = !delta_t;
15386
end
15387
endtask // check_tx_packet
15388
 
15389
task set_rx_packet;
15390
  input  [31:0] rxpnt;
15391
  input  [15:0] len;
15392
  input         plus_dribble_nibble; // if length is longer for one nibble
15393
  input  [47:0] eth_dest_addr;
15394
  input  [47:0] eth_source_addr;
15395
  input  [15:0] eth_type_len;
15396
  input  [7:0]  eth_start_data;
15397
  integer       i, sd;
15398
  reg    [47:0] dest_addr;
15399
  reg    [47:0] source_addr;
15400
  reg    [15:0] type_len;
15401
  reg    [21:0] buffer;
15402
  reg           delta_t;
15403
begin
15404
  buffer = rxpnt[21:0];
15405
  dest_addr = eth_dest_addr;
15406
  source_addr = eth_source_addr;
15407
  type_len = eth_type_len;
15408
  sd = eth_start_data;
15409
  delta_t = 0;
15410
  for(i = 0; i < len; i = i + 1)
15411
  begin
15412
    if (i < 6)
15413
    begin
15414
      eth_phy.rx_mem[buffer] = dest_addr[47:40];
15415
      dest_addr = dest_addr << 8;
15416
    end
15417
    else if (i < 12)
15418
    begin
15419
      eth_phy.rx_mem[buffer] = source_addr[47:40];
15420
      source_addr = source_addr << 8;
15421
    end
15422
    else if (i < 14)
15423
    begin
15424
      eth_phy.rx_mem[buffer] = type_len[15:8];
15425
      type_len = type_len << 8;
15426
    end
15427
    else
15428
    begin
15429
      eth_phy.rx_mem[buffer] = sd[7:0];
15430
      sd = sd + 1;
15431
    end
15432
    buffer = buffer + 1;
15433
  end
15434
  delta_t = !delta_t;
15435
  if (plus_dribble_nibble)
15436
    eth_phy.rx_mem[buffer] = {4'h0, 4'hD /*sd[3:0]*/};
15437
  delta_t = !delta_t;
15438
end
15439
endtask // set_rx_packet
15440
 
15441 243 tadejm
task set_rx_addr_type;
15442
  input  [31:0] rxpnt;
15443
  input  [47:0] eth_dest_addr;
15444
  input  [47:0] eth_source_addr;
15445
  input  [15:0] eth_type_len;
15446
  integer       i;
15447
  reg    [47:0] dest_addr;
15448
  reg    [47:0] source_addr;
15449
  reg    [15:0] type_len;
15450
  reg    [21:0] buffer;
15451
  reg           delta_t;
15452
begin
15453
  buffer = rxpnt[21:0];
15454
  dest_addr = eth_dest_addr;
15455
  source_addr = eth_source_addr;
15456
  type_len = eth_type_len;
15457
  delta_t = 0;
15458
  for(i = 0; i < 14; i = i + 1)
15459
  begin
15460
    if (i < 6)
15461
    begin
15462
      eth_phy.rx_mem[buffer] = dest_addr[47:40];
15463
      dest_addr = dest_addr << 8;
15464
    end
15465
    else if (i < 12)
15466
    begin
15467
      eth_phy.rx_mem[buffer] = source_addr[47:40];
15468
      source_addr = source_addr << 8;
15469
    end
15470
    else // if (i < 14)
15471
    begin
15472
      eth_phy.rx_mem[buffer] = type_len[15:8];
15473
      type_len = type_len << 8;
15474
    end
15475
    buffer = buffer + 1;
15476
  end
15477
  delta_t = !delta_t;
15478
end
15479
endtask // set_rx_addr_type
15480
 
15481 169 mohor
task check_rx_packet;
15482
  input  [31:0] rxpnt_phy; // source
15483
  input  [31:0] rxpnt_wb;  // destination
15484
  input  [15:0] len;
15485
  input         plus_dribble_nibble; // if length is longer for one nibble
15486
  input         successful_dribble_nibble; // if additional nibble is stored into memory
15487
  output [31:0] failure;
15488
  integer       i, data_wb, data_phy;
15489
  reg    [31:0] addr_wb, addr_phy;
15490
  reg    [31:0] failure;
15491
  reg    [21:0] buffer;
15492
  reg           delta_t;
15493
begin
15494
  addr_phy = rxpnt_phy;
15495
  addr_wb = rxpnt_wb;
15496
  delta_t = 0;
15497
  failure = 0;
15498
 
15499
  // First write might not be word allign.
15500
  if(addr_wb[1:0] == 1)
15501
  begin
15502
    wb_slave.rd_mem(addr_wb - 1, data_wb, 4'h7);
15503
    data_phy[31:24] = 0;
15504
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0]];
15505
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + 1];
15506
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 2];
15507
    i = 3;
15508
    if (data_phy[23:0] !== data_wb[23:0])
15509
    begin
15510
      `TIME;
15511 243 tadejm
      $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
15512
      $display("*E Wrong 1. word (3 bytes) of RX packet! phy = %h, wb = %h", data_phy[23:0], data_wb[23:0]);
15513 169 mohor
      failure = 1;
15514
    end
15515
  end
15516
  else if (addr_wb[1:0] == 2)
15517
  begin
15518
    wb_slave.rd_mem(addr_wb - 2, data_wb, 4'h3);
15519
    data_phy[31:16] = 0;
15520
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0]];
15521
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + 1];
15522
    i = 2;
15523
    if (data_phy[15:0] !== data_wb[15:0])
15524
    begin
15525
      `TIME;
15526 243 tadejm
      $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
15527
      $display("*E Wrong 1. word (2 bytes) of RX packet! phy = %h, wb = %h", data_phy[15:0], data_wb[15:0]);
15528 169 mohor
      failure = 1;
15529
    end
15530
  end
15531
  else if (addr_wb[1:0] == 3)
15532
  begin
15533
    wb_slave.rd_mem(addr_wb - 3, data_wb, 4'h1);
15534
    data_phy[31: 8] = 0;
15535
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0]];
15536
    i = 1;
15537
    if (data_phy[7:0] !== data_wb[7:0])
15538
    begin
15539
      `TIME;
15540 243 tadejm
      $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
15541
      $display("*E Wrong 1. word (1 byte) of RX packet! phy = %h, wb = %h", data_phy[7:0], data_wb[7:0]);
15542 169 mohor
      failure = 1;
15543
    end
15544
  end
15545
  else
15546
    i = 0;
15547
  delta_t = !delta_t;
15548
 
15549
  for(i = i; i < (len - 4); i = i + 4) // Last 0-3 bytes are not checked
15550
  begin
15551
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
15552
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
15553
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
15554
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
15555
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
15556
    if (data_phy[31:0] !== data_wb[31:0])
15557
    begin
15558
      `TIME;
15559 243 tadejm
      if (i == 0)
15560
        $display("   addr_phy = %h, addr_wb = %h", rxpnt_phy, rxpnt_wb);
15561
      $display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
15562 169 mohor
      failure = failure + 1;
15563
    end
15564
  end
15565
  delta_t = !delta_t;
15566
 
15567
  // Last word
15568
  if((len - i) == 3)
15569
  begin
15570
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
15571
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
15572
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
15573
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
15574
    if (plus_dribble_nibble)
15575
      data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
15576
    else
15577
      data_phy[ 7: 0] = 0;
15578
    if (data_phy[31:8] !== data_wb[31:8])
15579
    begin
15580
      `TIME;
15581 243 tadejm
      $display("*E Wrong %0d. word (3 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:8], data_wb[31:8]);
15582 169 mohor
      failure = failure + 1;
15583
    end
15584
    if (plus_dribble_nibble && successful_dribble_nibble)
15585
    begin
15586
      if (data_phy[3:0] !== data_wb[3:0])
15587 116 mohor
      begin
15588 169 mohor
        `TIME;
15589 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
15590 169 mohor
        failure = failure + 1;
15591 116 mohor
      end
15592 169 mohor
    end
15593
    else if (plus_dribble_nibble && !successful_dribble_nibble)
15594
    begin
15595
      if (data_phy[3:0] === data_wb[3:0])
15596 116 mohor
      begin
15597 169 mohor
        `TIME;
15598 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (3 bytes) of RX packet!", ((i/4)+1));
15599 169 mohor
        failure = failure + 1;
15600 116 mohor
      end
15601 169 mohor
    end
15602
  end
15603
  else if((len - i) == 2)
15604
  begin
15605
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hE);
15606
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
15607
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
15608
    if (plus_dribble_nibble)
15609
      data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
15610
    else
15611
      data_phy[15: 8] = 0;
15612
    data_phy[ 7: 0] = 0;
15613
    if (data_phy[31:16] !== data_wb[31:16])
15614
    begin
15615
      `TIME;
15616 243 tadejm
      $display("*E Wrong %0d. word (2 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:16], data_wb[31:16]);
15617 169 mohor
      failure = failure + 1;
15618
    end
15619
    if (plus_dribble_nibble && successful_dribble_nibble)
15620
    begin
15621
      if (data_phy[11:8] !== data_wb[11:8])
15622
      begin
15623
        `TIME;
15624 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
15625 169 mohor
        failure = failure + 1;
15626
      end
15627
    end
15628
    else if (plus_dribble_nibble && !successful_dribble_nibble)
15629
    begin
15630
      if (data_phy[11:8] === data_wb[11:8])
15631
      begin
15632
        `TIME;
15633 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (2 bytes) of RX packet!", ((i/4)+1));
15634 169 mohor
        failure = failure + 1;
15635
      end
15636
    end
15637
  end
15638
  else if((len - i) == 1)
15639
  begin
15640
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hC);
15641
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
15642
    if (plus_dribble_nibble)
15643
      data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
15644
    else
15645
      data_phy[23:16] = 0;
15646
    data_phy[15: 8] = 0;
15647
    data_phy[ 7: 0] = 0;
15648
    if (data_phy[31:24] !== data_wb[31:24])
15649
    begin
15650
      `TIME;
15651 243 tadejm
      $display("*E Wrong %0d. word (1 byte) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:24], data_wb[31:24]);
15652 169 mohor
      failure = failure + 1;
15653
    end
15654
    if (plus_dribble_nibble && successful_dribble_nibble)
15655
    begin
15656
      if (data_phy[19:16] !== data_wb[19:16])
15657
      begin
15658
        `TIME;
15659 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
15660 169 mohor
        failure = failure + 1;
15661
      end
15662
    end
15663
    else if (plus_dribble_nibble && !successful_dribble_nibble)
15664
    begin
15665
      if (data_phy[19:16] === data_wb[19:16])
15666
      begin
15667
        `TIME;
15668 243 tadejm
        $display("*E Wrong dribble nibble in %0d. word (1 byte) of RX packet!", ((i/4)+1));
15669 169 mohor
        failure = failure + 1;
15670
      end
15671
    end
15672
  end
15673
  else if((len - i) == 4)
15674
  begin
15675
    wb_slave.rd_mem(addr_wb + i, data_wb, 4'hF);
15676
    data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i];
15677
    data_phy[23:16] = eth_phy.rx_mem[addr_phy[21:0] + i + 1];
15678
    data_phy[15: 8] = eth_phy.rx_mem[addr_phy[21:0] + i + 2];
15679
    data_phy[ 7: 0] = eth_phy.rx_mem[addr_phy[21:0] + i + 3];
15680
    if (data_phy[31:0] !== data_wb[31:0])
15681
    begin
15682
      `TIME;
15683 243 tadejm
      $display("*E Wrong %0d. word (4 bytes) of RX packet! phy = %h, wb = %h", ((i/4)+1), data_phy[31:0], data_wb[31:0]);
15684 169 mohor
      failure = failure + 1;
15685
    end
15686
    if (plus_dribble_nibble)
15687
    begin
15688
      wb_slave.rd_mem(addr_wb + i + 4, data_wb, 4'h8);
15689
      data_phy[31:24] = eth_phy.rx_mem[addr_phy[21:0] + i + 4];
15690
      if (successful_dribble_nibble)
15691
      begin
15692
        if (data_phy[27:24] !== data_wb[27:24])
15693
        begin
15694
          `TIME;
15695 243 tadejm
          $display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
15696 169 mohor
          failure = failure + 1;
15697
        end
15698
      end
15699
      else
15700
      begin
15701
        if (data_phy[27:24] === data_wb[27:24])
15702
        begin
15703
          `TIME;
15704 243 tadejm
          $display("*E Wrong dribble nibble in %0d. word (0 bytes) of RX packet!", ((i/4)+2));
15705 169 mohor
          failure = failure + 1;
15706
        end
15707
      end
15708
    end
15709
  end
15710
  else
15711
    $display("(%0t)(%m) ERROR", $time);
15712
  delta_t = !delta_t;
15713
end
15714
endtask // check_rx_packet
15715 116 mohor
 
15716 169 mohor
//////////////////////////////////////////////////////////////
15717
// Ethernet CRC Basic tasks
15718
//////////////////////////////////////////////////////////////
15719
 
15720
task append_tx_crc;
15721
  input  [31:0] txpnt_wb;  // source
15722
  input  [15:0] len; // length in bytes without CRC
15723
  input         negated_crc; // if appended CRC is correct or not
15724
  reg    [31:0] crc;
15725
  reg    [31:0] addr_wb;
15726
  reg           delta_t;
15727
begin
15728 243 tadejm
  addr_wb = txpnt_wb + {16'h0, len};
15729 169 mohor
  delta_t = 0;
15730
  // calculate CRC from prepared packet
15731
  paralel_crc_mac(txpnt_wb, {16'h0, len}, 1'b0, crc);
15732
  if (negated_crc)
15733
    crc = ~crc;
15734
  delta_t = !delta_t;
15735
 
15736
  // Write might not be word allign.
15737
  if (addr_wb[1:0] == 1)
15738
  begin
15739
    wb_slave.wr_mem(addr_wb - 1, {8'h0, crc[7:0], crc[15:8], crc[23:16]}, 4'h7);
15740
    wb_slave.wr_mem(addr_wb + 3, {crc[31:24], 24'h0}, 4'h8);
15741 116 mohor
  end
15742 169 mohor
  else if (addr_wb[1:0] == 2)
15743
  begin
15744
    wb_slave.wr_mem(addr_wb - 2, {16'h0, crc[7:0], crc[15:8]}, 4'h3);
15745
    wb_slave.wr_mem(addr_wb + 2, {crc[23:16], crc[31:24], 16'h0}, 4'hC);
15746
  end
15747
  else if (addr_wb[1:0] == 3)
15748
  begin
15749
    wb_slave.wr_mem(addr_wb - 3, {24'h0, crc[7:0]}, 4'h1);
15750
    wb_slave.wr_mem(addr_wb + 1, {crc[15:8], crc[23:16], crc[31:24], 8'h0}, 4'hE);
15751
  end
15752
  else
15753
  begin
15754
    wb_slave.wr_mem(addr_wb, {crc[7:0], crc[15:8], crc[23:16], crc[31:24]}, 4'hF);
15755
  end
15756
  delta_t = !delta_t;
15757
end
15758
endtask // append_tx_crc
15759 116 mohor
 
15760 169 mohor
task check_tx_crc; // used to check crc added to TX packets by MAC
15761
  input  [31:0] txpnt_phy; // destination
15762
  input  [15:0] len; // length in bytes without CRC
15763
  input         negated_crc; // if appended CRC is correct or not
15764
  output [31:0] failure;
15765
  reg    [31:0] failure;
15766
  reg    [31:0] crc_calc;
15767
  reg    [31:0] crc;
15768
  reg    [31:0] addr_phy;
15769
  reg           delta_t;
15770
begin
15771
  addr_phy = txpnt_phy;
15772
  failure = 0;
15773
  // calculate CRC from sent packet
15774
//  serial_crc_phy_tx(addr_phy, {16'h0, len}, 1'b0, crc_calc);
15775
//#10;
15776
  paralel_crc_phy_tx(addr_phy, {16'h0, len}, 1'b0, crc_calc);
15777 209 tadejm
  #1;
15778 169 mohor
  addr_phy = addr_phy + len;
15779
  // Read CRC - BIG endian
15780
  crc[31:24] = eth_phy.tx_mem[addr_phy[21:0]];
15781
  crc[23:16] = eth_phy.tx_mem[addr_phy[21:0] + 1];
15782
  crc[15: 8] = eth_phy.tx_mem[addr_phy[21:0] + 2];
15783
  crc[ 7: 0] = eth_phy.tx_mem[addr_phy[21:0] + 3];
15784
 
15785
  delta_t = !delta_t;
15786
  if (negated_crc)
15787
  begin
15788
    if ((~crc_calc) !== crc)
15789
    begin
15790
      `TIME;
15791
      $display("*E Negated CRC was not successfuly transmitted!");
15792
      failure = failure + 1;
15793
    end
15794
  end
15795
  else
15796
  begin
15797
    if (crc_calc !== crc)
15798
    begin
15799
      `TIME;
15800 209 tadejm
      $display("*E Transmitted CRC was not correct; crc_calc: %0h, crc_mem: %0h", crc_calc, crc);
15801 169 mohor
      failure = failure + 1;
15802
    end
15803
  end
15804
  delta_t = !delta_t;
15805
end
15806
endtask // check_tx_crc
15807
 
15808
task append_rx_crc;
15809
  input  [31:0] rxpnt_phy; // source
15810
  input  [15:0] len; // length in bytes without CRC
15811
  input         plus_dribble_nibble; // if length is longer for one nibble
15812
  input         negated_crc; // if appended CRC is correct or not
15813
  reg    [31:0] crc;
15814
  reg    [7:0]  tmp;
15815
  reg    [31:0] addr_phy;
15816
  reg           delta_t;
15817
begin
15818
  addr_phy = rxpnt_phy + len;
15819
  delta_t = 0;
15820
  // calculate CRC from prepared packet
15821
  paralel_crc_phy_rx(rxpnt_phy, {16'h0, len}, plus_dribble_nibble, crc);
15822
  if (negated_crc)
15823
    crc = ~crc;
15824
  delta_t = !delta_t;
15825
 
15826
  if (plus_dribble_nibble)
15827
  begin
15828
    tmp = eth_phy.rx_mem[addr_phy];
15829 209 tadejm
    eth_phy.rx_mem[addr_phy]     = {crc[27:24], tmp[3:0]};
15830
    eth_phy.rx_mem[addr_phy + 1] = {crc[19:16], crc[31:28]};
15831
    eth_phy.rx_mem[addr_phy + 2] = {crc[11:8], crc[23:20]};
15832
    eth_phy.rx_mem[addr_phy + 3] = {crc[3:0], crc[15:12]};
15833
    eth_phy.rx_mem[addr_phy + 4] = {4'h0, crc[7:4]};
15834 169 mohor
  end
15835
  else
15836
  begin
15837 209 tadejm
    eth_phy.rx_mem[addr_phy]     = crc[31:24];
15838
    eth_phy.rx_mem[addr_phy + 1] = crc[23:16];
15839
    eth_phy.rx_mem[addr_phy + 2] = crc[15:8];
15840
    eth_phy.rx_mem[addr_phy + 3] = crc[7:0];
15841 169 mohor
  end
15842
end
15843
endtask // append_rx_crc
15844
 
15845
// paralel CRC checking for PHY TX
15846
task paralel_crc_phy_tx;
15847
  input  [31:0] start_addr; // start address
15848
  input  [31:0] len; // length of frame in Bytes without CRC length
15849
  input         plus_dribble_nibble; // if length is longer for one nibble
15850
  output [31:0] crc_out;
15851
  reg    [21:0] addr_cnt; // only 22 address lines
15852
  integer       word_cnt;
15853
  integer       nibble_cnt;
15854
  reg    [31:0] load_reg;
15855
  reg           delta_t;
15856
  reg    [31:0] crc_next;
15857
  reg    [31:0] crc;
15858
  reg           crc_error;
15859
  reg     [3:0] data_in;
15860
  integer       i;
15861
begin
15862
  #1 addr_cnt = start_addr[21:0];
15863
  word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
15864
  crc = 32'hFFFF_FFFF; // INITIAL value
15865
  delta_t = 0;
15866
  // length must include 4 bytes of ZEROs, to generate CRC
15867
  // get number of nibbles from Byte length (2^1 = 2)
15868
  if (plus_dribble_nibble)
15869
    nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
15870
  else
15871
    nibble_cnt = ((len + 4) << 1);
15872
  // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
15873
  load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
15874
  addr_cnt = addr_cnt + 1;
15875
  load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
15876
  addr_cnt = addr_cnt + 1;
15877
  load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
15878
  addr_cnt = addr_cnt + 1;
15879
  load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
15880
  addr_cnt = addr_cnt + 1;
15881
  while (nibble_cnt > 0)
15882
  begin
15883
    // wait for delta time
15884
    delta_t = !delta_t;
15885
    // shift data in
15886
 
15887
    if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
15888
      data_in[3:0] = 4'h0;
15889
    else
15890
 
15891
      data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
15892
    crc_next[0]  = (data_in[0] ^ crc[28]);
15893
    crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
15894
    crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
15895
    crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
15896
    crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
15897
    crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
15898
    crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
15899
    crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
15900
    crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
15901
    crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
15902
    crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
15903
    crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
15904
    crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
15905
    crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
15906
    crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
15907
    crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
15908
    crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
15909
    crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
15910
    crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
15911
    crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
15912
    crc_next[20] =  crc[16];
15913
    crc_next[21] =  crc[17];
15914
    crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
15915
    crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
15916
    crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
15917
    crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
15918
    crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
15919
    crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
15920
    crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
15921
    crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
15922
    crc_next[30] =  crc[26];
15923
    crc_next[31] =  crc[27];
15924
 
15925
    crc = crc_next;
15926
    crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
15927
    case (nibble_cnt)
15928
    9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
15929
                  !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
15930
                  !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
15931
                  !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
15932
    default: crc_out = crc_out;
15933
    endcase
15934
    // wait for delta time
15935
    delta_t = !delta_t;
15936
    // increment address and load new data
15937
    if ((word_cnt+3) == 7)//4)
15938
    begin
15939
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
15940
      load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
15941
      addr_cnt = addr_cnt + 1;
15942
      load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
15943
      addr_cnt = addr_cnt + 1;
15944
      load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
15945
      addr_cnt = addr_cnt + 1;
15946
      load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
15947
      addr_cnt = addr_cnt + 1;
15948
    end
15949
    // set new load bit position
15950
    if((word_cnt+3) == 31)
15951
      word_cnt = 16;
15952
    else if ((word_cnt+3) == 23)
15953
      word_cnt = 8;
15954
    else if ((word_cnt+3) == 15)
15955
      word_cnt = 0;
15956
    else if ((word_cnt+3) == 7)
15957
      word_cnt = 24;
15958
    else
15959
      word_cnt = word_cnt + 4;// - 4;
15960
    // decrement nibble counter
15961
    nibble_cnt = nibble_cnt - 1;
15962
    // wait for delta time
15963
    delta_t = !delta_t;
15964
  end // while
15965
  #1;
15966
end
15967
endtask // paralel_crc_phy_tx
15968
 
15969
// paralel CRC calculating for PHY RX
15970
task paralel_crc_phy_rx;
15971
  input  [31:0] start_addr; // start address
15972
  input  [31:0] len; // length of frame in Bytes without CRC length
15973
  input         plus_dribble_nibble; // if length is longer for one nibble
15974 209 tadejm
  output [31:0] crc_out;
15975 169 mohor
  reg    [21:0] addr_cnt; // only 22 address lines
15976
  integer       word_cnt;
15977 209 tadejm
  integer       nibble_cnt;
15978 169 mohor
  reg    [31:0] load_reg;
15979
  reg           delta_t;
15980 209 tadejm
  reg    [31:0] crc_next;
15981
  reg    [31:0] crc;
15982
  reg           crc_error;
15983
  reg     [3:0] data_in;
15984
  integer       i;
15985 169 mohor
begin
15986
  #1 addr_cnt = start_addr[21:0];
15987 209 tadejm
  word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
15988
  crc = 32'hFFFF_FFFF; // INITIAL value
15989 169 mohor
  delta_t = 0;
15990
  // length must include 4 bytes of ZEROs, to generate CRC
15991 209 tadejm
  // get number of nibbles from Byte length (2^1 = 2)
15992 169 mohor
  if (plus_dribble_nibble)
15993 209 tadejm
    nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
15994 169 mohor
  else
15995 209 tadejm
    nibble_cnt = ((len + 4) << 1);
15996
  // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
15997 169 mohor
  load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
15998
  addr_cnt = addr_cnt + 1;
15999
  load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
16000
  addr_cnt = addr_cnt + 1;
16001 209 tadejm
  load_reg[15: 8] = eth_phy.rx_mem[addr_cnt];
16002 169 mohor
  addr_cnt = addr_cnt + 1;
16003 209 tadejm
  load_reg[ 7: 0] = eth_phy.rx_mem[addr_cnt];
16004
  addr_cnt = addr_cnt + 1;
16005
  while (nibble_cnt > 0)
16006 169 mohor
  begin
16007
    // wait for delta time
16008
    delta_t = !delta_t;
16009
    // shift data in
16010 209 tadejm
 
16011
    if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
16012
      data_in[3:0] = 4'h0;
16013 169 mohor
    else
16014 209 tadejm
 
16015
      data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
16016
    crc_next[0]  = (data_in[0] ^ crc[28]);
16017
    crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
16018
    crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
16019
    crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
16020
    crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
16021
    crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
16022
    crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
16023
    crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
16024
    crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
16025
    crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
16026
    crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
16027
    crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
16028
    crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
16029
    crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
16030
    crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
16031
    crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
16032
    crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
16033
    crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
16034
    crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
16035
    crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
16036
    crc_next[20] =  crc[16];
16037
    crc_next[21] =  crc[17];
16038
    crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
16039
    crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
16040
    crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
16041
    crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
16042
    crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
16043
    crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
16044
    crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
16045
    crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
16046
    crc_next[30] =  crc[26];
16047
    crc_next[31] =  crc[27];
16048
 
16049
    crc = crc_next;
16050
    crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
16051
    case (nibble_cnt)
16052
    9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
16053
                  !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
16054
                  !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
16055
                  !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
16056
    default: crc_out = crc_out;
16057
    endcase
16058 169 mohor
    // wait for delta time
16059
    delta_t = !delta_t;
16060
    // increment address and load new data
16061 209 tadejm
    if ((word_cnt+3) == 7)//4)
16062 169 mohor
    begin
16063 209 tadejm
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
16064 169 mohor
      load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
16065
      addr_cnt = addr_cnt + 1;
16066
      load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
16067
      addr_cnt = addr_cnt + 1;
16068 209 tadejm
      load_reg[15: 8] = eth_phy.rx_mem[addr_cnt];
16069 169 mohor
      addr_cnt = addr_cnt + 1;
16070 209 tadejm
      load_reg[ 7: 0] = eth_phy.rx_mem[addr_cnt];
16071
      addr_cnt = addr_cnt + 1;
16072 169 mohor
    end
16073
    // set new load bit position
16074 209 tadejm
    if((word_cnt+3) == 31)
16075 169 mohor
      word_cnt = 16;
16076 209 tadejm
    else if ((word_cnt+3) == 23)
16077 169 mohor
      word_cnt = 8;
16078 209 tadejm
    else if ((word_cnt+3) == 15)
16079 169 mohor
      word_cnt = 0;
16080 209 tadejm
    else if ((word_cnt+3) == 7)
16081 169 mohor
      word_cnt = 24;
16082
    else
16083 209 tadejm
      word_cnt = word_cnt + 4;// - 4;
16084
    // decrement nibble counter
16085
    nibble_cnt = nibble_cnt - 1;
16086 169 mohor
    // wait for delta time
16087
    delta_t = !delta_t;
16088
  end // while
16089
  #1;
16090
end
16091
endtask // paralel_crc_phy_rx
16092
 
16093
// paralel CRC checking for MAC
16094
task paralel_crc_mac;
16095
  input  [31:0] start_addr; // start address
16096
  input  [31:0] len; // length of frame in Bytes without CRC length
16097
  input         plus_dribble_nibble; // if length is longer for one nibble
16098 209 tadejm
  output [31:0] crc_out;
16099
 
16100
  reg    [21:0] addr_cnt; // only 22 address lines
16101 169 mohor
  integer       word_cnt;
16102 209 tadejm
  integer       nibble_cnt;
16103 169 mohor
  reg    [31:0] load_reg;
16104
  reg           delta_t;
16105 209 tadejm
  reg    [31:0] crc_next;
16106
  reg    [31:0] crc;
16107
  reg           crc_error;
16108
  reg     [3:0] data_in;
16109
  integer       i;
16110 169 mohor
begin
16111
  #1 addr_cnt = start_addr[19:0];
16112
  // set starting point depending with which byte frame starts (e.g. if addr_cnt[1:0] == 0, then
16113
  //   MSB of the packet must be written to the LSB of Big ENDIAN Word [31:24])
16114
  if (addr_cnt[1:0] == 2'h1)
16115
    word_cnt = 16; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
16116
  else if (addr_cnt[1:0] == 2'h2)
16117
    word_cnt = 8; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
16118
  else if (addr_cnt[1:0] == 2'h3)
16119
    word_cnt = 0; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
16120
  else
16121
    word_cnt = 24; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
16122 209 tadejm
  crc = 32'hFFFF_FFFF; // INITIAL value
16123 169 mohor
  delta_t = 0;
16124
  // length must include 4 bytes of ZEROs, to generate CRC
16125 209 tadejm
  // get number of nibbles from Byte length (2^1 = 2)
16126 169 mohor
  if (plus_dribble_nibble)
16127 209 tadejm
    nibble_cnt = ((len + 4) << 1) + 1'b1; // one nibble longer
16128 169 mohor
  else
16129 209 tadejm
    nibble_cnt = ((len + 4) << 1);
16130 169 mohor
  load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
16131 209 tadejm
  addr_cnt = addr_cnt + 4;
16132
  while (nibble_cnt > 0)
16133 169 mohor
  begin
16134
    // wait for delta time
16135
    delta_t = !delta_t;
16136
    // shift data in
16137 209 tadejm
 
16138
    if(nibble_cnt <= 8) // for additional 8 nibbles shift ZEROs in!
16139
      data_in[3:0] = 4'h0;
16140 169 mohor
    else
16141 209 tadejm
 
16142
      data_in[3:0] = {load_reg[word_cnt], load_reg[word_cnt+1], load_reg[word_cnt+2], load_reg[word_cnt+3]};
16143
    crc_next[0]  = (data_in[0] ^ crc[28]);
16144
    crc_next[1]  = (data_in[1] ^ data_in[0] ^ crc[28]    ^ crc[29]);
16145
    crc_next[2]  = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]);
16146
    crc_next[3]  = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]);
16147
    crc_next[4]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[0];
16148
    crc_next[5]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[1];
16149
    crc_next[6]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[ 2];
16150
    crc_next[7]  = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[3];
16151
    crc_next[8]  = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[4];
16152
    crc_next[9]  = (data_in[2] ^ data_in[1] ^ crc[29]    ^ crc[30]) ^ crc[5];
16153
    crc_next[10] = (data_in[3] ^ data_in[2] ^ data_in[0] ^ crc[28]  ^ crc[30] ^ crc[31]) ^ crc[6];
16154
    crc_next[11] = (data_in[3] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[31]) ^ crc[7];
16155
    crc_next[12] = (data_in[2] ^ data_in[1] ^ data_in[0] ^ crc[28]  ^ crc[29] ^ crc[30]) ^ crc[8];
16156
    crc_next[13] = (data_in[3] ^ data_in[2] ^ data_in[1] ^ crc[29]  ^ crc[30] ^ crc[31]) ^ crc[9];
16157
    crc_next[14] = (data_in[3] ^ data_in[2] ^ crc[30]    ^ crc[31]) ^ crc[10];
16158
    crc_next[15] = (data_in[3] ^ crc[31])   ^ crc[11];
16159
    crc_next[16] = (data_in[0] ^ crc[28])   ^ crc[12];
16160
    crc_next[17] = (data_in[1] ^ crc[29])   ^ crc[13];
16161
    crc_next[18] = (data_in[2] ^ crc[30])   ^ crc[14];
16162
    crc_next[19] = (data_in[3] ^ crc[31])   ^ crc[15];
16163
    crc_next[20] =  crc[16];
16164
    crc_next[21] =  crc[17];
16165
    crc_next[22] = (data_in[0] ^ crc[28])   ^ crc[18];
16166
    crc_next[23] = (data_in[1] ^ data_in[0] ^ crc[29]    ^ crc[28]) ^ crc[19];
16167
    crc_next[24] = (data_in[2] ^ data_in[1] ^ crc[30]    ^ crc[29]) ^ crc[20];
16168
    crc_next[25] = (data_in[3] ^ data_in[2] ^ crc[31]    ^ crc[30]) ^ crc[21];
16169
    crc_next[26] = (data_in[3] ^ data_in[0] ^ crc[31]    ^ crc[28]) ^ crc[22];
16170
    crc_next[27] = (data_in[1] ^ crc[29])   ^ crc[23];
16171
    crc_next[28] = (data_in[2] ^ crc[30])   ^ crc[24];
16172
    crc_next[29] = (data_in[3] ^ crc[31])   ^ crc[25];
16173
    crc_next[30] =  crc[26];
16174
    crc_next[31] =  crc[27];
16175
 
16176
    crc = crc_next;
16177
    crc_error = crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number
16178
    case (nibble_cnt)
16179
    9: crc_out = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
16180
                  !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
16181
                  !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
16182
                  !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
16183
    default: crc_out = crc_out;
16184
    endcase
16185 169 mohor
    // wait for delta time
16186
    delta_t = !delta_t;
16187 209 tadejm
    // increment address and load new data
16188
    if ((word_cnt+3) == 7)//4)
16189 169 mohor
    begin
16190 209 tadejm
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
16191
      load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
16192 169 mohor
      addr_cnt = addr_cnt + 4;
16193
    end
16194 209 tadejm
    // set new load bit position
16195
    if((word_cnt+3) == 31)
16196 169 mohor
      word_cnt = 16;
16197 209 tadejm
    else if ((word_cnt+3) == 23)
16198 169 mohor
      word_cnt = 8;
16199 209 tadejm
    else if ((word_cnt+3) == 15)
16200 169 mohor
      word_cnt = 0;
16201 209 tadejm
    else if ((word_cnt+3) == 7)
16202 169 mohor
      word_cnt = 24;
16203
    else
16204 209 tadejm
      word_cnt = word_cnt + 4;// - 4;
16205
    // decrement nibble counter
16206
    nibble_cnt = nibble_cnt - 1;
16207 169 mohor
    // wait for delta time
16208
    delta_t = !delta_t;
16209
  end // while
16210
  #1;
16211
end
16212
endtask // paralel_crc_mac
16213
 
16214
// serial CRC checking for PHY TX
16215
task serial_crc_phy_tx;
16216
  input  [31:0] start_addr; // start address
16217
  input  [31:0] len; // length of frame in Bytes without CRC length
16218
  input         plus_dribble_nibble; // if length is longer for one nibble
16219
  output [31:0] crc;
16220
  reg    [21:0] addr_cnt; // only 22 address lines
16221
  integer       word_cnt;
16222
  integer       bit_cnt;
16223
  reg    [31:0] load_reg;
16224
  reg    [31:0] crc_shift_reg;
16225
  reg    [31:0] crc_store_reg;
16226
  reg           delta_t;
16227
begin
16228
  #1 addr_cnt = start_addr[21:0];
16229
  word_cnt = 24; // 27; // start of the frame - nibble granularity (MSbit first)
16230
  crc_store_reg = 32'hFFFF_FFFF; // INITIAL value
16231
  delta_t = 0;
16232
  // length must include 4 bytes of ZEROs, to generate CRC
16233
  // get number of bits from Byte length (2^3 = 8)
16234
  if (plus_dribble_nibble)
16235
    bit_cnt = ((len + 4) << 3) + 3'h4; // one nibble longer
16236
  else
16237
    bit_cnt = ((len + 4) << 3);
16238
  // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
16239
  load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
16240
  addr_cnt = addr_cnt + 1;
16241
  load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
16242
  addr_cnt = addr_cnt + 1;
16243
  load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
16244
  addr_cnt = addr_cnt + 1;
16245
  load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
16246
  addr_cnt = addr_cnt + 1;
16247
#1;
16248
  while (bit_cnt > 0)
16249
  begin
16250
    // wait for delta time
16251
    delta_t = !delta_t;
16252
#1;
16253
    // shift data in
16254
 
16255
    if(bit_cnt <= 32) // for additional 32 bits shift ZEROs in!
16256
     crc_shift_reg[0] = 1'b0               ^ crc_store_reg[31];
16257
    else
16258
 
16259
     crc_shift_reg[0] = load_reg[word_cnt] ^ crc_store_reg[31];
16260
    crc_shift_reg[1]  = crc_store_reg[0]   ^ crc_store_reg[31];
16261
    crc_shift_reg[2]  = crc_store_reg[1]   ^ crc_store_reg[31];
16262
    crc_shift_reg[3]  = crc_store_reg[2];
16263
    crc_shift_reg[4]  = crc_store_reg[3]   ^ crc_store_reg[31];
16264
    crc_shift_reg[5]  = crc_store_reg[4]   ^ crc_store_reg[31];
16265
    crc_shift_reg[6]  = crc_store_reg[5];
16266
    crc_shift_reg[7]  = crc_store_reg[6]   ^ crc_store_reg[31];
16267
    crc_shift_reg[8]  = crc_store_reg[7]   ^ crc_store_reg[31];
16268
    crc_shift_reg[9]  = crc_store_reg[8];
16269
    crc_shift_reg[10] = crc_store_reg[9]   ^ crc_store_reg[31];
16270
    crc_shift_reg[11] = crc_store_reg[10]  ^ crc_store_reg[31];
16271
    crc_shift_reg[12] = crc_store_reg[11]  ^ crc_store_reg[31];
16272
    crc_shift_reg[13] = crc_store_reg[12];
16273
    crc_shift_reg[14] = crc_store_reg[13];
16274
    crc_shift_reg[15] = crc_store_reg[14];
16275
    crc_shift_reg[16] = crc_store_reg[15]  ^ crc_store_reg[31];
16276
    crc_shift_reg[17] = crc_store_reg[16];
16277
    crc_shift_reg[18] = crc_store_reg[17];
16278
    crc_shift_reg[19] = crc_store_reg[18];
16279
    crc_shift_reg[20] = crc_store_reg[19];
16280
    crc_shift_reg[21] = crc_store_reg[20];
16281
    crc_shift_reg[22] = crc_store_reg[21]  ^ crc_store_reg[31];
16282
    crc_shift_reg[23] = crc_store_reg[22]  ^ crc_store_reg[31];
16283
    crc_shift_reg[24] = crc_store_reg[23];
16284
    crc_shift_reg[25] = crc_store_reg[24];
16285
    crc_shift_reg[26] = crc_store_reg[25]  ^ crc_store_reg[31];
16286
    crc_shift_reg[27] = crc_store_reg[26];
16287
    crc_shift_reg[28] = crc_store_reg[27];
16288
    crc_shift_reg[29] = crc_store_reg[28];
16289
    crc_shift_reg[30] = crc_store_reg[29];
16290
    crc_shift_reg[31] = crc_store_reg[30];
16291
    // wait for delta time
16292
    delta_t = !delta_t;
16293
 
16294
    // store previous data
16295
    crc_store_reg = crc_shift_reg;
16296
 
16297
    // put CRC out
16298
    case (bit_cnt)
16299
    33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 1:
16300
    begin
16301
      crc = crc_store_reg;
16302
      crc = {!crc[24], !crc[25], !crc[26], !crc[27], !crc[28], !crc[29], !crc[30], !crc[31],
16303
             !crc[16], !crc[17], !crc[18], !crc[19], !crc[20], !crc[21], !crc[22], !crc[23],
16304
             !crc[ 8], !crc[ 9], !crc[10], !crc[11], !crc[12], !crc[13], !crc[14], !crc[15],
16305
             !crc[ 0], !crc[ 1], !crc[ 2], !crc[ 3], !crc[ 4], !crc[ 5], !crc[ 6], !crc[ 7]};
16306
    end
16307
    default: crc = crc;
16308
    endcase
16309
 
16310
    // increment address and load new data
16311
#1;
16312
    if (word_cnt == 7)//4)
16313
    begin
16314
      // because of MAGIC NUMBER nibbles are swapped [3:0] -> [0:3]
16315
      load_reg[31:24] = eth_phy.tx_mem[addr_cnt];
16316
//      load_reg[31:24] = {load_reg[28], load_reg[29], load_reg[30], load_reg[31], 
16317
//                         load_reg[24], load_reg[25], load_reg[26], load_reg[27]};
16318
      addr_cnt = addr_cnt + 1;
16319
      load_reg[23:16] = eth_phy.tx_mem[addr_cnt];
16320
//      load_reg[23:16] = {load_reg[20], load_reg[21], load_reg[22], load_reg[23], 
16321
//                         load_reg[16], load_reg[17], load_reg[18], load_reg[19]};
16322
      addr_cnt = addr_cnt + 1;
16323
      load_reg[15: 8] = eth_phy.tx_mem[addr_cnt];
16324
//      load_reg[15: 8] = {load_reg[12], load_reg[13], load_reg[14], load_reg[15], 
16325
//                         load_reg[ 8], load_reg[ 9], load_reg[10], load_reg[11]};
16326
      addr_cnt = addr_cnt + 1;
16327
      load_reg[ 7: 0] = eth_phy.tx_mem[addr_cnt];
16328
//      load_reg[ 7: 0] = {load_reg[ 4], load_reg[ 5], load_reg[ 6], load_reg[ 7], 
16329
//                         load_reg[ 0], load_reg[ 1], load_reg[ 2], load_reg[ 3]};
16330
      addr_cnt = addr_cnt + 1;
16331
    end
16332
#1;
16333
    // set new load bit position
16334
    if(word_cnt == 31)
16335
      word_cnt = 16;
16336
    else if (word_cnt == 23)
16337
      word_cnt = 8;
16338
    else if (word_cnt == 15)
16339
      word_cnt = 0;
16340
    else if (word_cnt == 7)
16341
      word_cnt = 24;
16342
 
16343
//   if(word_cnt == 24)
16344
//     word_cnt = 31;
16345
//   else if (word_cnt == 28)
16346
//     word_cnt = 19;
16347
//   else if (word_cnt == 16)
16348
//     word_cnt = 23;
16349
//   else if (word_cnt == 20)
16350
//     word_cnt = 11;
16351
//   else if(word_cnt == 8)
16352
//     word_cnt = 15;
16353
//   else if (word_cnt == 12)
16354
//     word_cnt = 3;
16355
//   else if (word_cnt == 0)
16356
//     word_cnt = 7;
16357
//   else if (word_cnt == 4)
16358
//     word_cnt = 27;
16359
    else
16360
      word_cnt = word_cnt + 1;// - 1;
16361
#1;
16362
    // decrement bit counter
16363
    bit_cnt = bit_cnt - 1;
16364
#1;
16365
    // wait for delta time
16366
    delta_t = !delta_t;
16367
  end // while
16368
 
16369
  #1;
16370
end
16371
endtask // serial_crc_phy_tx
16372
 
16373
// serial CRC calculating for PHY RX
16374
task serial_crc_phy_rx;
16375
  input  [31:0] start_addr; // start address
16376
  input  [31:0] len; // length of frame in Bytes without CRC length
16377
  input         plus_dribble_nibble; // if length is longer for one nibble
16378
  output [31:0] crc;
16379
  reg    [21:0] addr_cnt; // only 22 address lines
16380
  integer       word_cnt;
16381
  integer       bit_cnt;
16382
  reg    [31:0] load_reg;
16383
  reg    [31:0] crc_shift_reg;
16384
  reg    [31:0] crc_store_reg;
16385
  reg           delta_t;
16386
begin
16387
  #1 addr_cnt = start_addr[21:0];
16388
  word_cnt = 24; // start of the frame
16389
  crc_shift_reg = 0;
16390
  delta_t = 0;
16391
  // length must include 4 bytes of ZEROs, to generate CRC
16392
  // get number of bits from Byte length (2^3 = 8)
16393
  if (plus_dribble_nibble)
16394
    bit_cnt = ((len + 4) << 3) + 3'h4; // one nibble longer
16395
  else
16396
    bit_cnt = ((len + 4) << 3);
16397
  load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
16398
  addr_cnt = addr_cnt + 1;
16399
  load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
16400
  addr_cnt = addr_cnt + 1;
16401
  load_reg[15:8]  = eth_phy.rx_mem[addr_cnt];
16402
  addr_cnt = addr_cnt + 1;
16403
  load_reg[7:0]   = eth_phy.rx_mem[addr_cnt];
16404
 
16405
  while (bit_cnt > 0)
16406
  begin
16407
    // wait for delta time
16408
    delta_t = !delta_t;
16409
    // store previous data
16410
    crc_store_reg = crc_shift_reg;
16411
    // shift data in
16412
    if(bit_cnt <= 32) // for additional 32 bits shift ZEROs in!
16413
     crc_shift_reg[0] = 1'b0               ^ crc_store_reg[31];
16414
    else
16415
     crc_shift_reg[0] = load_reg[word_cnt] ^ crc_store_reg[31];
16416
    crc_shift_reg[1]  = crc_store_reg[0]   ^ crc_store_reg[31];
16417
    crc_shift_reg[2]  = crc_store_reg[1]   ^ crc_store_reg[31];
16418
    crc_shift_reg[3]  = crc_store_reg[2];
16419
    crc_shift_reg[4]  = crc_store_reg[3]   ^ crc_store_reg[31];
16420
    crc_shift_reg[5]  = crc_store_reg[4]   ^ crc_store_reg[31];
16421
    crc_shift_reg[6]  = crc_store_reg[5];
16422
    crc_shift_reg[7]  = crc_store_reg[6]   ^ crc_store_reg[31];
16423
    crc_shift_reg[8]  = crc_store_reg[7]   ^ crc_store_reg[31];
16424
    crc_shift_reg[9]  = crc_store_reg[8];
16425
    crc_shift_reg[10] = crc_store_reg[9]   ^ crc_store_reg[31];
16426
    crc_shift_reg[11] = crc_store_reg[10]  ^ crc_store_reg[31];
16427
    crc_shift_reg[12] = crc_store_reg[11]  ^ crc_store_reg[31];
16428
    crc_shift_reg[13] = crc_store_reg[12];
16429
    crc_shift_reg[14] = crc_store_reg[13];
16430
    crc_shift_reg[15] = crc_store_reg[14];
16431
    crc_shift_reg[16] = crc_store_reg[15]  ^ crc_store_reg[31];
16432
    crc_shift_reg[17] = crc_store_reg[16];
16433
    crc_shift_reg[18] = crc_store_reg[17];
16434
    crc_shift_reg[19] = crc_store_reg[18];
16435
    crc_shift_reg[20] = crc_store_reg[19];
16436
    crc_shift_reg[21] = crc_store_reg[20];
16437
    crc_shift_reg[22] = crc_store_reg[21]  ^ crc_store_reg[31];
16438
    crc_shift_reg[23] = crc_store_reg[22]  ^ crc_store_reg[31];
16439
    crc_shift_reg[24] = crc_store_reg[23];
16440
    crc_shift_reg[25] = crc_store_reg[24];
16441
    crc_shift_reg[26] = crc_store_reg[25]  ^ crc_store_reg[31];
16442
    crc_shift_reg[27] = crc_store_reg[26];
16443
    crc_shift_reg[28] = crc_store_reg[27];
16444
    crc_shift_reg[29] = crc_store_reg[28];
16445
    crc_shift_reg[30] = crc_store_reg[29];
16446
    crc_shift_reg[31] = crc_store_reg[30];
16447
    // wait for delta time
16448
    delta_t = !delta_t;
16449
    // increment address and load new data
16450
    if (word_cnt == 7)
16451
    begin
16452
      addr_cnt = addr_cnt + 1;
16453
      load_reg[31:24] = eth_phy.rx_mem[addr_cnt];
16454
      addr_cnt = addr_cnt + 1;
16455
      load_reg[23:16] = eth_phy.rx_mem[addr_cnt];
16456
      addr_cnt = addr_cnt + 1;
16457
      load_reg[15:8]  = eth_phy.rx_mem[addr_cnt];
16458
      addr_cnt = addr_cnt + 1;
16459
      load_reg[7:0]   = eth_phy.rx_mem[addr_cnt];
16460
    end
16461
    // set new load bit position
16462
    if(word_cnt == 31)
16463
      word_cnt = 16;
16464
    else if (word_cnt == 23)
16465
      word_cnt = 8;
16466
    else if (word_cnt == 15)
16467
      word_cnt = 0;
16468
    else if (word_cnt == 7)
16469
      word_cnt = 24;
16470
    else
16471
      word_cnt = word_cnt + 1;
16472
    // decrement bit counter
16473
    bit_cnt = bit_cnt - 1;
16474
    // wait for delta time
16475
    delta_t = !delta_t;
16476
  end // while
16477
 
16478
  // put CRC out
16479
  crc = crc_shift_reg;
16480
  #1;
16481
end
16482
endtask // serial_crc_phy_rx
16483
 
16484
// serial CRC checking for MAC
16485
task serial_crc_mac;
16486
  input  [31:0] start_addr; // start address
16487
  input  [31:0] len; // length of frame in Bytes without CRC length
16488
  input         plus_dribble_nibble; // if length is longer for one nibble
16489
  output [31:0] crc;
16490
  reg    [19:0] addr_cnt; // only 20 address lines
16491
  integer       word_cnt;
16492
  integer       bit_cnt;
16493
  reg    [31:0] load_reg;
16494
  reg    [31:0] crc_shift_reg;
16495
  reg    [31:0] crc_store_reg;
16496
  reg           delta_t;
16497
begin
16498
  #1 addr_cnt = start_addr[19:0];
16499
  // set starting point depending with which byte frame starts (e.g. if addr_cnt[1:0] == 0, then
16500
  //   MSB of the packet must be written to the LSB of Big ENDIAN Word [31:24])
16501
  if (addr_cnt[1:0] == 2'h1)
16502
    word_cnt = 16; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
16503
  else if (addr_cnt[1:0] == 2'h2)
16504
    word_cnt = 8; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
16505
  else if (addr_cnt[1:0] == 2'h3)
16506
    word_cnt = 0; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
16507
  else
16508
    word_cnt = 24; // start of the frame for Big ENDIAN Bytes (Litle ENDIAN bits)
16509
 
16510
  crc_shift_reg = 0;
16511
  delta_t = 0;
16512
  // length must include 4 bytes of ZEROs, to generate CRC
16513
  // get number of bits from Byte length (2^3 = 8)
16514
  if (plus_dribble_nibble)
16515
    bit_cnt = ((len + 4) << 3) + 3'h4; // one nibble longer
16516
  else
16517
    bit_cnt = ((len + 4) << 3);
16518
  load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
16519
 
16520
  while (bit_cnt > 0)
16521
  begin
16522
    // wait for delta time
16523
    delta_t = !delta_t;
16524
    // store previous data
16525
    crc_store_reg = crc_shift_reg;
16526
    // shift data in
16527
    if(bit_cnt <= 32) // for additional 32 bits shift ZEROs in!
16528
     crc_shift_reg[0] = 1'b0               ^ crc_store_reg[31];
16529
    else
16530
     crc_shift_reg[0] = load_reg[word_cnt] ^ crc_store_reg[31];
16531
    crc_shift_reg[1]  = crc_store_reg[0]   ^ crc_store_reg[31];
16532
    crc_shift_reg[2]  = crc_store_reg[1]   ^ crc_store_reg[31];
16533
    crc_shift_reg[3]  = crc_store_reg[2];
16534
    crc_shift_reg[4]  = crc_store_reg[3]   ^ crc_store_reg[31];
16535
    crc_shift_reg[5]  = crc_store_reg[4]   ^ crc_store_reg[31];
16536
    crc_shift_reg[6]  = crc_store_reg[5];
16537
    crc_shift_reg[7]  = crc_store_reg[6]   ^ crc_store_reg[31];
16538
    crc_shift_reg[8]  = crc_store_reg[7]   ^ crc_store_reg[31];
16539
    crc_shift_reg[9]  = crc_store_reg[8];
16540
    crc_shift_reg[10] = crc_store_reg[9]   ^ crc_store_reg[31];
16541
    crc_shift_reg[11] = crc_store_reg[10]  ^ crc_store_reg[31];
16542
    crc_shift_reg[12] = crc_store_reg[11]  ^ crc_store_reg[31];
16543
    crc_shift_reg[13] = crc_store_reg[12];
16544
    crc_shift_reg[14] = crc_store_reg[13];
16545
    crc_shift_reg[15] = crc_store_reg[14];
16546
    crc_shift_reg[16] = crc_store_reg[15]  ^ crc_store_reg[31];
16547
    crc_shift_reg[17] = crc_store_reg[16];
16548
    crc_shift_reg[18] = crc_store_reg[17];
16549
    crc_shift_reg[19] = crc_store_reg[18];
16550
    crc_shift_reg[20] = crc_store_reg[19];
16551
    crc_shift_reg[21] = crc_store_reg[20];
16552
    crc_shift_reg[22] = crc_store_reg[21]  ^ crc_store_reg[31];
16553
    crc_shift_reg[23] = crc_store_reg[22]  ^ crc_store_reg[31];
16554
    crc_shift_reg[24] = crc_store_reg[23];
16555
    crc_shift_reg[25] = crc_store_reg[24];
16556
    crc_shift_reg[26] = crc_store_reg[25]  ^ crc_store_reg[31];
16557
    crc_shift_reg[27] = crc_store_reg[26];
16558
    crc_shift_reg[28] = crc_store_reg[27];
16559
    crc_shift_reg[29] = crc_store_reg[28];
16560
    crc_shift_reg[30] = crc_store_reg[29];
16561
    crc_shift_reg[31] = crc_store_reg[30];
16562
    // wait for delta time
16563
    delta_t = !delta_t;
16564
    // increment address and load new data for Big ENDIAN Bytes (Litle ENDIAN bits)
16565
    if (word_cnt == 7)
16566
    begin
16567
      addr_cnt = addr_cnt + 4;
16568
      load_reg = wb_slave.wb_memory[{12'h0, addr_cnt}];
16569
    end
16570
    // set new load bit position for Big ENDIAN Bytes (Litle ENDIAN bits)
16571
    if(word_cnt == 31)
16572
      word_cnt = 16;
16573
    else if (word_cnt == 23)
16574
      word_cnt = 8;
16575
    else if (word_cnt == 15)
16576
      word_cnt = 0;
16577
    else if (word_cnt == 7)
16578
      word_cnt = 24;
16579
    else
16580
      word_cnt = word_cnt + 1;
16581
    // decrement bit counter
16582
    bit_cnt = bit_cnt - 1;
16583
    // wait for delta time
16584
    delta_t = !delta_t;
16585
  end // while
16586
 
16587
  // put CRC out
16588
  crc = crc_shift_reg;
16589
  #1;
16590
end
16591
endtask // serial_crc_mac
16592
 
16593
//////////////////////////////////////////////////////////////
16594
// MIIM Basic tasks
16595
//////////////////////////////////////////////////////////////
16596
 
16597
task reset_mii; //  MII module
16598
  reg [31:0] tmp;
16599
  reg [31:0] tmp_no_rst;
16600
begin
16601
  // read MII mode register first
16602
  wbm_read(`ETH_MIIMODER, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16603
  // set reset bit - write back to MII mode register with RESET bit
16604
  wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_RST | tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16605
  // clear reset bit - write back to MII mode register without RESET bit
16606
  tmp_no_rst = `ETH_MIIMODER_RST;
16607
  tmp_no_rst = ~tmp_no_rst;
16608
  wbm_write(`ETH_MIIMODER, (tmp_no_rst & tmp), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16609
end
16610
endtask // reset_mii
16611
 
16612
task mii_set_clk_div; // set clock divider for MII clock
16613
  input [7:0]  clk_div;
16614
begin
16615
  // MII mode register
16616
  wbm_write(`ETH_MIIMODER, (`ETH_MIIMODER_CLKDIV & clk_div), 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16617
end
16618
endtask // mii_set_clk_div
16619
 
16620
 
16621
task check_mii_busy; // MII - check if BUSY
16622
  reg [31:0] tmp;
16623
begin
16624
  @(posedge wb_clk);
16625
  // MII read status register
16626
  wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16627
  while(tmp[`ETH_MIISTATUS_BUSY] !== 1'b0) //`ETH_MIISTATUS_BUSY
16628
  begin
16629
    @(posedge wb_clk);
16630
    wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16631
  end
16632
end
16633
endtask // check_mii_busy
16634
 
16635
 
16636
task check_mii_scan_valid; // MII - check if SCAN data are valid
16637
  reg [31:0] tmp;
16638
begin
16639
  @(posedge wb_clk);
16640
  // MII read status register
16641
  wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16642
  while(tmp[`ETH_MIISTATUS_NVALID] !== 1'b0) //`ETH_MIISTATUS_NVALID
16643
  begin
16644
    @(posedge wb_clk);
16645
    wbm_read(`ETH_MIISTATUS, tmp, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16646
  end
16647
end
16648
endtask // check_mii_scan_valid
16649
 
16650
 
16651
task mii_write_req; // requests write to MII
16652
  input [4:0]  phy_addr;
16653
  input [4:0]  reg_addr;
16654
  input [15:0] data_in;
16655
begin
16656
  // MII address, PHY address = 1, command register address = 0
16657
  wbm_write(`ETH_MIIADDRESS, (`ETH_MIIADDRESS_FIAD & phy_addr) | (`ETH_MIIADDRESS_RGAD & (reg_addr << 8)),
16658
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16659
  // MII TX data
16660
  wbm_write(`ETH_MIITX_DATA, {16'h0000, data_in}, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16661
  // MII command
16662
  wbm_write(`ETH_MIICOMMAND, `ETH_MIICOMMAND_WCTRLDATA, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16663
  @(posedge wb_clk);
16664
end
16665
endtask // mii_write_req
16666
 
16667
 
16668
task mii_read_req; // requests read from MII
16669
  input [4:0]  phy_addr;
16670
  input [4:0]  reg_addr;
16671
begin
16672
  // MII address, PHY address = 1, command register address = 0
16673
  wbm_write(`ETH_MIIADDRESS, (`ETH_MIIADDRESS_FIAD & phy_addr) | (`ETH_MIIADDRESS_RGAD & (reg_addr << 8)),
16674
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16675
  // MII command
16676
  wbm_write(`ETH_MIICOMMAND, `ETH_MIICOMMAND_RSTAT, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16677
  @(posedge wb_clk);
16678
end
16679
endtask // mii_read_req
16680
 
16681
 
16682
task mii_scan_req; // requests scan from MII
16683
  input [4:0]  phy_addr;
16684
  input [4:0]  reg_addr;
16685
begin
16686
  // MII address, PHY address = 1, command register address = 0
16687
  wbm_write(`ETH_MIIADDRESS, (`ETH_MIIADDRESS_FIAD & phy_addr) | (`ETH_MIIADDRESS_RGAD & (reg_addr << 8)),
16688
            4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16689
  // MII command
16690
  wbm_write(`ETH_MIICOMMAND, `ETH_MIICOMMAND_SCANSTAT, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16691
  @(posedge wb_clk);
16692
end
16693
endtask // mii_scan_req
16694
 
16695
 
16696
task mii_scan_finish; // finish scan from MII
16697
begin
16698
  // MII command
16699
  wbm_write(`ETH_MIICOMMAND, 32'h0, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
16700
  @(posedge wb_clk);
16701
end
16702
endtask // mii_scan_finish
16703
 
16704
//////////////////////////////////////////////////////////////
16705
// Log files and memory tasks
16706
//////////////////////////////////////////////////////////////
16707
 
16708
task clear_memories;
16709
  reg    [22:0]  adr_i;
16710
  reg            delta_t;
16711
begin
16712
  delta_t = 0;
16713
  for (adr_i = 0; adr_i < 4194304; adr_i = adr_i + 1)
16714
  begin
16715
    eth_phy.rx_mem[adr_i[21:0]] = 0;
16716
    eth_phy.tx_mem[adr_i[21:0]] = 0;
16717
    wb_slave.wb_memory[adr_i[21:2]] = 0;
16718
    delta_t = !delta_t;
16719
  end
16720
end
16721
endtask // clear_memories
16722
 
16723 243 tadejm
task clear_buffer_descriptors;
16724
  reg    [8:0]  adr_i;
16725
  reg            delta_t;
16726
begin
16727
  delta_t = 0;
16728
  for (adr_i = 0; adr_i < 256; adr_i = adr_i + 1)
16729
  begin
16730
    wbm_write((`TX_BD_BASE + {adr_i[7:0], 2'b0}), 32'h0, 4'hF, 1, 4'h1, 4'h1);
16731
    delta_t = !delta_t;
16732
  end
16733
end
16734
endtask // clear_buffer_descriptors
16735
 
16736 169 mohor
task test_note;
16737
  input [799:0] test_note ;
16738
  reg   [799:0] display_note ;
16739
begin
16740
  display_note = test_note;
16741
  while ( display_note[799:792] == 0 )
16742
    display_note = display_note << 8 ;
16743
  $fdisplay( tb_log_file, " " ) ;
16744
  $fdisplay( tb_log_file, "NOTE: %s", display_note ) ;
16745
  $fdisplay( tb_log_file, " " ) ;
16746
end
16747
endtask // test_note
16748
 
16749
task test_heading;
16750
  input [799:0] test_heading ;
16751
  reg   [799:0] display_test ;
16752
begin
16753
  display_test = test_heading;
16754
  while ( display_test[799:792] == 0 )
16755
    display_test = display_test << 8 ;
16756
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
16757
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
16758
  $fdisplay( tb_log_file, "  Heading: %s", display_test ) ;
16759
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
16760
  $fdisplay( tb_log_file, "  ***************************************************************************************" ) ;
16761
  $fdisplay( tb_log_file, " " ) ;
16762
end
16763
endtask // test_heading
16764
 
16765
 
16766
task test_fail ;
16767
  input [7999:0] failure_reason ;
16768
//  reg   [8007:0] display_failure ;
16769
  reg   [7999:0] display_failure ;
16770
  reg   [799:0] display_test ;
16771
begin
16772
  tests_failed = tests_failed + 1 ;
16773
 
16774
  display_failure = failure_reason; // {failure_reason, "!"} ;
16775
  while ( display_failure[7999:7992] == 0 )
16776
    display_failure = display_failure << 8 ;
16777
 
16778
  display_test = test_name ;
16779
  while ( display_test[799:792] == 0 )
16780
    display_test = display_test << 8 ;
16781
 
16782
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
16783
  $fdisplay( tb_log_file, "    At time: %t ", $time ) ;
16784
  $fdisplay( tb_log_file, "    Test: %s", display_test ) ;
16785
  $fdisplay( tb_log_file, "    *FAILED* because") ;
16786
  $fdisplay( tb_log_file, "    %s", display_failure ) ;
16787
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
16788
  $fdisplay( tb_log_file, " " ) ;
16789
 
16790
 `ifdef STOP_ON_FAILURE
16791
    #20 $stop ;
16792
 `endif
16793
end
16794
endtask // test_fail
16795
 
16796
 
16797
task test_ok ;
16798
  reg [799:0] display_test ;
16799
begin
16800
  tests_successfull = tests_successfull + 1 ;
16801
 
16802
  display_test = test_name ;
16803
  while ( display_test[799:792] == 0 )
16804
    display_test = display_test << 8 ;
16805
 
16806
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
16807
  $fdisplay( tb_log_file, "    At time: %t ", $time ) ;
16808
  $fdisplay( tb_log_file, "    Test: %s", display_test ) ;
16809
  $fdisplay( tb_log_file, "    reported *SUCCESSFULL*! ") ;
16810
  $fdisplay( tb_log_file, "    *************************************************************************************" ) ;
16811
  $fdisplay( tb_log_file, " " ) ;
16812
end
16813
endtask // test_ok
16814
 
16815
 
16816
task test_summary;
16817
begin
16818
  $fdisplay(tb_log_file, "**************************** Ethernet MAC test summary **********************************") ;
16819
  $fdisplay(tb_log_file, "Tests performed:   %d", tests_successfull + tests_failed) ;
16820
  $fdisplay(tb_log_file, "Failed tests   :   %d", tests_failed) ;
16821
  $fdisplay(tb_log_file, "Successfull tests: %d", tests_successfull) ;
16822
  $fdisplay(tb_log_file, "**************************** Ethernet MAC test summary **********************************") ;
16823
  $fclose(tb_log_file) ;
16824
end
16825
endtask // test_summary
16826
 
16827
 
16828 116 mohor
endmodule

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