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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_top.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 202 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 202 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 272 tadejm
// Revision 1.44  2003/01/21 12:09:40  mohor
45
// When receiving normal data frame and RxFlow control was switched on, RXB
46
// interrupt was not set.
47
//
48 270 mohor
// Revision 1.43  2002/11/22 01:57:06  mohor
49
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
50
// synchronized.
51
//
52 261 mohor
// Revision 1.42  2002/11/21 00:09:19  mohor
53
// TPauseRq synchronized to tx_clk.
54
//
55 255 mohor
// Revision 1.41  2002/11/19 18:13:49  mohor
56
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
57
//
58 253 mohor
// Revision 1.40  2002/11/19 17:34:25  mohor
59
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
60
// that a frame was received because of the promiscous mode.
61
//
62 250 mohor
// Revision 1.39  2002/11/18 17:31:55  mohor
63
// wb_rst_i is used for MIIM reset.
64
//
65 248 mohor
// Revision 1.38  2002/11/14 18:37:20  mohor
66
// r_Rst signal does not reset any module any more and is removed from the design.
67
//
68 244 mohor
// Revision 1.37  2002/11/13 22:25:36  tadejm
69
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
70
//
71 240 tadejm
// Revision 1.36  2002/10/18 17:04:20  tadejm
72
// Changed BIST scan signals.
73
//
74 227 tadejm
// Revision 1.35  2002/10/11 13:36:58  mohor
75
// Typo error fixed. (When using Bist)
76
//
77 218 mohor
// Revision 1.34  2002/10/10 16:49:50  mohor
78
// Signals for WISHBONE B3 compliant interface added.
79
//
80 214 mohor
// Revision 1.33  2002/10/10 16:29:30  mohor
81
// BIST added.
82
//
83 210 mohor
// Revision 1.32  2002/09/20 17:12:58  mohor
84
// CsMiss added. When address between 0x800 and 0xfff is accessed within
85
// Ethernet Core, error acknowledge is generated.
86
//
87 202 mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
88
// CarrierSenseLost bug fixed when operating in full duplex mode.
89
//
90 168 mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
91
// Ethernet debug registers removed.
92
//
93 164 mohor
// Revision 1.29  2002/09/09 13:03:13  mohor
94
// Error acknowledge is generated when accessing BDs and RST bit in the
95
// MODER register (r_Rst) is set.
96
//
97 161 mohor
// Revision 1.28  2002/09/04 18:44:10  mohor
98
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
99
// connected.
100
//
101 149 mohor
// Revision 1.27  2002/07/25 18:15:37  mohor
102
// RxAbort changed. Packets received with MRxErr (from PHY) are also
103
// aborted.
104
//
105 125 mohor
// Revision 1.26  2002/07/17 18:51:50  mohor
106
// EXTERNAL_DMA removed. External DMA not supported.
107
//
108 114 mohor
// Revision 1.25  2002/05/03 10:15:50  mohor
109
// Outputs registered. Reset changed for eth_wishbone module.
110
//
111 106 mohor
// Revision 1.24  2002/04/22 14:15:42  mohor
112
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
113
// selected in eth_defines.v
114
//
115 103 mohor
// Revision 1.23  2002/03/25 13:33:53  mohor
116
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
117
// name was incorrect.
118
//
119 95 mohor
// Revision 1.22  2002/02/26 16:59:54  mohor
120
// Small fixes for external/internal DMA missmatches.
121
//
122 80 mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
123
// Interrupts changed in the top file
124
//
125 76 mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
126
// Small fixes.
127
//
128 70 mohor
// Revision 1.19  2002/02/16 14:03:44  mohor
129
// Registered trimmed. Unused registers removed.
130
//
131 68 mohor
// Revision 1.18  2002/02/16 13:06:33  mohor
132
// EXTERNAL_DMA used instead of WISHBONE_DMA.
133
//
134 67 mohor
// Revision 1.17  2002/02/16 07:15:27  mohor
135
// Testbench fixed, code simplified, unused signals removed.
136
//
137 65 mohor
// Revision 1.16  2002/02/15 13:49:39  mohor
138
// RxAbort is connected differently.
139
//
140 63 mohor
// Revision 1.15  2002/02/15 11:38:26  mohor
141
// Changes that were lost when updating from 1.11 to 1.14 fixed.
142
//
143 59 mohor
// Revision 1.14  2002/02/14 20:19:11  billditt
144
// Modified for Address Checking,
145
// addition of eth_addrcheck.v
146
//
147
// Revision 1.13  2002/02/12 17:03:03  mohor
148
// HASH0 and HASH1 registers added. Registers address width was
149
// changed to 8 bits.
150
//
151
// Revision 1.12  2002/02/11 09:18:22  mohor
152
// Tx status is written back to the BD.
153
//
154 43 mohor
// Revision 1.11  2002/02/08 16:21:54  mohor
155
// Rx status is written back to the BD.
156
//
157 42 mohor
// Revision 1.10  2002/02/06 14:10:21  mohor
158
// non-DMA host interface added. Select the right configutation in eth_defines.
159
//
160 41 mohor
// Revision 1.9  2002/01/23 10:28:16  mohor
161
// Link in the header changed.
162
//
163 37 mohor
// Revision 1.8  2001/12/05 15:00:16  mohor
164
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
165
// instead of the number of RX descriptors).
166
//
167 34 mohor
// Revision 1.7  2001/12/05 10:45:59  mohor
168
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
169
//
170 33 mohor
// Revision 1.6  2001/10/19 11:24:29  mohor
171
// Number of addresses (wb_adr_i) minimized.
172
//
173 23 mohor
// Revision 1.5  2001/10/19 08:43:51  mohor
174
// eth_timescale.v changed to timescale.v This is done because of the
175
// simulation of the few cores in a one joined project.
176
//
177 22 mohor
// Revision 1.4  2001/10/18 12:07:11  mohor
178
// Status signals changed, Adress decoding changed, interrupt controller
179
// added.
180
//
181 21 mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
182
// Defines changed (All precede with ETH_). Small changes because some
183
// tools generate warnings when two operands are together. Synchronization
184
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
185
// demands).
186
//
187 20 mohor
// Revision 1.2  2001/08/15 14:03:59  mohor
188
// Signal names changed on the top level for easier pad insertion (ASIC).
189
//
190 17 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
191
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
192
// Include files fixed to contain no path.
193
// File names and module names changed ta have a eth_ prologue in the name.
194
// File eth_timescale.v is used to define timescale
195
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
196
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
197
// and Mdo_OE. The bidirectional signal must be created on the top level. This
198
// is done due to the ASIC tools.
199
//
200 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
201
// Unconnected signals are now connected.
202
//
203
// Revision 1.1  2001/07/30 21:23:42  mohor
204
// Directory structure changed. Files checked and joind together.
205
//
206
//
207
//
208 20 mohor
// 
209 15 mohor
 
210
 
211
`include "eth_defines.v"
212 22 mohor
`include "timescale.v"
213 15 mohor
 
214
 
215
module eth_top
216
(
217
  // WISHBONE common
218 17 mohor
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
219 15 mohor
 
220
  // WISHBONE slave
221 17 mohor
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
222 15 mohor
 
223 41 mohor
  // WISHBONE master
224
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
225
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
226
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
227
 
228 214 mohor
`ifdef ETH_WISHBONE_B3
229
  m_wb_cti_o, m_wb_bte_o,
230
`endif
231
 
232 15 mohor
  //TX
233 20 mohor
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
234 15 mohor
 
235
  //RX
236 20 mohor
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
237 15 mohor
 
238
  // MIIM
239 95 mohor
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
240 17 mohor
 
241 21 mohor
  int_o
242 17 mohor
 
243 210 mohor
  // Bist
244
`ifdef ETH_BIST
245 227 tadejm
  ,
246
  // debug chain signals
247
  scanb_rst,      // bist scan reset
248
  scanb_clk,      // bist scan clock
249
  scanb_si,       // bist scan serial in
250
  scanb_so,       // bist scan serial out
251
  scanb_en        // bist scan shift enable
252 210 mohor
`endif
253 21 mohor
 
254 15 mohor
);
255
 
256
 
257
parameter Tp = 1;
258
 
259
 
260
// WISHBONE common
261 17 mohor
input           wb_clk_i;     // WISHBONE clock
262
input           wb_rst_i;     // WISHBONE reset
263
input   [31:0]  wb_dat_i;     // WISHBONE data input
264
output  [31:0]  wb_dat_o;     // WISHBONE data output
265
output          wb_err_o;     // WISHBONE error output
266 15 mohor
 
267
// WISHBONE slave
268 23 mohor
input   [11:2]  wb_adr_i;     // WISHBONE address input
269 17 mohor
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
270
input           wb_we_i;      // WISHBONE write enable input
271
input           wb_cyc_i;     // WISHBONE cycle input
272
input           wb_stb_i;     // WISHBONE strobe input
273
output          wb_ack_o;     // WISHBONE acknowledge output
274 15 mohor
 
275 41 mohor
// WISHBONE master
276
output  [31:0]  m_wb_adr_o;
277
output   [3:0]  m_wb_sel_o;
278
output          m_wb_we_o;
279
input   [31:0]  m_wb_dat_i;
280
output  [31:0]  m_wb_dat_o;
281
output          m_wb_cyc_o;
282
output          m_wb_stb_o;
283
input           m_wb_ack_i;
284
input           m_wb_err_i;
285 15 mohor
 
286 214 mohor
`ifdef ETH_WISHBONE_B3
287
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
288
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
289
`endif
290 41 mohor
 
291 15 mohor
// Tx
292 20 mohor
input           mtx_clk_pad_i; // Transmit clock (from PHY)
293 21 mohor
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
294
output          mtxen_pad_o;   // Transmit enable (to PHY)
295
output          mtxerr_pad_o;  // Transmit error (to PHY)
296 15 mohor
 
297
// Rx
298 20 mohor
input           mrx_clk_pad_i; // Receive clock (from PHY)
299 21 mohor
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
300
input           mrxdv_pad_i;   // Receive data valid (from PHY)
301
input           mrxerr_pad_i;  // Receive data error (from PHY)
302 15 mohor
 
303
// Common Tx and Rx
304 21 mohor
input           mcoll_pad_i;   // Collision (from PHY)
305
input           mcrs_pad_i;    // Carrier sense (from PHY)
306 15 mohor
 
307
// MII Management interface
308 21 mohor
input           md_pad_i;      // MII data input (from I/O cell)
309
output          mdc_pad_o;     // MII Management data clock (to PHY)
310
output          md_pad_o;      // MII data output (to I/O cell)
311 95 mohor
output          md_padoe_o;    // MII data output enable (to I/O cell)
312 15 mohor
 
313 21 mohor
output          int_o;         // Interrupt output
314 15 mohor
 
315 210 mohor
// Bist
316
`ifdef ETH_BIST
317 227 tadejm
input   scanb_rst;      // bist scan reset
318
input   scanb_clk;      // bist scan clock
319
input   scanb_si;       // bist scan serial in
320
output  scanb_so;       // bist scan serial out
321
input   scanb_en;       // bist scan shift enable
322 210 mohor
`endif
323
 
324 15 mohor
wire     [7:0]  r_ClkDiv;
325
wire            r_MiiNoPre;
326
wire    [15:0]  r_CtrlData;
327
wire     [4:0]  r_FIAD;
328
wire     [4:0]  r_RGAD;
329
wire            r_WCtrlData;
330
wire            r_RStat;
331
wire            r_ScanStat;
332
wire            NValid_stat;
333
wire            Busy_stat;
334
wire            LinkFail;
335
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
336
wire            WCtrlDataStart;
337
wire            RStatStart;
338
wire            UpdateMIIRX_DATAReg;
339
 
340
wire            TxStartFrm;
341
wire            TxEndFrm;
342
wire            TxUsedData;
343
wire     [7:0]  TxData;
344
wire            TxRetry;
345
wire            TxAbort;
346
wire            TxUnderRun;
347
wire            TxDone;
348 42 mohor
wire     [5:0]  CollValid;
349 15 mohor
 
350
 
351 149 mohor
reg             WillSendControlFrame_sync1;
352
reg             WillSendControlFrame_sync2;
353
reg             WillSendControlFrame_sync3;
354
reg             RstTxPauseRq;
355 15 mohor
 
356 255 mohor
reg             TxPauseRq_sync1;
357
reg             TxPauseRq_sync2;
358
reg             TxPauseRq_sync3;
359
reg             TPauseRq;
360 15 mohor
 
361 255 mohor
 
362 15 mohor
// Connecting Miim module
363
eth_miim miim1
364
(
365 248 mohor
  .Clk(wb_clk_i),                         .Reset(wb_rst_i),                   .Divider(r_ClkDiv),
366 15 mohor
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
367
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
368 17 mohor
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
369 95 mohor
  .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
370 15 mohor
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
371
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
372
);
373
 
374
 
375
 
376
 
377
wire        RegCs;          // Connected to registers
378 17 mohor
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
379 42 mohor
wire        r_RecSmall;     // Receive small frames
380 15 mohor
wire        r_LoopBck;      // Loopback
381
wire        r_TxEn;         // Tx Enable
382
wire        r_RxEn;         // Rx Enable
383
 
384
wire        MRxDV_Lb;       // Muxed MII receive data valid
385
wire        MRxErr_Lb;      // Muxed MII Receive Error
386
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
387
wire        Transmitting;   // Indication that TxEthMAC is transmitting
388
wire        r_HugEn;        // Huge packet enable
389
wire        r_DlyCrcEn;     // Delayed CRC enabled
390
wire [15:0] r_MaxFL;        // Maximum frame length
391
 
392
wire [15:0] r_MinFL;        // Minimum frame length
393 42 mohor
wire        ShortFrame;
394
wire        DribbleNibble;  // Extra nibble received
395
wire        ReceivedPacketTooBig; // Received packet is too big
396 15 mohor
wire [47:0] r_MAC;          // MAC address
397 42 mohor
wire        LoadRxStatus;   // Rx status was loaded
398 52 billditt
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
399
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
400 34 mohor
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
401 15 mohor
wire  [6:0] r_IPGT;         // 
402
wire  [6:0] r_IPGR1;        // 
403
wire  [6:0] r_IPGR2;        // 
404
wire  [5:0] r_CollValid;    // 
405 149 mohor
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
406
wire        r_TxPauseRq;    // Transmit PAUSE request
407 15 mohor
 
408
wire  [3:0] r_MaxRet;       //
409
wire        r_NoBckof;      // 
410
wire        r_ExDfrEn;      // 
411 34 mohor
wire        TX_BD_NUM_Wr;   // Write enable that writes RX_BD_NUM to the registers.
412 15 mohor
wire        r_TxFlow;       // Tx flow control enable
413
wire        r_IFG;          // Minimum interframe gap for incoming packets
414
 
415 21 mohor
wire        TxB_IRQ;        // Interrupt Tx Buffer
416
wire        TxE_IRQ;        // Interrupt Tx Error
417
wire        RxB_IRQ;        // Interrupt Rx Buffer
418 76 mohor
wire        RxE_IRQ;        // Interrupt Rx Error
419 21 mohor
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
420 15 mohor
 
421
wire        DWord;
422
wire        BDAck;
423 103 mohor
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
424 21 mohor
wire        BDCs;           // Buffer descriptor CS
425 202 mohor
wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
426
                            // but data is not valid.
427 15 mohor
 
428 103 mohor
wire        temp_wb_ack_o;
429
wire [31:0] temp_wb_dat_o;
430
wire        temp_wb_err_o;
431 15 mohor
 
432 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
433
  reg         temp_wb_ack_o_reg;
434
  reg [31:0]  temp_wb_dat_o_reg;
435
  reg         temp_wb_err_o_reg;
436
`endif
437
 
438 17 mohor
assign DWord = &wb_sel_i;
439 103 mohor
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];   // 0x0   - 0x3FF
440 114 mohor
assign BDCs  = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] &  wb_adr_i[10];   // 0x400 - 0x7FF
441 202 mohor
assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11];                   // 0x800 - 0xfFF
442 103 mohor
assign temp_wb_ack_o = RegCs | BDAck;
443
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
444 240 tadejm
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
445 15 mohor
 
446 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
447
  assign wb_ack_o = temp_wb_ack_o_reg;
448
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
449
  assign wb_err_o = temp_wb_err_o_reg;
450
`else
451
  assign wb_ack_o = temp_wb_ack_o;
452
  assign wb_dat_o[31:0] = temp_wb_dat_o;
453
  assign wb_err_o = temp_wb_err_o;
454
`endif
455 15 mohor
 
456
 
457
 
458 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
459
  always @ (posedge wb_clk_i or posedge wb_rst_i)
460
  begin
461
    if(wb_rst_i)
462
      begin
463
        temp_wb_ack_o_reg <=#Tp 1'b0;
464
        temp_wb_dat_o_reg <=#Tp 32'h0;
465
        temp_wb_err_o_reg <=#Tp 1'b0;
466
      end
467
    else
468
      begin
469 106 mohor
        temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
470 103 mohor
        temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
471 106 mohor
        temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
472 103 mohor
      end
473
  end
474
`endif
475
 
476
 
477 15 mohor
// Connecting Ethernet registers
478
eth_registers ethreg1
479
(
480 47 mohor
  .DataIn(wb_dat_i),                      .Address(wb_adr_i[9:2]),                    .Rw(wb_we_i),
481 17 mohor
  .Cs(RegCs),                             .Clk(wb_clk_i),                             .Reset(wb_rst_i),
482 68 mohor
  .DataOut(RegDataOut),                   .r_RecSmall(r_RecSmall),
483 15 mohor
  .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),
484 244 mohor
  .r_DlyCrcEn(r_DlyCrcEn),                .r_FullD(r_FullD),
485 15 mohor
  .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),
486 52 billditt
  .r_IFG(r_IFG),                          .r_Pro(r_Pro),                              .r_Iam(),
487
  .r_Bro(r_Bro),                          .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),
488 76 mohor
  .r_RxEn(r_RxEn),                        .Busy_IRQ(Busy_IRQ),                        .RxE_IRQ(RxE_IRQ),
489 21 mohor
  .RxB_IRQ(RxB_IRQ),                      .TxE_IRQ(TxE_IRQ),                          .TxB_IRQ(TxB_IRQ),
490 149 mohor
  .r_IPGT(r_IPGT),
491 15 mohor
  .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),
492
  .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),
493
  .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),
494 253 mohor
  .r_MiiNoPre(r_MiiNoPre),                .r_ClkDiv(r_ClkDiv),
495 15 mohor
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
496
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
497
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
498
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
499
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
500 47 mohor
  .r_TxBDNum(r_TxBDNum),                  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),                .int_o(int_o),
501 149 mohor
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
502
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
503
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
504 261 mohor
  .SetPauseTimer(SetPauseTimer)
505 149 mohor
 
506 15 mohor
);
507
 
508
 
509
 
510
wire  [7:0] RxData;
511
wire        RxValid;
512
wire        RxStartFrm;
513
wire        RxEndFrm;
514 41 mohor
wire        RxAbort;
515 15 mohor
 
516
wire        WillTransmit;            // Will transmit (to RxEthMAC)
517
wire        ResetCollision;          // Reset Collision (for synchronizing collision)
518
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
519
wire        WillSendControlFrame;
520
wire        ReceiveEnd;
521
wire        ReceivedPacketGood;
522
wire        ReceivedLengthOK;
523 42 mohor
wire        InvalidSymbol;
524
wire        LatchedCrcError;
525
wire        RxLateCollision;
526 59 mohor
wire  [3:0] RetryCntLatched;
527
wire  [3:0] RetryCnt;
528
wire        StartTxAbort;
529
wire        MaxCollisionOccured;
530
wire        RetryLimit;
531
wire        StatePreamble;
532
wire  [1:0] StateData;
533 15 mohor
 
534
// Connecting MACControl
535
eth_maccontrol maccontrol1
536
(
537 255 mohor
  .MTxClk(mtx_clk_pad_i),                       .TPauseRq(TPauseRq),
538 149 mohor
  .TxPauseTV(r_TxPauseTV),                      .TxDataIn(TxData),
539 15 mohor
  .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),
540
  .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),
541 20 mohor
  .TxAbortIn(TxAbortIn),                        .MRxClk(mrx_clk_pad_i),
542 15 mohor
  .RxData(RxData),                              .RxValid(RxValid),
543
  .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),
544
  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),
545 261 mohor
  .TxFlow(r_TxFlow),
546 15 mohor
  .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),
547
  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),
548
  .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),
549 240 tadejm
  .CrcEnOut(CrcEnOut),                          .TxReset(wb_rst_i),
550
  .RxReset(wb_rst_i),                           .ReceivedLengthOK(ReceivedLengthOK),
551 15 mohor
  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),
552
  .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),
553
  .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),
554
  .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),
555 261 mohor
  .ReceivedPauseFrm(ReceivedPauseFrm),          .ControlFrmAddressOK(ControlFrmAddressOK),
556 272 tadejm
  .SetPauseTimer(SetPauseTimer),
557
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),                .r_PassAll(r_PassAll)
558 15 mohor
);
559
 
560
 
561
 
562
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
563
wire Collision;               // Synchronized Collision
564
 
565
reg CarrierSense_Tx1;
566
reg CarrierSense_Tx2;
567
reg Collision_Tx1;
568
reg Collision_Tx2;
569
 
570
reg RxEnSync;                 // Synchronized Receive Enable
571
reg CarrierSense_Rx1;
572
reg RxCarrierSense;           // Synchronized CarrierSense (to Rx clock)
573
reg WillTransmit_q;
574
reg WillTransmit_q2;
575
 
576
 
577
 
578
// Muxed MII receive data valid
579 17 mohor
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
580 15 mohor
 
581
// Muxed MII Receive Error
582 17 mohor
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
583 15 mohor
 
584
// Muxed MII Receive Data
585 17 mohor
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
586 15 mohor
 
587
 
588
 
589
// Connecting TxEthMAC
590
eth_txethmac txethmac1
591
(
592 240 tadejm
  .MTxClk(mtx_clk_pad_i),             .Reset(wb_rst_i),                   .CarrierSense(TxCarrierSense),
593 15 mohor
  .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),
594
  .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),
595
  .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),
596
  .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),
597
  .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),
598
  .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),
599 17 mohor
  .MaxFL(r_MaxFL),                    .MTxEn(mtxen_pad_o),                .MTxD(mtxd_pad_o),
600
  .MTxErr(mtxerr_pad_o),              .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),
601 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),
602 59 mohor
  .ResetCollision(ResetCollision),    .RetryCnt(RetryCnt),                .StartTxDone(StartTxDone),
603
  .StartTxAbort(StartTxAbort),        .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
604
  .StartDefer(StartDefer),            .StatePreamble(StatePreamble),      .StateData(StateData)
605 15 mohor
);
606
 
607
 
608
 
609
 
610
wire  [15:0]  RxByteCnt;
611
wire          RxByteCntEq0;
612
wire          RxByteCntGreat2;
613
wire          RxByteCntMaxFrame;
614
wire          RxCrcError;
615
wire          RxStateIdle;
616
wire          RxStatePreamble;
617
wire          RxStateSFD;
618
wire   [1:0]  RxStateData;
619 250 mohor
wire          AddressMiss;
620 15 mohor
 
621
 
622
 
623
// Connecting RxEthMAC
624
eth_rxethmac rxethmac1
625
(
626 21 mohor
  .MRxClk(mrx_clk_pad_i),               .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),
627 15 mohor
  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),
628 240 tadejm
  .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(wb_rst_i),
629 15 mohor
  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm),
630 65 mohor
  .RxEndFrm(RxEndFrm),                  .ByteCnt(RxByteCnt),
631 15 mohor
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame),
632
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble),
633 52 billditt
  .StateSFD(RxStateSFD),                .StateData(RxStateData),
634 63 mohor
  .MAC(r_MAC),                          .r_Pro(r_Pro),                        .r_Bro(r_Bro),
635 250 mohor
  .r_HASH0(r_HASH0),                    .r_HASH1(r_HASH1),                    .RxAbort(RxAbort),
636 261 mohor
  .AddressMiss(AddressMiss),            .PassAll(r_PassAll),                  .ControlFrmAddressOK(ControlFrmAddressOK)
637 15 mohor
);
638
 
639
 
640
// MII Carrier Sense Synchronization
641 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
642 15 mohor
begin
643 240 tadejm
  if(wb_rst_i)
644 15 mohor
    begin
645
      CarrierSense_Tx1 <= #Tp 1'b0;
646
      CarrierSense_Tx2 <= #Tp 1'b0;
647
    end
648
  else
649
    begin
650 17 mohor
      CarrierSense_Tx1 <= #Tp mcrs_pad_i;
651 15 mohor
      CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
652
    end
653
end
654
 
655
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
656
 
657
 
658
// MII Collision Synchronization
659 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
660 15 mohor
begin
661 240 tadejm
  if(wb_rst_i)
662 15 mohor
    begin
663
      Collision_Tx1 <= #Tp 1'b0;
664
      Collision_Tx2 <= #Tp 1'b0;
665
    end
666
  else
667
    begin
668 17 mohor
      Collision_Tx1 <= #Tp mcoll_pad_i;
669 15 mohor
      if(ResetCollision)
670
        Collision_Tx2 <= #Tp 1'b0;
671
      else
672
      if(Collision_Tx1)
673
        Collision_Tx2 <= #Tp 1'b1;
674
    end
675
end
676
 
677
 
678
// Synchronized Collision
679
assign Collision = ~r_FullD & Collision_Tx2;
680
 
681
 
682
 
683
// Carrier sense is synchronized to receive clock.
684 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
685 15 mohor
begin
686 240 tadejm
  if(wb_rst_i)
687 15 mohor
    begin
688
      CarrierSense_Rx1 <= #Tp 1'h0;
689
      RxCarrierSense <= #Tp 1'h0;
690
    end
691
  else
692
    begin
693 17 mohor
      CarrierSense_Rx1 <= #Tp mcrs_pad_i;
694 15 mohor
      RxCarrierSense <= #Tp CarrierSense_Rx1;
695
    end
696
end
697
 
698
 
699
// Delayed WillTransmit
700 20 mohor
always @ (posedge mrx_clk_pad_i)
701 15 mohor
begin
702
  WillTransmit_q <= #Tp WillTransmit;
703
  WillTransmit_q2 <= #Tp WillTransmit_q;
704
end
705
 
706
 
707
assign Transmitting = ~r_FullD & WillTransmit_q2;
708
 
709
 
710
 
711
// Synchronized Receive Enable
712 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
713 15 mohor
begin
714 240 tadejm
  if(wb_rst_i)
715 15 mohor
    RxEnSync <= #Tp 1'b0;
716
  else
717
  if(~RxCarrierSense | RxCarrierSense & Transmitting)
718
    RxEnSync <= #Tp r_RxEn;
719
end
720
 
721
 
722
 
723 149 mohor
// Synchronizing WillSendControlFrame to WB_CLK;
724
always @ (posedge wb_clk_i or posedge wb_rst_i)
725
begin
726
  if(wb_rst_i)
727
    WillSendControlFrame_sync1 <= 1'b0;
728
  else
729
    WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
730
end
731 15 mohor
 
732 149 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
733
begin
734
  if(wb_rst_i)
735
    WillSendControlFrame_sync2 <= 1'b0;
736
  else
737
    WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
738
end
739
 
740
always @ (posedge wb_clk_i or posedge wb_rst_i)
741
begin
742
  if(wb_rst_i)
743
    WillSendControlFrame_sync3 <= 1'b0;
744
  else
745
    WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
746
end
747
 
748
always @ (posedge wb_clk_i or posedge wb_rst_i)
749
begin
750
  if(wb_rst_i)
751
    RstTxPauseRq <= 1'b0;
752
  else
753
    RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
754
end
755
 
756
 
757 255 mohor
 
758
 
759
// TX Pause request Synchronization
760
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
761
begin
762
  if(wb_rst_i)
763
    begin
764
      TxPauseRq_sync1 <= #Tp 1'b0;
765
      TxPauseRq_sync2 <= #Tp 1'b0;
766
      TxPauseRq_sync3 <= #Tp 1'b0;
767
    end
768
  else
769
    begin
770
      TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
771
      TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
772
      TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
773
    end
774
end
775
 
776
 
777
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
778
begin
779
  if(wb_rst_i)
780
    TPauseRq <= #Tp 1'b0;
781
  else
782
    TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
783
end
784
 
785
 
786 261 mohor
wire LatchedMRxErr;
787
reg RxAbort_latch;
788
reg RxAbort_sync1;
789
reg RxAbort_sync2;
790
reg RxAbort_wb;
791
reg RxAbortRst_sync1;
792
reg RxAbortRst;
793 255 mohor
 
794 261 mohor
// Synchronizing RxAbort to the WISHBONE clock
795
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
796
begin
797
  if(wb_rst_i)
798
    RxAbort_latch <= #Tp 1'b0;
799
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
800
    RxAbort_latch <= #Tp 1'b1;
801
  else if(RxAbortRst)
802
    RxAbort_latch <= #Tp 1'b0;
803
end
804 255 mohor
 
805 261 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
806
begin
807
  if(wb_rst_i)
808
    begin
809
      RxAbort_sync1 <= #Tp 1'b0;
810
      RxAbort_wb    <= #Tp 1'b0;
811
      RxAbort_wb    <= #Tp 1'b0;
812
    end
813
  else
814
    begin
815
      RxAbort_sync1 <= #Tp RxAbort_latch;
816
      RxAbort_wb    <= #Tp RxAbort_sync1;
817
    end
818
end
819
 
820
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
821
begin
822
  if(wb_rst_i)
823
    begin
824
      RxAbortRst_sync1 <= #Tp 1'b0;
825
      RxAbortRst       <= #Tp 1'b0;
826
    end
827
  else
828
    begin
829
      RxAbortRst_sync1 <= #Tp RxAbort_wb;
830
      RxAbortRst       <= #Tp RxAbortRst_sync1;
831
    end
832
end
833
 
834
 
835
 
836 114 mohor
// Connecting Wishbone module
837 41 mohor
eth_wishbone wishbone
838 15 mohor
(
839 41 mohor
  .WB_CLK_I(wb_clk_i),                .WB_DAT_I(wb_dat_i),
840 103 mohor
  .WB_DAT_O(BD_WB_DAT_O),
841 15 mohor
 
842
  // WISHBONE slave
843 76 mohor
  .WB_ADR_I(wb_adr_i[9:2]),           .WB_WE_I(wb_we_i),
844 21 mohor
  .BDCs(BDCs),                        .WB_ACK_O(BDAck),
845 15 mohor
 
846 240 tadejm
  .Reset(wb_rst_i),
847 41 mohor
 
848
  // WISHBONE master
849
  .m_wb_adr_o(m_wb_adr_o),            .m_wb_sel_o(m_wb_sel_o),                  .m_wb_we_o(m_wb_we_o),
850
  .m_wb_dat_i(m_wb_dat_i),            .m_wb_dat_o(m_wb_dat_o),                  .m_wb_cyc_o(m_wb_cyc_o),
851
  .m_wb_stb_o(m_wb_stb_o),            .m_wb_ack_i(m_wb_ack_i),                  .m_wb_err_i(m_wb_err_i),
852 214 mohor
 
853
`ifdef ETH_WISHBONE_B3
854
  .m_wb_cti_o(m_wb_cti_o),            .m_wb_bte_o(m_wb_bte_o),
855
`endif
856
 
857 41 mohor
 
858 15 mohor
    //TX
859 21 mohor
  .MTxClk(mtx_clk_pad_i),             .TxStartFrm(TxStartFrm),                  .TxEndFrm(TxEndFrm),
860 59 mohor
  .TxUsedData(TxUsedData),            .TxData(TxData),
861 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbort),                        .TxUnderRun(TxUnderRun),
862 149 mohor
  .TxDone(TxDone),
863
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
864 15 mohor
 
865
  // Register
866 34 mohor
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
867 270 mohor
  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),        .r_RxFlow(r_RxFlow),                      .r_PassAll(r_PassAll),
868 15 mohor
 
869
  //RX
870 21 mohor
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
871 41 mohor
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
872 76 mohor
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),
873 149 mohor
  .TxE_IRQ(TxE_IRQ),                  .TxB_IRQ(TxB_IRQ),
874 21 mohor
 
875 272 tadejm
  .RxAbort(RxAbort_wb),               .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
876 41 mohor
 
877 42 mohor
  .InvalidSymbol(InvalidSymbol),      .LatchedCrcError(LatchedCrcError),        .RxLength(RxByteCnt),
878
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
879 59 mohor
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
880
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
881 261 mohor
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),  .AddressMiss(AddressMiss),
882
  .ReceivedPauseFrm(ReceivedPauseFrm)
883 59 mohor
 
884 210 mohor
`ifdef ETH_BIST
885 218 mohor
  ,
886 227 tadejm
  .scanb_rst      (scanb_rst),
887
  .scanb_clk      (scanb_clk),
888
  .scanb_si       (scanb_si),
889
  .scanb_so       (scanb_so),
890
  .scanb_en       (scanb_en)
891 210 mohor
`endif
892 15 mohor
);
893
 
894
 
895
 
896
// Connecting MacStatus module
897
eth_macstatus macstatus1
898
(
899 240 tadejm
  .MRxClk(mrx_clk_pad_i),             .Reset(wb_rst_i),
900 42 mohor
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),     .ReceivedLengthOK(ReceivedLengthOK),
901
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                          .MRxDV(MRxDV_Lb),
902
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                   .RxStatePreamble(RxStatePreamble),
903
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),                 .RxByteCnt(RxByteCnt),
904
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),           .RxByteCntMaxFrame(RxByteCntMaxFrame),
905 261 mohor
  .InvalidSymbol(InvalidSymbol),
906 42 mohor
  .MRxD(MRxD_Lb),                     .LatchedCrcError(LatchedCrcError),           .Collision(mcoll_pad_i),
907
  .CollValid(r_CollValid),            .RxLateCollision(RxLateCollision),           .r_RecSmall(r_RecSmall),
908
  .r_MinFL(r_MinFL),                  .r_MaxFL(r_MaxFL),                           .ShortFrame(ShortFrame),
909
  .DribbleNibble(DribbleNibble),      .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
910 59 mohor
  .LoadRxStatus(LoadRxStatus),        .RetryCnt(RetryCnt),                         .StartTxDone(StartTxDone),
911
  .StartTxAbort(StartTxAbort),        .RetryCntLatched(RetryCntLatched),           .MTxClk(mtx_clk_pad_i),
912
  .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit),              .LateCollision(LateCollision),
913
  .LateCollLatched(LateCollLatched),  .StartDefer(StartDefer),                     .DeferLatched(DeferLatched),
914
  .TxStartFrm(TxStartFrmOut),         .StatePreamble(StatePreamble),               .StateData(StateData),
915 125 mohor
  .CarrierSense(CarrierSense_Tx2),    .CarrierSenseLost(CarrierSenseLost),         .TxUsedData(TxUsedDataIn),
916 168 mohor
  .LatchedMRxErr(LatchedMRxErr),      .Loopback(r_LoopBck),                        .r_FullD(r_FullD)
917 15 mohor
);
918
 
919
 
920
endmodule

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