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172 |
mohor |
// Signalscan Version 6.7p1
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define noactivityindicator
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define analog waveform lines
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define add variable default overlay off
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define waveform window analogheight 1
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define terminal automatic
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define buttons control \
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1 opensimmulationfile \
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2 executedofile \
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3 designbrowser \
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4 waveform \
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5 source \
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6 breakpoints \
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7 definesourcessearchpath \
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8 exit \
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9 createbreakpoint \
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10 creategroup \
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11 createmarker \
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12 closesimmulationfile \
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13 renamesimmulationfile \
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14 replacesimulationfiledata \
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15 listopensimmulationfiles \
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16 savedofile
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define buttons waveform \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 zoomin \
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7 zoomout \
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8 zoomoutfull \
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9 expand \
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10 createmarker \
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11 designbrowser:1 \
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12 variableradixbinary \
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13 variableradixoctal \
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14 variableradixdecimal \
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15 variableradixhexadecimal \
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16 variableradixascii
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define buttons designbrowser \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 cdupscope \
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7 getallvariables \
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8 getdeepallvariables \
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9 addvariables \
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10 addvarsandclosewindow \
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11 closewindow \
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12 scopefiltermodule \
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13 scopefiltertask \
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14 scopefilterfunction \
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15 scopefilterblock \
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16 scopefilterprimitive
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define buttons event \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 move \
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7 closewindow \
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8 duplicate \
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9 defineasrisingedge \
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10 defineasfallingedge \
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11 defineasanyedge \
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12 variableradixbinary \
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13 variableradixoctal \
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14 variableradixdecimal \
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15 variableradixhexadecimal \
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16 variableradixascii
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define buttons source \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 createbreakpoint \
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7 creategroup \
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8 createmarker \
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9 createevent \
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10 createregisterpage \
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11 closewindow \
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12 opensimmulationfile \
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13 closesimmulationfile \
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14 renamesimmulationfile \
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15 replacesimulationfiledata \
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16 listopensimmulationfiles
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define buttons register \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 createregisterpage \
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7 closewindow \
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8 continuefor \
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9 continueuntil \
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10 continueforever \
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11 stop \
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12 previous \
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13 next \
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14 variableradixbinary \
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15 variableradixhexadecimal \
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16 variableradixascii
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define show related transactions
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define exit prompt
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define event search direction forward
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define variable nofullhierarchy
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define variable nofilenames
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define variable nofullpathfilenames
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include bookmark with filenames
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include scope history without filenames
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319 |
tadejm |
define waveform window listpane 11
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define waveform window namepane 16
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172 |
mohor |
define multivalueindication
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define pattern curpos dot
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define pattern cursor1 dot
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define pattern cursor2 dot
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define pattern marker dot
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define print designer "Miha Dolenc"
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define print border
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define print color blackonwhite
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define print command "/usr/ucb/lpr -P%P"
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define print printer lp
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define print range visible
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define print variable visible
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define rise fall time low threshold percentage 10
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define rise fall time high threshold percentage 90
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define rise fall time low value 0
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define rise fall time high value 3.3
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define sendmail command "/usr/lib/sendmail"
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define sequence time width 30.00
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define snap
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define source noprompt
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define time units default
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define userdefinedbussymbol
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define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html"
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define waveform window grid off
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define waveform window waveheight 14
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define waveform window wavespace 6
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define web browser command netscape
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define zoom outfull on initial add off
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add group \
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A \
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add group \
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"WISHBONE common" \
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tb_ethernet.eth_top.wb_clk_i \
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tb_ethernet.eth_top.wb_rst_i \
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tb_ethernet.eth_top.wb_dat_i[31:0]'h \
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tb_ethernet.eth_top.wb_dat_o[31:0]'h \
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tb_ethernet.eth_top.wb_err_o \
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add group \
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"WISHBONE slave signals" \
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319 |
tadejm |
tb_ethernet.eth_sl_wb_dat_i[31:0]'h \
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tb_ethernet.eth_sl_wb_dat_o[31:0]'h \
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172 |
mohor |
tb_ethernet.eth_top.wb_adr_i[11:2]'h \
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tb_ethernet.eth_top.wb_sel_i[3:0]'h \
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tb_ethernet.eth_top.wb_we_i \
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tb_ethernet.eth_top.wb_cyc_i \
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tb_ethernet.eth_top.wb_stb_i \
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tb_ethernet.eth_top.wb_ack_o \
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add group \
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"WISHBONE master signals" \
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tb_ethernet.eth_top.m_wb_adr_o[31:0]'h \
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tb_ethernet.eth_top.m_wb_sel_o[3:0]'h \
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tb_ethernet.eth_top.m_wb_we_o \
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tb_ethernet.eth_top.m_wb_dat_i[31:0]'h \
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tb_ethernet.eth_top.m_wb_dat_o[31:0]'h \
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tb_ethernet.eth_top.m_wb_cyc_o \
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tb_ethernet.eth_top.m_wb_stb_o \
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tb_ethernet.eth_top.m_wb_ack_i \
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tb_ethernet.eth_top.m_wb_err_i \
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add group \
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319 |
tadejm |
"WISHBONE RX memory" \
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tb_ethernet.eth_top.wishbone.TxLength[15:0]'h \
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tb_ethernet.eth_top.wishbone.TxLengthEq0 \
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| 188 |
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tb_ethernet.eth_top.wishbone.TxLengthLt4 \
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| 189 |
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tb_ethernet.eth_top.wishbone.TxPointerLSB[1:0]'h \
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tb_ethernet.eth_top.wishbone.TxPointerLSB_rst[1:0]'h \
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| 191 |
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tb_ethernet.eth_top.wishbone.TxPointerMSB[31:2]'h \
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| 192 |
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tb_ethernet.eth_top.wishbone.TxPointerRead \
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| 193 |
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tb_ethernet.eth_top.wishbone.TxBDReady \
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| 194 |
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tb_ethernet.eth_top.wishbone.TxBufferAlmostEmpty \
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tb_ethernet.eth_top.wishbone.TxBufferAlmostFull \
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| 196 |
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tb_ethernet.eth_top.wishbone.TxBufferEmpty \
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| 197 |
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tb_ethernet.eth_top.wishbone.TxBufferFull \
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| 198 |
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tb_ethernet.eth_top.wishbone.TxData_wb[31:0]'h \
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| 199 |
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tb_ethernet.eth_top.wishbone.TxData[7:0]'h \
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| 200 |
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tb_ethernet.eth_top.wishbone.TxDataLatched[31:0]'h \
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| 201 |
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tb_ethernet.eth_top.wishbone.TxByteCnt[1:0]'h \
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| 202 |
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tb_ethernet.eth_top.wishbone.TxStatus[14:11]'h \
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| 203 |
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tb_ethernet.eth_top.wishbone.TxStatusInLatched[8:0]'h \
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| 204 |
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tb_ethernet.test_mac_full_duplex_transmit.max_tmp[15:0]'h \
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| 205 |
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tb_ethernet.test_mac_full_duplex_transmit.min_tmp[15:0]'h \
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| 206 |
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tb_ethernet.test_mac_full_duplex_transmit.i_length'h \
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| 207 |
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tb_ethernet.eth_phy.tx_len[31:0]'h \
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| 208 |
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tb_ethernet.eth_phy.tx_len_err[31:0]'h \
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| 209 |
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tb_ethernet.eth_phy.tx_cnt[31:0]'h \
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| 210 |
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tb_ethernet.eth_phy.tx_byte_aligned_ok \
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| 211 |
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tb_ethernet.wb_slave.CYC_I \
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| 212 |
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tb_ethernet.wb_slave.STB_I \
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| 213 |
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tb_ethernet.wb_slave.WE_I \
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| 214 |
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tb_ethernet.wb_slave.ADR_I[31:0]'h \
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| 215 |
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tb_ethernet.wb_slave.DAT_I[31:0]'h \
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| 216 |
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tb_ethernet.wb_slave.SEL_I[3:0]'h \
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| 217 |
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tb_ethernet.wb_slave.ACK_O \
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| 218 |
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tb_ethernet.wb_slave.ERR_O \
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| 219 |
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tb_ethernet.wb_slave.RTY_O \
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| 220 |
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tb_ethernet.wb_slave.mem_wr_data_out[31:0]'h \
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| 221 |
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tb_ethernet.test_mac_full_duplex_receive.num_of_frames's \
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| 222 |
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tb_ethernet.test_mac_full_duplex_receive.first_fr_received \
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| 223 |
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tb_ethernet.test_mac_full_duplex_receive.bit_end_1's \
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| 224 |
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tb_ethernet.test_mac_full_duplex_receive.bit_end_2's \
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| 225 |
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tb_ethernet.test_mac_full_duplex_receive.bit_start_1's \
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| 226 |
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tb_ethernet.test_mac_full_duplex_receive.bit_start_2's \
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| 227 |
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tb_ethernet.test_mac_full_duplex_receive.burst_data[32767:0]'h \
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| 228 |
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tb_ethernet.test_mac_full_duplex_receive.burst_tmp_data[32767:0]'h \
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| 229 |
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tb_ethernet.test_mac_full_duplex_receive.check_frame \
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| 230 |
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tb_ethernet.test_mac_full_duplex_receive.data[31:0]'h \
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| 231 |
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tb_ethernet.test_mac_full_duplex_receive.end_task[31:0]'h \
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| 232 |
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tb_ethernet.test_mac_full_duplex_receive.fail's \
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| 233 |
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tb_ethernet.test_mac_full_duplex_receive.first_fr_received \
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| 234 |
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tb_ethernet.test_mac_full_duplex_receive.frame_ended \
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| 235 |
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tb_ethernet.test_mac_full_duplex_receive.frame_started \
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| 236 |
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tb_ethernet.test_mac_full_duplex_receive.i's \
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| 237 |
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tb_ethernet.test_mac_full_duplex_receive.i1's \
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| 238 |
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tb_ethernet.test_mac_full_duplex_receive.i2's \
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| 239 |
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tb_ethernet.test_mac_full_duplex_receive.i3's \
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| 240 |
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tb_ethernet.test_mac_full_duplex_receive.i_addr's \
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| 241 |
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tb_ethernet.test_mac_full_duplex_receive.i_data's \
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| 242 |
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tb_ethernet.test_mac_full_duplex_receive.i_length's \
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| 243 |
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tb_ethernet.test_mac_full_duplex_receive.max_tmp[15:0]'h \
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| 244 |
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tb_ethernet.test_mac_full_duplex_receive.min_tmp[15:0]'h \
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| 245 |
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tb_ethernet.test_mac_full_duplex_receive.num_of_bd's \
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| 246 |
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tb_ethernet.test_mac_full_duplex_receive.num_of_frames's \
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| 247 |
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tb_ethernet.test_mac_full_duplex_receive.num_of_reg's \
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| 248 |
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tb_ethernet.test_mac_full_duplex_receive.speed's \
|
| 249 |
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tb_ethernet.test_mac_full_duplex_receive.st_data[7:0]'h \
|
| 250 |
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tb_ethernet.test_mac_full_duplex_receive.start_task[31:0]'h \
|
| 251 |
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tb_ethernet.test_mac_full_duplex_receive.stop_checking_frame \
|
| 252 |
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tb_ethernet.test_mac_full_duplex_receive.test_num's \
|
| 253 |
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tb_ethernet.test_mac_full_duplex_receive.tmp[31:0]'h \
|
| 254 |
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tb_ethernet.test_mac_full_duplex_receive.tmp_bd'h \
|
| 255 |
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tb_ethernet.test_mac_full_duplex_receive.tmp_bd_num's \
|
| 256 |
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tb_ethernet.test_mac_full_duplex_receive.tmp_data's \
|
| 257 |
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tb_ethernet.test_mac_full_duplex_receive.tmp_ipgt's \
|
| 258 |
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tb_ethernet.test_mac_full_duplex_receive.tmp_len's \
|
| 259 |
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tb_ethernet.test_mac_full_duplex_receive.tx_bd_num[31:0]'h \
|
| 260 |
|
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tb_ethernet.test_mac_full_duplex_receive.wait_for_frame \
|
| 261 |
|
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tb_ethernet.wbm_working \
|
| 262 |
|
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tb_ethernet.check_rx_packet.addr_phy[31:0]'h \
|
| 263 |
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tb_ethernet.check_rx_packet.addr_wb[31:0]'h \
|
| 264 |
|
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tb_ethernet.check_rx_packet.buffer[21:0]'h \
|
| 265 |
|
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tb_ethernet.check_rx_packet.data_phy'h \
|
| 266 |
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tb_ethernet.check_rx_packet.data_wb'h \
|
| 267 |
|
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tb_ethernet.check_rx_packet.delta_t \
|
| 268 |
|
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tb_ethernet.check_rx_packet.failure[31:0]'h \
|
| 269 |
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tb_ethernet.check_rx_packet.i's \
|
| 270 |
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tb_ethernet.check_rx_packet.len[15:0]'h \
|
| 271 |
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tb_ethernet.check_rx_packet.plus_dribble_nibble \
|
| 272 |
|
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tb_ethernet.check_rx_packet.rxpnt_phy[31:0]'h \
|
| 273 |
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tb_ethernet.check_rx_packet.rxpnt_wb[31:0]'h \
|
| 274 |
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tb_ethernet.check_rx_packet.successful_dribble_nibble \
|
| 275 |
|
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tb_ethernet.wb_slave.rd_mem.adr_i[31:0]'h \
|
| 276 |
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tb_ethernet.wb_slave.rd_mem.dat_o[31:0]'h \
|
| 277 |
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tb_ethernet.wb_slave.rd_mem.sel_i[3:0]'h \
|
| 278 |
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tb_ethernet.wb_slave.ADR_I[31:0]'h \
|
| 279 |
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tb_ethernet.wb_slave.mem_wr_data_out[31:0]'h \
|
| 280 |
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tb_ethernet.wb_slave.SEL_I[3:0]'h \
|
| 281 |
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|
| 282 |
|
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add group \
|
| 283 |
310 |
tadejm |
"MAC FIFO" \
|
| 284 |
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tb_ethernet.eth_top.wishbone.rx_fifo.write \
|
| 285 |
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tb_ethernet.eth_top.wishbone.rx_fifo.data_in[31:0]'h \
|
| 286 |
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tb_ethernet.eth_top.wishbone.rx_fifo.write_pointer[3:0]'h \
|
| 287 |
|
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tb_ethernet.eth_top.wishbone.rx_fifo.almost_full \
|
| 288 |
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tb_ethernet.eth_top.wishbone.rx_fifo.full \
|
| 289 |
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tb_ethernet.eth_top.wishbone.rx_fifo.read \
|
| 290 |
|
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tb_ethernet.eth_top.wishbone.rx_fifo.data_out[31:0]'h \
|
| 291 |
|
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tb_ethernet.eth_top.wishbone.rx_fifo.read_pointer[3:0]'h \
|
| 292 |
|
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tb_ethernet.eth_top.wishbone.rx_fifo.almost_empty \
|
| 293 |
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tb_ethernet.eth_top.wishbone.rx_fifo.empty \
|
| 294 |
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|
|
| 295 |
|
|
add group \
|
| 296 |
|
|
"MAC registers" \
|
| 297 |
|
|
tb_ethernet.eth_top.ethreg1.MODEROut[31:0]'h \
|
| 298 |
|
|
tb_ethernet.eth_top.ethreg1.INT_SOURCEOut[31:0]'h \
|
| 299 |
|
|
tb_ethernet.eth_top.ethreg1.INT_MASKOut[31:0]'h \
|
| 300 |
|
|
tb_ethernet.eth_top.ethreg1.IPGTOut[31:0]'h \
|
| 301 |
|
|
tb_ethernet.eth_top.ethreg1.IPGR1Out[31:0]'h \
|
| 302 |
|
|
tb_ethernet.eth_top.ethreg1.IPGR2Out[31:0]'h \
|
| 303 |
|
|
tb_ethernet.eth_top.ethreg1.PACKETLENOut[31:0]'h \
|
| 304 |
|
|
tb_ethernet.eth_top.ethreg1.COLLCONFOut[31:0]'h \
|
| 305 |
|
|
tb_ethernet.eth_top.ethreg1.TX_BD_NUMOut[31:0]'h \
|
| 306 |
|
|
tb_ethernet.eth_top.ethreg1.CTRLMODEROut[31:0]'h \
|
| 307 |
|
|
tb_ethernet.eth_top.ethreg1.MIIMODEROut[31:0]'h \
|
| 308 |
|
|
tb_ethernet.eth_top.ethreg1.MIICOMMANDOut[31:0]'h \
|
| 309 |
|
|
tb_ethernet.eth_top.ethreg1.MIIADDRESSOut[31:0]'h \
|
| 310 |
|
|
tb_ethernet.eth_top.ethreg1.MIITX_DATAOut[31:0]'h \
|
| 311 |
|
|
tb_ethernet.eth_top.ethreg1.MIIRX_DATAOut[31:0]'h \
|
| 312 |
|
|
tb_ethernet.eth_top.ethreg1.MIISTATUSOut[31:0]'h \
|
| 313 |
|
|
tb_ethernet.eth_top.ethreg1.MAC_ADDR0Out[31:0]'h \
|
| 314 |
|
|
tb_ethernet.eth_top.ethreg1.MAC_ADDR1Out[31:0]'h \
|
| 315 |
|
|
tb_ethernet.eth_top.ethreg1.HASH0Out[31:0]'h \
|
| 316 |
|
|
tb_ethernet.eth_top.ethreg1.HASH1Out[31:0]'h \
|
| 317 |
|
|
tb_ethernet.eth_top.ethreg1.TXCTRLOut[31:0]'h \
|
| 318 |
|
|
|
| 319 |
|
|
add group \
|
| 320 |
|
|
testbench_test_signals \
|
| 321 |
|
|
tb_ethernet.test_mac_full_duplex_transmit.i_length's \
|
| 322 |
|
|
tb_ethernet.test_mac_full_duplex_transmit.tmp_len's \
|
| 323 |
|
|
|
| 324 |
|
|
add group \
|
| 325 |
172 |
mohor |
"MAC common" \
|
| 326 |
|
|
tb_ethernet.eth_top.mcoll_pad_i \
|
| 327 |
|
|
tb_ethernet.eth_top.mcrs_pad_i \
|
| 328 |
|
|
|
| 329 |
|
|
add group \
|
| 330 |
|
|
"MAC TX" \
|
| 331 |
|
|
tb_ethernet.eth_top.mtx_clk_pad_i \
|
| 332 |
|
|
tb_ethernet.eth_top.mtxd_pad_o[3:0]'h \
|
| 333 |
|
|
tb_ethernet.eth_top.mtxen_pad_o \
|
| 334 |
|
|
tb_ethernet.eth_top.mtxerr_pad_o \
|
| 335 |
|
|
|
| 336 |
|
|
add group \
|
| 337 |
|
|
"MAC RX" \
|
| 338 |
|
|
tb_ethernet.eth_top.mrx_clk_pad_i \
|
| 339 |
|
|
tb_ethernet.eth_top.mrxd_pad_i[3:0]'h \
|
| 340 |
|
|
tb_ethernet.eth_top.mrxdv_pad_i \
|
| 341 |
|
|
tb_ethernet.eth_top.mrxerr_pad_i \
|
| 342 |
|
|
|
| 343 |
|
|
add group \
|
| 344 |
|
|
"MAC MIIM interface" \
|
| 345 |
|
|
tb_ethernet.eth_top.mdc_pad_o \
|
| 346 |
|
|
tb_ethernet.eth_top.md_padoe_o \
|
| 347 |
|
|
tb_ethernet.eth_top.md_pad_o \
|
| 348 |
|
|
tb_ethernet.eth_top.md_pad_i \
|
| 349 |
|
|
tb_ethernet.eth_top.miim1.Busy \
|
| 350 |
|
|
tb_ethernet.eth_top.miim1.LinkFail \
|
| 351 |
|
|
tb_ethernet.eth_top.miim1.Nvalid \
|
| 352 |
|
|
tb_ethernet.eth_top.miim1.CtrlData[15:0]'h \
|
| 353 |
|
|
tb_ethernet.eth_top.miim1.UpdateMIIRX_DATAReg \
|
| 354 |
|
|
tb_ethernet.eth_top.miim1.Prsd[15:0]'h \
|
| 355 |
|
|
tb_ethernet.eth_top.miim1.Divider[7:0]'h \
|
| 356 |
|
|
|
| 357 |
|
|
add group \
|
| 358 |
|
|
"Test signals" \
|
| 359 |
|
|
tb_ethernet.test_name[799:0]'a \
|
| 360 |
310 |
tadejm |
tb_ethernet.eth_top.miim1.Nvalid \
|
| 361 |
|
|
tb_ethernet.eth_top.miim1.Busy \
|
| 362 |
|
|
tb_ethernet.eth_top.miim1.LinkFail \
|
| 363 |
|
|
tb_ethernet.eth_top.miim1.WriteDataOp \
|
| 364 |
|
|
tb_ethernet.eth_top.miim1.ReadStatusOp \
|
| 365 |
|
|
tb_ethernet.eth_top.miim1.ScanStatusOp \
|
| 366 |
172 |
mohor |
tb_ethernet.eth_top.ethreg1.MIISTATUSOut[31:0]'h \
|
| 367 |
310 |
tadejm |
tb_ethernet.eth_top.ethreg1.MIITX_DATAOut[31:0]'h \
|
| 368 |
|
|
tb_ethernet.eth_top.ethreg1.MIIRX_DATAOut[31:0]'h \
|
| 369 |
|
|
tb_ethernet.eth_top.ethreg1.MIIMODEROut[31:0]'h \
|
| 370 |
172 |
mohor |
tb_ethernet.eth_top.miim1.InProgress \
|
| 371 |
|
|
tb_ethernet.eth_top.miim1.InProgress_q1 \
|
| 372 |
|
|
tb_ethernet.eth_top.miim1.InProgress_q2 \
|
| 373 |
|
|
tb_ethernet.eth_top.miim1.InProgress_q3 \
|
| 374 |
|
|
tb_ethernet.eth_top.miim1.shftrg.ShiftReg[7:0]'h \
|
| 375 |
|
|
tb_ethernet.eth_phy.status_bit6_0[6:0]'h \
|
| 376 |
|
|
tb_ethernet.eth_phy.control_bit8_0[8:0]'h \
|
| 377 |
|
|
tb_ethernet.eth_phy.control_bit9 \
|
| 378 |
|
|
tb_ethernet.eth_phy.control_bit14_10[14:10]'h \
|
| 379 |
|
|
tb_ethernet.eth_phy.control_bit15 \
|
| 380 |
|
|
tb_ethernet.eth_phy.eth_speed \
|
| 381 |
|
|
tb_ethernet.eth_phy.m_rst_n_i \
|
| 382 |
|
|
tb_ethernet.eth_phy.mcoll_o \
|
| 383 |
|
|
tb_ethernet.eth_phy.mcrs_o \
|
| 384 |
|
|
tb_ethernet.eth_phy.md_get_phy_address \
|
| 385 |
|
|
tb_ethernet.eth_phy.md_get_reg_address \
|
| 386 |
|
|
tb_ethernet.eth_phy.md_get_reg_data_in \
|
| 387 |
|
|
tb_ethernet.eth_phy.md_put_reg_data_in \
|
| 388 |
|
|
tb_ethernet.eth_phy.md_put_reg_data_out \
|
| 389 |
|
|
tb_ethernet.eth_phy.reg_data_in[15:0]'h \
|
| 390 |
|
|
tb_ethernet.eth_phy.reg_data_out[15:0]'h \
|
| 391 |
|
|
tb_ethernet.eth_phy.register_bus_in[15:0]'h \
|
| 392 |
|
|
tb_ethernet.eth_phy.register_bus_out[15:0]'h \
|
| 393 |
|
|
tb_ethernet.eth_phy.reg_address[4:0]'h \
|
| 394 |
|
|
tb_ethernet.eth_phy.md_io_output \
|
| 395 |
|
|
tb_ethernet.eth_phy.md_io_enable \
|
| 396 |
|
|
tb_ethernet.eth_phy.md_io \
|
| 397 |
|
|
tb_ethernet.Mdc_O \
|
| 398 |
|
|
tb_ethernet.Mdi_I \
|
| 399 |
|
|
tb_ethernet.Mdio_IO \
|
| 400 |
|
|
tb_ethernet.Mdo_O \
|
| 401 |
|
|
tb_ethernet.Mdo_OE \
|
| 402 |
|
|
tb_ethernet.eth_phy.md_io_enable \
|
| 403 |
|
|
tb_ethernet.eth_phy.md_io_output \
|
| 404 |
|
|
tb_ethernet.eth_phy.md_io_rd_wr \
|
| 405 |
|
|
tb_ethernet.eth_phy.md_io_reg \
|
| 406 |
|
|
tb_ethernet.eth_phy.m_rst_n_i \
|
| 407 |
|
|
tb_ethernet.eth_phy.md_transfer_cnt'd \
|
| 408 |
|
|
tb_ethernet.eth_phy.md_transfer_cnt_reset \
|
| 409 |
|
|
tb_ethernet.eth_phy.mdc_i \
|
| 410 |
|
|
tb_ethernet.eth_phy.mrx_clk_o \
|
| 411 |
|
|
tb_ethernet.eth_phy.mrxd_o[3:0]'h \
|
| 412 |
|
|
tb_ethernet.eth_phy.mrxdv_o \
|
| 413 |
|
|
tb_ethernet.eth_phy.mrxerr_o \
|
| 414 |
|
|
tb_ethernet.eth_phy.mtx_clk_o \
|
| 415 |
|
|
tb_ethernet.eth_phy.mtxd_i[3:0]'h \
|
| 416 |
|
|
tb_ethernet.eth_phy.mtxen_i \
|
| 417 |
|
|
tb_ethernet.eth_phy.mtxerr_i \
|
| 418 |
|
|
tb_ethernet.eth_phy.phy_address[4:0]'h \
|
| 419 |
|
|
tb_ethernet.eth_phy.phy_id1[15:0]'h \
|
| 420 |
|
|
tb_ethernet.eth_phy.phy_id2[15:0]'h \
|
| 421 |
|
|
tb_ethernet.eth_phy.phy_log[31:0]'h \
|
| 422 |
|
|
tb_ethernet.eth_phy.reg_address[4:0]'h \
|
| 423 |
|
|
tb_ethernet.eth_phy.register_bus_in[15:0]'h \
|
| 424 |
|
|
tb_ethernet.eth_phy.register_bus_out[15:0]'h \
|
| 425 |
|
|
tb_ethernet.eth_phy.registers_addr_data_test_operation \
|
| 426 |
|
|
tb_ethernet.eth_phy.rx_link_down_halfperiod \
|
| 427 |
|
|
( \
|
| 428 |
|
|
minmax 0 93 \
|
| 429 |
|
|
) \
|
| 430 |
|
|
tb_ethernet.eth_phy.self_clear_d0 \
|
| 431 |
|
|
tb_ethernet.eth_phy.self_clear_d1 \
|
| 432 |
|
|
tb_ethernet.eth_phy.self_clear_d2 \
|
| 433 |
|
|
tb_ethernet.eth_phy.self_clear_d3 \
|
| 434 |
|
|
tb_ethernet.eth_phy.status_bit6_0[6:0]'h \
|
| 435 |
|
|
tb_ethernet.eth_phy.status_bit7 \
|
| 436 |
|
|
tb_ethernet.eth_phy.status_bit8 \
|
| 437 |
|
|
tb_ethernet.eth_phy.status_bit15_9[15:9]'h \
|
| 438 |
|
|
|
| 439 |
|
|
|
| 440 |
|
|
deselect all
|
| 441 |
319 |
tadejm |
open window designbrowser 1 geometry 56 121 855 550
|
