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//////////////////////////////////////////////////////////////////////
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//// ////
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//// eth_defines.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/cores/ethmac/ ////
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//// ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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//
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//
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//
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//
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//
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`define FPGA // Core is going to be implemented in FPGA and contains FPGA specific elements
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// Should be cleared for the ASIC implementation
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// Address is {`ETHERNET_SPACE, REG_SPACE, 12'hx}
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`define ETHERNET_SPACE 16'hf000 // Ethernet space is allocated from 0xF0000000 to 0xF000FFFF
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`define REG_SPACE 4'h0 // Register space is allocated to 0xF0000000
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`define BD_SPACE 4'h1 // Buffer descriptor space is allocated to 0xF0001000
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`define TX_DATA 4'h2 // Tx data is written to address 0xF0002000. Since DMA is used, TX_DATA is not used in equations.
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`define RX_DATA 4'h3 // Rx data is read from address 0xF0003000. Since DMA is used, RX_DATA is not used in equations.
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`define PACKET_SEND_ADR 32'h20 // Packet for TX are written to the address 0x20
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`define MODER_ADR 6'h0
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`define INT_SOURCE_ADR 6'h1
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`define INT_MASK_ADR 6'h2
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`define IPGT_ADR 6'h3
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`define IPGR1_ADR 6'h4
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`define IPGR2_ADR 6'h5
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`define PACKETLEN_ADR 6'h6
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`define COLLCONF_ADR 6'h7
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`define RX_BD_ADR_ADR 6'h8
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`define CTRLMODER_ADR 6'hA
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`define MIIMODER_ADR 6'hB
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`define MIICOMMAND_ADR 6'hC
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`define MIIADDRESS_ADR 6'hD
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`define MIITX_DATA_ADR 6'hE
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`define MIIRX_DATA_ADR 6'hF
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`define MIISTATUS_ADR 6'h10
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`define MAC_ADDR0_ADR 6'h11
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`define MAC_ADDR1_ADR 6'h12
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`define MODER_DEF 32'h0000A000
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`define INT_SOURCE_DEF 32'h00000000
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`define INT_MASK_DEF 32'h00000000
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`define IPGT_DEF 32'h00000012
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`define IPGR1_DEF 32'h0000000C
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`define IPGR2_DEF 32'h00000012
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`define PACKETLEN_DEF 32'h003C0600
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`define COLLCONF_DEF 32'h000F0040
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`define CTRLMODER_DEF 32'h00000000
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`define MIIMODER_DEF 32'h00000064
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`define MIICOMMAND_DEF 32'h00000000
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`define MIIADDRESS_DEF 32'h00000000
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`define MIITX_DATA_DEF 32'h00000000
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`define MIIRX_DATA_DEF 32'h00000000
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`define MIISTATUS_DEF 32'h00000000
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`define MAC_ADDR0_DEF 32'h00000000
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`define MAC_ADDR1_DEF 32'h00000000
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`define RX_BD_ADR_DEF 8'h0
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