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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_top.v                                                   ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/02 09:25:31  mohor
// Unconnected signals are now connected.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
 
 
`include "eth_defines.v"
`include "eth_timescale.v"
 
 
module eth_top
(
  // WISHBONE common
  WB_CLK_I, WB_RST_I, WB_DAT_I, WB_DAT_O,
 
  // WISHBONE slave
  WB_ADR_I, WB_SEL_I, WB_WE_I, WB_CYC_I, WB_STB_I, WB_ACK_O, WB_ERR_O,
  WB_REQ_O, WB_ACK_I, WB_ND_O, WB_RD_O,
 
  //TX
  MTxClk_I, MTxD_O, MTxEn_O, MTxErr_O,
 
  //RX
  MRxClk_I, MRxD_I, MRxDV_I, MRxErr_I, MColl_I, MCrs_I,
 
  // MIIM
  Mdc_O, Mdi_I, Mdo_O, Mdo_OE
);
 
 
parameter Tp = 1;
 
 
// WISHBONE common
input           WB_CLK_I;     // WISHBONE clock
input           WB_RST_I;     // WISHBONE reset
input   [31:0]  WB_DAT_I;     // WISHBONE data input
output  [31:0]  WB_DAT_O;     // WISHBONE data output
output          WB_ERR_O;     // WISHBONE error output
 
// WISHBONE slave
input   [31:0]  WB_ADR_I;     // WISHBONE address input
input    [3:0]  WB_SEL_I;     // WISHBONE byte select input
input           WB_WE_I;      // WISHBONE write enable input
input           WB_CYC_I;     // WISHBONE cycle input
input           WB_STB_I;     // WISHBONE strobe input
output          WB_ACK_O;     // WISHBONE acknowledge output
 
// DMA
input    [1:0]  WB_ACK_I;     // DMA acknowledge input
output   [1:0]  WB_REQ_O;     // DMA request output
output   [1:0]  WB_ND_O;      // DMA force new descriptor output
output          WB_RD_O;      // DMA restart descriptor output
 
// Tx
input           MTxClk_I;     // Transmit clock (from PHY)
output   [3:0]  MTxD_O;       // Transmit nibble (to PHY)
output          MTxEn_O;      // Transmit enable (to PHY)
output          MTxErr_O;     // Transmit error (to PHY)
 
// Rx
input           MRxClk_I;     // Receive clock (from PHY)
input    [3:0]  MRxD_I;       // Receive nibble (from PHY)
input           MRxDV_I;      // Receive data valid (from PHY)
input           MRxErr_I;     // Receive data error (from PHY)
 
// Common Tx and Rx
input           MColl_I;      // Collision (from PHY)
input           MCrs_I;       // Carrier sense (from PHY)
 
// MII Management interface
input           Mdi_I;        // MII data input (from I/O cell)
output          Mdc_O;        // MII Management data clock (to PHY)
output          Mdo_O;        // MII data output (to I/O cell)
output          Mdo_OE;       // MII data output enable (to I/O cell)
 
 
wire     [7:0]  r_ClkDiv;
wire            r_MiiNoPre;
wire    [15:0]  r_CtrlData;
wire     [4:0]  r_FIAD;
wire     [4:0]  r_RGAD;
wire            r_WCtrlData;
wire            r_RStat;
wire            r_ScanStat;
wire            NValid_stat;
wire            Busy_stat;
wire            LinkFail;
wire            r_MiiMRst;
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
wire            WCtrlDataStart;
wire            RStatStart;
wire            UpdateMIIRX_DATAReg;
 
wire            TxStartFrm;
wire            TxEndFrm;
wire            TxUsedData;
wire     [7:0]  TxData;
wire            TxRetry;
wire            TxAbort;
wire            TxUnderRun;
wire            TxDone;
 
 
 
 
// Connecting Miim module
eth_miim miim1
(
  .Clk(WB_CLK_I),                         .Reset(r_MiiMRst),                  .Divider(r_ClkDiv),
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
  .ScanStat(r_ScanStat),                  .Mdi(Mdi_I),                        .Mdo(Mdo_O),
  .MdoEn(Mdo_OE),                         .Mdc(Mdc_O),                        .Busy(Busy_stat),
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
 
 
 
 
wire        RegCs;          // Connected to registers
wire [31:0] RegDataOut;     // Multiplexed to WB_DAT_O
wire        r_DmaEn;        // DMA enable
wire        r_Rst;          // Reset
wire        r_LoopBck;      // Loopback
wire        r_TxEn;         // Tx Enable
wire        r_RxEn;         // Rx Enable
 
wire        MRxDV_Lb;       // Muxed MII receive data valid
wire        MRxErr_Lb;      // Muxed MII Receive Error
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
wire        Transmitting;   // Indication that TxEthMAC is transmitting
wire        r_HugEn;        // Huge packet enable
wire        r_DlyCrcEn;     // Delayed CRC enabled
wire [15:0] r_MaxFL;        // Maximum frame length
 
wire [15:0] r_MinFL;        // Minimum frame length
wire [47:0] r_MAC;          // MAC address
 
wire  [7:0] r_RxBDAddress;  // Receive buffer descriptor base address
wire  [6:0] r_IPGT;         // 
wire  [6:0] r_IPGR1;        // 
wire  [6:0] r_IPGR2;        // 
wire  [5:0] r_CollValid;    // 
wire        r_TPauseRq;     // Transmit PAUSE request pulse
 
wire  [3:0] r_MaxRet;       //
wire        r_NoBckof;      // 
wire        r_ExDfrEn;      // 
wire        RX_BD_ADR_Wr;   // Write enable that writes RX_BD_ADR to the registers.
wire        TPauseRq;       // Sinhronized Tx PAUSE request
wire [15:0] TxPauseTV;      // Tx PAUSE timer value
wire        r_TxFlow;       // Tx flow control enable
wire        r_IFG;          // Minimum interframe gap for incoming packets
 
wire        EthAddMatch;
wire        WB_STB_I_eth;
wire        WB_CYC_I_eth;
 
wire        DWord;
wire        RegAck;
wire        BDAck;
wire [31:0] DMA_WB_DAT_O;   // WB_DAT_O that comes from the WishboneDMA module
 
 
 
assign EthAddMatch = WB_ADR_I[31:16] == `ETHERNET_SPACE;
assign WB_STB_I_eth = WB_STB_I & EthAddMatch;
assign WB_CYC_I_eth = WB_STB_I & EthAddMatch;
 
assign WB_ERR_O = WB_STB_I & WB_CYC_I & EthAddMatch & ~DWord;
assign DWord = &WB_SEL_I;
assign RegCs = WB_STB_I & WB_CYC_I & DWord & EthAddMatch & (WB_ADR_I[15:12] == `REG_SPACE);
assign RegAck = RegCs;
assign WB_ACK_O = RegAck | BDAck;
 
 
// Selecting the WISHBONE output data
assign WB_DAT_O[31:0] = (RegCs & ~WB_WE_I)? RegDataOut : DMA_WB_DAT_O;
 
 
// Connecting Ethernet registers
eth_registers ethreg1
(
  .DataIn(WB_DAT_I),                      .Address(WB_ADR_I[7:2]),                    .Rw(WB_WE_I),
  .Cs(RegCs),                             .Clk(WB_CLK_I),                             .Reset(WB_RST_I),
  .DataOut(RegDataOut),                   .r_DmaEn(r_DmaEn),                          .r_RecSmall(),
  .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),
  .r_DlyCrcEn(r_DlyCrcEn),                .r_Rst(r_Rst),                              .r_FullD(r_FullD),
  .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),
  .r_IFG(r_IFG),                          .r_Pro(),                                   .r_Iam(),
  .r_Bro(),                               .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),
  .r_RxEn(r_RxEn),                        .Busy_IRQ(),                                .RxF_IRQ(),
  .RxB_IRQ(),                             .TxE_IRQ(),                                 .TxB_IRQ(),
  .Busy_MASK(),                           .RxF_MASK(),                                .RxB_MASK(),
  .TxE_MASK(),                            .TxB_MASK(),                                .r_IPGT(r_IPGT),
  .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),
  .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),
  .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),
  .r_MiiMRst(r_MiiMRst),                  .r_MiiNoPre(r_MiiNoPre),                    .r_ClkDiv(r_ClkDiv),
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
  .r_RxBDAddress(r_RxBDAddress),          .RX_BD_ADR_Wr(RX_BD_ADR_Wr)
);
 
 
 
wire  [7:0] RxData;
wire        RxValid;
wire        RxStartFrm;
wire        RxEndFrm;
 
wire        WillTransmit;            // Will transmit (to RxEthMAC)
wire        ResetCollision;          // Reset Collision (for synchronizing collision)
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
wire        WillSendControlFrame;
wire        TxCtrlEndFrm;
wire        ReceivedPauseFrm;
wire        ReceiveEnd;
wire        ReceivedPacketGood;
wire        ReceivedLengthOK;
 
// Connecting MACControl
eth_maccontrol maccontrol1
(
  .MTxClk(MTxClk_I),                            .TPauseRq(TPauseRq),
  .TxPauseTV(TxPauseTV),                        .TxDataIn(TxData),
  .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),
  .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),
  .TxAbortIn(TxAbortIn),                        .MRxClk(MRxClk_I),
  .RxData(RxData),                              .RxValid(RxValid),
  .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),
  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),
  .PassAll(r_PassAll),                          .TxFlow(r_TxFlow),
  .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),
  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),
  .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),
  .CrcEnOut(CrcEnOut),                          .TxReset(r_Rst),
  .RxReset(r_Rst),                              .ReceivedLengthOK(ReceivedLengthOK),
  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),
  .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),
  .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),
  .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),
  .ReceivedPauseFrm(ReceivedPauseFrm)
);
 
 
 
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
wire Collision;               // Synchronized Collision
 
reg CarrierSense_Tx1;
reg CarrierSense_Tx2;
reg Collision_Tx1;
reg Collision_Tx2;
 
reg RxEnSync;                 // Synchronized Receive Enable
reg CarrierSense_Rx1;
reg RxCarrierSense;           // Synchronized CarrierSense (to Rx clock)
reg WillTransmit_q;
reg WillTransmit_q2;
 
 
 
// Muxed MII receive data valid
assign MRxDV_Lb = r_LoopBck? MTxEn_O : MRxDV_I & RxEnSync;
 
// Muxed MII Receive Error
assign MRxErr_Lb = r_LoopBck? MTxErr_O : MRxErr_I & RxEnSync;
 
// Muxed MII Receive Data
assign MRxD_Lb[3:0] = r_LoopBck? MTxD_O[3:0] : MRxD_I[3:0];
 
 
 
// Connecting TxEthMAC
eth_txethmac txethmac1
(
  .MTxClk(MTxClk_I),                  .Reset(r_Rst),                      .CarrierSense(TxCarrierSense),
  .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),
  .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),
  .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),
  .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),
  .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),
  .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),
  .MaxFL(r_MaxFL),                    .MTxEn(MTxEn_O),                    .MTxD(MTxD_O),
  .MTxErr(MTxErr_O),                  .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),
  .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),
  .ResetCollision(ResetCollision)
);
 
 
 
 
wire  [15:0]  RxByteCnt;
wire          RxByteCntEq0;
wire          RxByteCntGreat2;
wire          RxByteCntMaxFrame;
wire          RxCrcError;
wire          RxStateIdle;
wire          RxStatePreamble;
wire          RxStateSFD;
wire   [1:0]  RxStateData;
 
 
 
 
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
  .MRxClk(MRxClk_I),                    .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),
  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),
  .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(r_Rst),
  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm),
  .RxEndFrm(RxEndFrm),                  .CrcHash(),                           .CrcHashGood(),
  .Broadcast(),                         .Multicast(),                         .ByteCnt(RxByteCnt),
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame),
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble),
  .StateSFD(RxStateSFD),                .StateData(RxStateData)
);
 
 
// MII Carrier Sense Synchronization
always @ (posedge MTxClk_I or posedge r_Rst)
begin
  if(r_Rst)
    begin
      CarrierSense_Tx1 <= #Tp 1'b0;
      CarrierSense_Tx2 <= #Tp 1'b0;
    end
  else
    begin
      CarrierSense_Tx1 <= #Tp MCrs_I;
      CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
    end
end
 
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
 
 
// MII Collision Synchronization
always @ (posedge MTxClk_I or posedge r_Rst)
begin
  if(r_Rst)
    begin
      Collision_Tx1 <= #Tp 1'b0;
      Collision_Tx2 <= #Tp 1'b0;
    end
  else
    begin
      Collision_Tx1 <= #Tp MColl_I;
      if(ResetCollision)
        Collision_Tx2 <= #Tp 1'b0;
      else
      if(Collision_Tx1)
        Collision_Tx2 <= #Tp 1'b1;
    end
end
 
 
// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;
 
 
 
// Carrier sense is synchronized to receive clock.
always @ (posedge MRxClk_I or posedge r_Rst)
begin
  if(r_Rst)
    begin
      CarrierSense_Rx1 <= #Tp 1'h0;
      RxCarrierSense <= #Tp 1'h0;
    end
  else
    begin
      CarrierSense_Rx1 <= #Tp MCrs_I;
      RxCarrierSense <= #Tp CarrierSense_Rx1;
    end
end
 
 
// Delayed WillTransmit
always @ (posedge MRxClk_I)
begin
  WillTransmit_q <= #Tp WillTransmit;
  WillTransmit_q2 <= #Tp WillTransmit_q;
end
 
 
assign Transmitting = ~r_FullD & WillTransmit_q2;
 
 
 
// Synchronized Receive Enable
always @ (posedge MRxClk_I or posedge r_Rst)
begin
  if(r_Rst)
    RxEnSync <= #Tp 1'b0;
  else
  if(~RxCarrierSense | RxCarrierSense & Transmitting)
    RxEnSync <= #Tp r_RxEn;
end
 
 
 
 
// Connecting WishboneDMA module
eth_wishbonedma wbdma
(
  .WB_CLK_I(WB_CLK_I),                .WB_RST_I(WB_RST_I),                      .WB_DAT_I(WB_DAT_I),
  .WB_DAT_O(DMA_WB_DAT_O),
 
  // WISHBONE slave
  .WB_ADR_I(WB_ADR_I),                .WB_SEL_I(WB_SEL_I),                      .WB_WE_I(WB_WE_I),
  .WB_CYC_I(WB_CYC_I_eth),            .WB_STB_I(WB_STB_I_eth),                  .WB_ACK_O(BDAck),
  .WB_REQ_O(WB_REQ_O),                .WB_ACK_I(WB_ACK_I),                      .WB_ND_O(WB_ND_O),
  .WB_RD_O(WB_RD_O),
 
    //TX
  .MTxClk(MTxClk_I),                  .TxStartFrm(TxStartFrm),                  .TxEndFrm(TxEndFrm),
  .TxUsedData(TxUsedData),            .TxData(TxData),                          .StatusIzTxEthMACModula(16'h0),
  .TxRetry(TxRetry),                  .TxAbort(TxAbort),                        .TxUnderRun(TxUnderRun),
  .TxDone(TxDone),                    .TPauseRq(TPauseRq),                      .TxPauseTV(TxPauseTV),
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),              .WillSendControlFrame(WillSendControlFrame),
  .TxCtrlEndFrm(TxCtrlEndFrm),
 
  // Register
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_RxBDAddress(r_RxBDAddress),
  .r_DmaEn(r_DmaEn),                  .RX_BD_ADR_Wr(RX_BD_ADR_Wr),
 
  //RX
  .MRxClk(MRxClk_I),                  .RxData(RxData),                          .RxValid(RxValid),
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm)
);
 
 
 
// Connecting MacStatus module
eth_macstatus macstatus1
(
  .MRxClk(MRxClk_I),                  .Reset(r_Rst),                            .TransmitEnd(),
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),  .ReceivedLengthOK(ReceivedLengthOK),
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                       .MRxDV(MRxDV_Lb),
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                .RxStatePreamble(RxStatePreamble),
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),              .RxByteCnt(RxByteCnt),
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),        .RxByteCntMaxFrame(RxByteCntMaxFrame),
  .ReceivedPauseFrm(ReceivedPauseFrm)
);
 
 
endmodule

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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_top.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/cores/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.2 2001/08/02 09:25:31 mohor`
45			`// Unconnected signals are now connected.`
46			`//`
47			`// Revision 1.1 2001/07/30 21:23:42 mohor`
48			`// Directory structure changed. Files checked and joind together.`
49			`//`
50			`//`
51			`//`
52			`//`
53			`//`
54
55
56
57			`include "eth_defines.v"
58			`include "eth_timescale.v"
59
60
61			`module eth_top`
62			`(`
63			`// WISHBONE common`
64			`WB_CLK_I, WB_RST_I, WB_DAT_I, WB_DAT_O,`
65
66			`// WISHBONE slave`
67			`WB_ADR_I, WB_SEL_I, WB_WE_I, WB_CYC_I, WB_STB_I, WB_ACK_O, WB_ERR_O,`
68			`WB_REQ_O, WB_ACK_I, WB_ND_O, WB_RD_O,`
69
70			`//TX`
71			`MTxClk_I, MTxD_O, MTxEn_O, MTxErr_O,`
72
73			`//RX`
74			`MRxClk_I, MRxD_I, MRxDV_I, MRxErr_I, MColl_I, MCrs_I,`
75
76			`// MIIM`
77			`Mdc_O, Mdi_I, Mdo_O, Mdo_OE`
78			`);`
79
80
81			`parameter Tp = 1;`
82
83
84			`// WISHBONE common`
85			`input WB_CLK_I; // WISHBONE clock`
86			`input WB_RST_I; // WISHBONE reset`
87			`input [31:0] WB_DAT_I; // WISHBONE data input`
88			`output [31:0] WB_DAT_O; // WISHBONE data output`
89			`output WB_ERR_O; // WISHBONE error output`
90
91			`// WISHBONE slave`
92			`input [31:0] WB_ADR_I; // WISHBONE address input`
93			`input [3:0] WB_SEL_I; // WISHBONE byte select input`
94			`input WB_WE_I; // WISHBONE write enable input`
95			`input WB_CYC_I; // WISHBONE cycle input`
96			`input WB_STB_I; // WISHBONE strobe input`
97			`output WB_ACK_O; // WISHBONE acknowledge output`
98
99			`// DMA`
100			`input [1:0] WB_ACK_I; // DMA acknowledge input`
101			`output [1:0] WB_REQ_O; // DMA request output`
102			`output [1:0] WB_ND_O; // DMA force new descriptor output`
103			`output WB_RD_O; // DMA restart descriptor output`
104
105			`// Tx`
106			`input MTxClk_I; // Transmit clock (from PHY)`
107			`output [3:0] MTxD_O; // Transmit nibble (to PHY)`
108			`output MTxEn_O; // Transmit enable (to PHY)`
109			`output MTxErr_O; // Transmit error (to PHY)`
110
111			`// Rx`
112			`input MRxClk_I; // Receive clock (from PHY)`
113			`input [3:0] MRxD_I; // Receive nibble (from PHY)`
114			`input MRxDV_I; // Receive data valid (from PHY)`
115			`input MRxErr_I; // Receive data error (from PHY)`
116
117			`// Common Tx and Rx`
118			`input MColl_I; // Collision (from PHY)`
119			`input MCrs_I; // Carrier sense (from PHY)`
120
121			`// MII Management interface`
122			`input Mdi_I; // MII data input (from I/O cell)`
123			`output Mdc_O; // MII Management data clock (to PHY)`
124			`output Mdo_O; // MII data output (to I/O cell)`
125			`output Mdo_OE; // MII data output enable (to I/O cell)`
126
127
128			`wire [7:0] r_ClkDiv;`
129			`wire r_MiiNoPre;`
130			`wire [15:0] r_CtrlData;`
131			`wire [4:0] r_FIAD;`
132			`wire [4:0] r_RGAD;`
133			`wire r_WCtrlData;`
134			`wire r_RStat;`
135			`wire r_ScanStat;`
136			`wire NValid_stat;`
137			`wire Busy_stat;`
138			`wire LinkFail;`
139			`wire r_MiiMRst;`
140			`wire [15:0] Prsd; // Read Status Data (data read from the PHY)`
141			`wire WCtrlDataStart;`
142			`wire RStatStart;`
143			`wire UpdateMIIRX_DATAReg;`
144
145			`wire TxStartFrm;`
146			`wire TxEndFrm;`
147			`wire TxUsedData;`
148			`wire [7:0] TxData;`
149			`wire TxRetry;`
150			`wire TxAbort;`
151			`wire TxUnderRun;`
152			`wire TxDone;`
153
154
155
156
157			`// Connecting Miim module`
158			`eth_miim miim1`
159			`(`
160			`.Clk(WB_CLK_I), .Reset(r_MiiMRst), .Divider(r_ClkDiv),`
161			`.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),`
162			`.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),`
163			`.ScanStat(r_ScanStat), .Mdi(Mdi_I), .Mdo(Mdo_O),`
164			`.MdoEn(Mdo_OE), .Mdc(Mdc_O), .Busy(Busy_stat),`
165			`.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),`
166			`.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)`
167			`);`
168
169
170
171
172			`wire RegCs; // Connected to registers`
173			`wire [31:0] RegDataOut; // Multiplexed to WB_DAT_O`
174			`wire r_DmaEn; // DMA enable`
175			`wire r_Rst; // Reset`
176			`wire r_LoopBck; // Loopback`
177			`wire r_TxEn; // Tx Enable`
178			`wire r_RxEn; // Rx Enable`
179
180			`wire MRxDV_Lb; // Muxed MII receive data valid`
181			`wire MRxErr_Lb; // Muxed MII Receive Error`
182			`wire [3:0] MRxD_Lb; // Muxed MII Receive Data`
183			`wire Transmitting; // Indication that TxEthMAC is transmitting`
184			`wire r_HugEn; // Huge packet enable`
185			`wire r_DlyCrcEn; // Delayed CRC enabled`
186			`wire [15:0] r_MaxFL; // Maximum frame length`
187
188			`wire [15:0] r_MinFL; // Minimum frame length`
189			`wire [47:0] r_MAC; // MAC address`
190
191			`wire [7:0] r_RxBDAddress; // Receive buffer descriptor base address`
192			`wire [6:0] r_IPGT; //`
193			`wire [6:0] r_IPGR1; //`
194			`wire [6:0] r_IPGR2; //`
195			`wire [5:0] r_CollValid; //`
196			`wire r_TPauseRq; // Transmit PAUSE request pulse`
197
198			`wire [3:0] r_MaxRet; //`
199			`wire r_NoBckof; //`
200			`wire r_ExDfrEn; //`
201			`wire RX_BD_ADR_Wr; // Write enable that writes RX_BD_ADR to the registers.`
202			`wire TPauseRq; // Sinhronized Tx PAUSE request`
203			`wire [15:0] TxPauseTV; // Tx PAUSE timer value`
204			`wire r_TxFlow; // Tx flow control enable`
205			`wire r_IFG; // Minimum interframe gap for incoming packets`
206
207			`wire EthAddMatch;`
208			`wire WB_STB_I_eth;`
209			`wire WB_CYC_I_eth;`
210
211			`wire DWord;`
212			`wire RegAck;`
213			`wire BDAck;`
214			`wire [31:0] DMA_WB_DAT_O; // WB_DAT_O that comes from the WishboneDMA module`
215
216
217
218			assign EthAddMatch = WB_ADR_I[31:16] == `ETHERNET_SPACE;
219			`assign WB_STB_I_eth = WB_STB_I & EthAddMatch;`
220			`assign WB_CYC_I_eth = WB_STB_I & EthAddMatch;`
221
222			`assign WB_ERR_O = WB_STB_I & WB_CYC_I & EthAddMatch & ~DWord;`
223			`assign DWord = &WB_SEL_I;`
224			assign RegCs = WB_STB_I & WB_CYC_I & DWord & EthAddMatch & (WB_ADR_I[15:12] == `REG_SPACE);
225			`assign RegAck = RegCs;`
226			`assign WB_ACK_O = RegAck \| BDAck;`
227
228
229			`// Selecting the WISHBONE output data`
230			`assign WB_DAT_O[31:0] = (RegCs & ~WB_WE_I)? RegDataOut : DMA_WB_DAT_O;`
231
232
233			`// Connecting Ethernet registers`
234			`eth_registers ethreg1`
235			`(`
236			`.DataIn(WB_DAT_I), .Address(WB_ADR_I[7:2]), .Rw(WB_WE_I),`
237			`.Cs(RegCs), .Clk(WB_CLK_I), .Reset(WB_RST_I),`
238			`.DataOut(RegDataOut), .r_DmaEn(r_DmaEn), .r_RecSmall(),`
239			`.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),`
240			`.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD),`
241			`.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),`
242			`.r_IFG(r_IFG), .r_Pro(), .r_Iam(),`
243			`.r_Bro(), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),`
244			`.r_RxEn(r_RxEn), .Busy_IRQ(), .RxF_IRQ(),`
245			`.RxB_IRQ(), .TxE_IRQ(), .TxB_IRQ(),`
246			`.Busy_MASK(), .RxF_MASK(), .RxB_MASK(),`
247			`.TxE_MASK(), .TxB_MASK(), .r_IPGT(r_IPGT),`
248			`.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),`
249			`.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),`
250			`.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),`
251			`.r_MiiMRst(r_MiiMRst), .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),`
252			`.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),`
253			`.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),`
254			`.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),`
255			`.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),`
256			`.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),`
257			`.r_RxBDAddress(r_RxBDAddress), .RX_BD_ADR_Wr(RX_BD_ADR_Wr)`
258			`);`
259
260
261
262			`wire [7:0] RxData;`
263			`wire RxValid;`
264			`wire RxStartFrm;`
265			`wire RxEndFrm;`
266
267			`wire WillTransmit; // Will transmit (to RxEthMAC)`
268			`wire ResetCollision; // Reset Collision (for synchronizing collision)`
269			`wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)`
270			`wire WillSendControlFrame;`
271			`wire TxCtrlEndFrm;`
272			`wire ReceivedPauseFrm;`
273			`wire ReceiveEnd;`
274			`wire ReceivedPacketGood;`
275			`wire ReceivedLengthOK;`
276
277			`// Connecting MACControl`
278			`eth_maccontrol maccontrol1`
279			`(`
280			`.MTxClk(MTxClk_I), .TPauseRq(TPauseRq),`
281			`.TxPauseTV(TxPauseTV), .TxDataIn(TxData),`
282			`.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),`
283			`.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),`
284			`.TxAbortIn(TxAbortIn), .MRxClk(MRxClk_I),`
285			`.RxData(RxData), .RxValid(RxValid),`
286			`.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),`
287			`.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),`
288			`.PassAll(r_PassAll), .TxFlow(r_TxFlow),`
289			`.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),`
290			`.MAC(r_MAC), .PadIn(r_Pad \| PerPacketPad),`
291			`.PadOut(PadOut), .CrcEnIn(r_CrcEn \| PerPacketCrcEn),`
292			`.CrcEnOut(CrcEnOut), .TxReset(r_Rst),`
293			`.RxReset(r_Rst), .ReceivedLengthOK(ReceivedLengthOK),`
294			`.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),`
295			`.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),`
296			`.TxDoneOut(TxDone), .TxAbortOut(TxAbort),`
297			`.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),`
298			`.ReceivedPauseFrm(ReceivedPauseFrm)`
299			`);`
300
301
302
303			`wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)`
304			`wire Collision; // Synchronized Collision`
305
306			`reg CarrierSense_Tx1;`
307			`reg CarrierSense_Tx2;`
308			`reg Collision_Tx1;`
309			`reg Collision_Tx2;`
310
311			`reg RxEnSync; // Synchronized Receive Enable`
312			`reg CarrierSense_Rx1;`
313			`reg RxCarrierSense; // Synchronized CarrierSense (to Rx clock)`
314			`reg WillTransmit_q;`
315			`reg WillTransmit_q2;`
316
317
318
319			`// Muxed MII receive data valid`
320			`assign MRxDV_Lb = r_LoopBck? MTxEn_O : MRxDV_I & RxEnSync;`
321
322			`// Muxed MII Receive Error`
323			`assign MRxErr_Lb = r_LoopBck? MTxErr_O : MRxErr_I & RxEnSync;`
324
325			`// Muxed MII Receive Data`
326			`assign MRxD_Lb[3:0] = r_LoopBck? MTxD_O[3:0] : MRxD_I[3:0];`
327
328
329
330			`// Connecting TxEthMAC`
331			`eth_txethmac txethmac1`
332			`(`
333			`.MTxClk(MTxClk_I), .Reset(r_Rst), .CarrierSense(TxCarrierSense),`
334			`.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),`
335			`.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),`
336			`.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),`
337			`.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),`
338			`.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),`
339			`.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),`
340			`.MaxFL(r_MaxFL), .MTxEn(MTxEn_O), .MTxD(MTxD_O),`
341			`.MTxErr(MTxErr_O), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),`
342			`.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),`
343			`.ResetCollision(ResetCollision)`
344			`);`
345
346
347
348
349			`wire [15:0] RxByteCnt;`
350			`wire RxByteCntEq0;`
351			`wire RxByteCntGreat2;`
352			`wire RxByteCntMaxFrame;`
353			`wire RxCrcError;`
354			`wire RxStateIdle;`
355			`wire RxStatePreamble;`
356			`wire RxStateSFD;`
357			`wire [1:0] RxStateData;`
358
359
360
361
362			`// Connecting RxEthMAC`
363			`eth_rxethmac rxethmac1`
364			`(`
365			`.MRxClk(MRxClk_I), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),`
366			`.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),`
367			`.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(r_Rst),`
368			`.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),`
369			`.RxEndFrm(RxEndFrm), .CrcHash(), .CrcHashGood(),`
370			`.Broadcast(), .Multicast(), .ByteCnt(RxByteCnt),`
371			`.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),`
372			`.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),`
373			`.StateSFD(RxStateSFD), .StateData(RxStateData)`
374			`);`
375
376
377			`// MII Carrier Sense Synchronization`
378			`always @ (posedge MTxClk_I or posedge r_Rst)`
379			`begin`
380			`if(r_Rst)`
381			`begin`
382			`CarrierSense_Tx1 <= #Tp 1'b0;`
383			`CarrierSense_Tx2 <= #Tp 1'b0;`
384			`end`
385			`else`
386			`begin`
387			`CarrierSense_Tx1 <= #Tp MCrs_I;`
388			`CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;`
389			`end`
390			`end`
391
392			`assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;`
393
394
395			`// MII Collision Synchronization`
396			`always @ (posedge MTxClk_I or posedge r_Rst)`
397			`begin`
398			`if(r_Rst)`
399			`begin`
400			`Collision_Tx1 <= #Tp 1'b0;`
401			`Collision_Tx2 <= #Tp 1'b0;`
402			`end`
403			`else`
404			`begin`
405			`Collision_Tx1 <= #Tp MColl_I;`
406			`if(ResetCollision)`
407			`Collision_Tx2 <= #Tp 1'b0;`
408			`else`
409			`if(Collision_Tx1)`
410			`Collision_Tx2 <= #Tp 1'b1;`
411			`end`
412			`end`
413
414
415			`// Synchronized Collision`
416			`assign Collision = ~r_FullD & Collision_Tx2;`
417
418
419
420			`// Carrier sense is synchronized to receive clock.`
421			`always @ (posedge MRxClk_I or posedge r_Rst)`
422			`begin`
423			`if(r_Rst)`
424			`begin`
425			`CarrierSense_Rx1 <= #Tp 1'h0;`
426			`RxCarrierSense <= #Tp 1'h0;`
427			`end`
428			`else`
429			`begin`
430			`CarrierSense_Rx1 <= #Tp MCrs_I;`
431			`RxCarrierSense <= #Tp CarrierSense_Rx1;`
432			`end`
433			`end`
434
435
436			`// Delayed WillTransmit`
437			`always @ (posedge MRxClk_I)`
438			`begin`
439			`WillTransmit_q <= #Tp WillTransmit;`
440			`WillTransmit_q2 <= #Tp WillTransmit_q;`
441			`end`
442
443
444			`assign Transmitting = ~r_FullD & WillTransmit_q2;`
445
446
447
448			`// Synchronized Receive Enable`
449			`always @ (posedge MRxClk_I or posedge r_Rst)`
450			`begin`
451			`if(r_Rst)`
452			`RxEnSync <= #Tp 1'b0;`
453			`else`
454			`if(~RxCarrierSense \| RxCarrierSense & Transmitting)`
455			`RxEnSync <= #Tp r_RxEn;`
456			`end`
457
458
459
460
461			`// Connecting WishboneDMA module`
462			`eth_wishbonedma wbdma`
463			`(`
464			`.WB_CLK_I(WB_CLK_I), .WB_RST_I(WB_RST_I), .WB_DAT_I(WB_DAT_I),`
465			`.WB_DAT_O(DMA_WB_DAT_O),`
466
467			`// WISHBONE slave`
468			`.WB_ADR_I(WB_ADR_I), .WB_SEL_I(WB_SEL_I), .WB_WE_I(WB_WE_I),`
469			`.WB_CYC_I(WB_CYC_I_eth), .WB_STB_I(WB_STB_I_eth), .WB_ACK_O(BDAck),`
470			`.WB_REQ_O(WB_REQ_O), .WB_ACK_I(WB_ACK_I), .WB_ND_O(WB_ND_O),`
471			`.WB_RD_O(WB_RD_O),`
472
473			`//TX`
474			`.MTxClk(MTxClk_I), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),`
475			`.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0),`
476			`.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),`
477			`.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV),`
478			`.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), .WillSendControlFrame(WillSendControlFrame),`
479			`.TxCtrlEndFrm(TxCtrlEndFrm),`
480
481			`// Register`
482			`.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDAddress(r_RxBDAddress),`
483			`.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr),`
484
485			`//RX`
486			`.MRxClk(MRxClk_I), .RxData(RxData), .RxValid(RxValid),`
487			`.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm)`
488			`);`
489
490
491
492			`// Connecting MacStatus module`
493			`eth_macstatus macstatus1`
494			`(`
495			`.MRxClk(MRxClk_I), .Reset(r_Rst), .TransmitEnd(),`
496			`.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),`
497			`.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),`
498			`.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),`
499			`.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),`
500			`.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),`
501			`.ReceivedPauseFrm(ReceivedPauseFrm)`
502			`);`
503
504
505			`endmodule`