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mohor |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "wb_bus_mon.v" ////
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//// ////
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170 |
mohor |
//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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169 |
mohor |
//// ////
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//// Author(s): ////
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mohor |
//// - Miha Dolenc (mihad@opencores.org) ////
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mohor |
//// ////
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mohor |
//// All additional information is available in the README.pdf ////
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169 |
mohor |
//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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170 |
mohor |
//// Copyright (C) 2002 Authors ////
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169 |
mohor |
//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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170 |
mohor |
// Revision 1.1 2002/09/13 11:57:20 mohor
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// New testbench. Thanks to Tadej M - "The Spammer".
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//
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169 |
mohor |
// Revision 1.1 2002/02/01 13:39:43 mihad
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// Initial testbench import. Still under development
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//
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// Revision 1.1 2001/08/06 18:12:58 mihad
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// Pocasi delamo kompletno zadevo
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//
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//
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`include "wb_model_defines.v"
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// WISHBONE bus monitor module - it connects to WISHBONE master signals and
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// monitors for any illegal combinations appearing on the bus.
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module WB_BUS_MON(
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CLK_I,
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RST_I,
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ACK_I,
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ADDR_O,
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CYC_O,
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DAT_I,
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DAT_O,
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ERR_I,
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RTY_I,
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SEL_O,
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STB_O,
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WE_O,
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TAG_I,
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TAG_O,
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CAB_O,
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log_file_desc
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) ;
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input CLK_I ;
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input RST_I ;
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input ACK_I ;
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input [(`WB_ADDR_WIDTH-1):0] ADDR_O ;
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input CYC_O ;
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input [(`WB_DATA_WIDTH-1):0] DAT_I ;
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input [(`WB_DATA_WIDTH-1):0] DAT_O ;
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input ERR_I ;
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input RTY_I ;
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input [(`WB_SEL_WIDTH-1):0] SEL_O ;
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input STB_O ;
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input WE_O ;
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input [(`WB_TAG_WIDTH-1):0] TAG_I ;
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input [(`WB_TAG_WIDTH-1):0] TAG_O ;
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input CAB_O ;
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input [31:0] log_file_desc ;
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always@(posedge CLK_I or posedge RST_I)
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begin
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if (RST_I)
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begin
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// when reset is applied, all control signals must be low
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if (CYC_O)
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begin
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$display("*E (%0t) CYC_O active under reset", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)CYC_O active under reset", $time) ;
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end
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if (STB_O)
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begin
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$display("*E (%0t) STB_O active under reset", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active under reset", $time) ;
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end
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/*if (ACK_I)
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$display("ACK_I active under reset") ;*/
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if (ERR_I)
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begin
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$display("*E (%0t) ERR_I active under reset", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active under reset", $time) ;
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end
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if (RTY_I)
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begin
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$display("*E (%0t) RTY_I active under reset", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active under reset", $time) ;
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end
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if (CAB_O)
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begin
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$display("*E (%0t) CAB_O active under reset", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active under reset", $time) ;
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end
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end // reset
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else
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if (~CYC_O)
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begin
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// when cycle indicator is low, all control signals must be low
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if (STB_O)
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begin
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$display("*E (%0t) STB_O active without CYC_O being active", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)STB_O active without CYC_O being active", $time) ;
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end
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if (ACK_I)
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begin
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$display("*E (%0t) ACK_I active without CYC_O being active", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I active without CYC_O being active", $time) ;
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end
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if (ERR_I)
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begin
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$display("*E (%0t) ERR_I active without CYC_O being active", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I active without CYC_O being active", $time) ;
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end
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if (RTY_I)
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begin
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$display("*E (%0t) RTY_I active without CYC_O being active", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I active without CYC_O being active", $time) ;
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end
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if (CAB_O)
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begin
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$display("*E (%0t) CAB_O active without CYC_O being active", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O active without CYC_O being active", $time) ;
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end
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end // ~CYC_O
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end
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reg [`WB_DATA_WIDTH-1:0] previous_data ;
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reg [`WB_ADDR_WIDTH-1:0] previous_address ;
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reg [`WB_SEL_WIDTH-1:0] previous_sel ;
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reg previous_stb ;
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reg previous_ack ;
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reg previous_err ;
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reg previous_rty ;
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reg previous_cyc ;
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reg can_change ;
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always@(posedge CLK_I or posedge RST_I)
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begin
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if (RST_I)
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begin
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previous_stb <= 1'b0 ;
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previous_ack <= 1'b0 ;
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previous_err <= 1'b0 ;
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previous_rty <= 1'b0 ;
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previous_cyc <= 1'b0 ;
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end
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else
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begin
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previous_stb <= STB_O ;
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previous_ack <= ACK_I ;
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previous_err <= ERR_I ;
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previous_rty <= RTY_I ;
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previous_cyc <= CYC_O ;
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end
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end
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// cycle monitor
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always@(posedge CLK_I)
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begin
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if (CYC_O && ~RST_I) // cycle in progress
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begin
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if (STB_O)
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begin
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// check for two control signals active at same edge
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if ( ACK_I && RTY_I )
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begin
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$display("*E (%0t) ACK_I and RTY_I asserted at the same time during cycle", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and RTY_I asserted at the same time during cycle", $time) ;
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end
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if ( ACK_I && ERR_I )
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begin
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$display("*E (%0t) ACK_I and ERR_I asserted at the same time during cycle", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)ACK_I and ERR_I asserted at the same time during cycle", $time) ;
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end
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if ( RTY_I && ERR_I )
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begin
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$display("*E (%0t) RTY_I and ERR_I asserted at the same time during cycle", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I and ERR_I asserted at the same time during cycle", $time) ;
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end
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if ( can_change !== 1 )
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begin
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if ( ADDR_O !== previous_address )
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begin
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$display("*E (%0t) WB bus monitor detected address change in the middle of the cycle!", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected address change in the middle of the cycle!", $time) ;
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end
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if ( SEL_O !== previous_sel )
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begin
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$display("*E (%0t) WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected select lines changed in the middle of the cycle!", $time) ;
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end
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if ( (WE_O !== 0) && ( DAT_O !== previous_data ) )
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begin
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$display("*E (%0t) WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
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$fdisplay(log_file_desc, "*E (%0t)(%m)WB bus monitor detected data lines changed in the middle of the cycle!", $time) ;
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end
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end
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if ( ACK_I || RTY_I || ERR_I )
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can_change = 1 ;
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else
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238 |
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begin
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previous_data = DAT_O ;
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previous_address = ADDR_O ;
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previous_sel = SEL_O ;
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can_change = 0 ;
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end
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244 |
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end // STB_O
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else
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247 |
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begin //~STB_O
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248 |
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// while STB_O is inactive, only ACK_I is allowed to be active
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249 |
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if ( ERR_I )
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250 |
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begin
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251 |
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$display("*E (%0t) ERR_I asserted during cycle without STB_O", $time) ;
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252 |
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$fdisplay(log_file_desc, "*E (%0t)(%m)ERR_I asserted during cycle without STB_O", $time) ;
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253 |
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end
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254 |
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if ( RTY_I )
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255 |
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begin
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256 |
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$display("*E (%0t) RTY_I asserted during cycle without STB_O", $time) ;
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257 |
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$fdisplay(log_file_desc, "*E (%0t)(%m)RTY_I asserted during cycle without STB_O", $time) ;
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258 |
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end
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259 |
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260 |
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if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
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261 |
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begin
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262 |
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$display("STB_O de-asserted without reception of slave response") ;
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263 |
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$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
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264 |
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end
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265 |
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|
266 |
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can_change = 1 ;
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267 |
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end // ~STB_O
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268 |
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end // cycle in progress
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269 |
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else if (!RST_I)
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270 |
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begin
|
271 |
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// cycle not in progress anymore
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272 |
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can_change = 1 ;
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273 |
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if ((previous_ack !== 1) && (previous_err !== 1) && (previous_rty !== 1) && (previous_stb !== 0))
|
274 |
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begin
|
275 |
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$display("STB_O de-asserted without reception of slave response") ;
|
276 |
|
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$fdisplay(log_file_desc, "STB_O de-asserted without reception of slave response") ;
|
277 |
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end
|
278 |
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end
|
279 |
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end // cycle monitor
|
280 |
|
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|
281 |
|
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// CAB_O monitor - CAB_O musn't change during one cycle
|
282 |
|
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reg [1:0] first_cab_val ;
|
283 |
|
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always@(posedge CLK_I or RST_I)
|
284 |
|
|
begin
|
285 |
|
|
if ((CYC_O === 0) || RST_I)
|
286 |
|
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first_cab_val <= 2'b00 ;
|
287 |
|
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else
|
288 |
|
|
begin
|
289 |
|
|
// cycle in progress - is this first clock edge in a cycle ?
|
290 |
|
|
if (first_cab_val[1] === 1'b0)
|
291 |
|
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first_cab_val <= {1'b1, CAB_O} ;
|
292 |
|
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else if ( first_cab_val[0] !== CAB_O )
|
293 |
|
|
begin
|
294 |
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$display("*E (%0t) CAB_O value changed during cycle", $time) ;
|
295 |
|
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$fdisplay(log_file_desc, "*E (%0t)(%m)CAB_O value changed during cycle", $time) ;
|
296 |
|
|
end
|
297 |
|
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end
|
298 |
|
|
end // CAB_O monitor
|
299 |
|
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|
300 |
|
|
// WE_O monitor for consecutive address bursts
|
301 |
|
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reg [1:0] first_we_val ;
|
302 |
|
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always@(posedge CLK_I or posedge RST_I)
|
303 |
|
|
begin
|
304 |
|
|
if (~CYC_O || ~CAB_O || RST_I)
|
305 |
|
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first_we_val <= 2'b00 ;
|
306 |
|
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else
|
307 |
|
|
if (STB_O)
|
308 |
|
|
begin
|
309 |
|
|
// cycle in progress - is this first clock edge in a cycle ?
|
310 |
|
|
if (first_we_val[1] == 1'b0)
|
311 |
|
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first_we_val <= {1'b1, WE_O} ;
|
312 |
|
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else if ( first_we_val[0] != WE_O )
|
313 |
|
|
begin
|
314 |
|
|
$display("*E (%0t) WE_O value changed during CAB cycle", $time) ;
|
315 |
|
|
$fdisplay(log_file_desc, "*E (%0t)(%m)WE_O value changed during CAB cycle", $time) ;
|
316 |
|
|
end
|
317 |
|
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end
|
318 |
|
|
end // CAB_O monitor
|
319 |
|
|
|
320 |
|
|
// address monitor for consecutive address bursts
|
321 |
|
|
reg [`WB_ADDR_WIDTH:0] address ;
|
322 |
|
|
always@(posedge CLK_I or posedge RST_I)
|
323 |
|
|
begin
|
324 |
|
|
if (~CYC_O || ~CAB_O || RST_I)
|
325 |
|
|
address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
|
326 |
|
|
else
|
327 |
|
|
begin
|
328 |
|
|
if (STB_O && ACK_I)
|
329 |
|
|
begin
|
330 |
|
|
if (address[`WB_ADDR_WIDTH] == 1'b0)
|
331 |
|
|
address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
|
332 |
|
|
else
|
333 |
|
|
begin
|
334 |
|
|
if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
|
335 |
|
|
begin
|
336 |
|
|
$display("*E (%0t) Consecutive address burst address incrementing incorrect", $time) ;
|
337 |
|
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Consecutive address burst address incrementing incorrect", $time) ;
|
338 |
|
|
end
|
339 |
|
|
else
|
340 |
|
|
address <= {1'b1, (ADDR_O + `WB_SEL_WIDTH)} ;
|
341 |
|
|
end
|
342 |
|
|
end
|
343 |
|
|
end
|
344 |
|
|
end // address monitor
|
345 |
|
|
|
346 |
|
|
// data monitor
|
347 |
|
|
always@(posedge CLK_I or posedge RST_I)
|
348 |
|
|
begin
|
349 |
|
|
if (CYC_O && STB_O && ~RST_I)
|
350 |
|
|
begin
|
351 |
|
|
if ( ((^ADDR_O) !== 1'b1) && ((^ADDR_O) !== 1'b0) )
|
352 |
|
|
begin
|
353 |
|
|
$display("*E (%0t) Master provided invalid address and qualified it with STB_O", $time) ;
|
354 |
|
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid address and qualified it with STB_O", $time) ;
|
355 |
|
|
end
|
356 |
|
|
if ( WE_O )
|
357 |
|
|
begin
|
358 |
|
|
if (
|
359 |
|
|
(SEL_O[0] && (((^DAT_O[7:0]) !== 1'b0) && ((^DAT_O[7:0]) !== 1'b1))) ||
|
360 |
|
|
(SEL_O[1] && (((^DAT_O[15:8]) !== 1'b0) && ((^DAT_O[15:8]) !== 1'b1))) ||
|
361 |
|
|
(SEL_O[2] && (((^DAT_O[23:16]) !== 1'b0) && ((^DAT_O[23:16]) !== 1'b1))) ||
|
362 |
|
|
(SEL_O[3] && (((^DAT_O[31:24]) !== 1'b0) && ((^DAT_O[31:24]) !== 1'b1)))
|
363 |
|
|
)
|
364 |
|
|
begin
|
365 |
|
|
$display("*E (%0t) Master provided invalid data during write and qualified it with STB_O", $time) ;
|
366 |
|
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Master provided invalid data during write and qualified it with STB_O", $time) ;
|
367 |
|
|
$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;
|
368 |
|
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", $time, SEL_O, DAT_O) ;
|
369 |
|
|
end
|
370 |
|
|
|
371 |
|
|
end
|
372 |
|
|
else
|
373 |
|
|
if (~WE_O && ACK_I)
|
374 |
|
|
begin
|
375 |
|
|
if (
|
376 |
|
|
(SEL_O[0] && (((^DAT_I[7:0]) !== 1'b0) && ((^DAT_I[7:0]) !== 1'b1))) ||
|
377 |
|
|
(SEL_O[1] && (((^DAT_I[15:8]) !== 1'b0) && ((^DAT_I[15:8]) !== 1'b1))) ||
|
378 |
|
|
(SEL_O[2] && (((^DAT_I[23:16]) !== 1'b0) && ((^DAT_I[23:16]) !== 1'b1))) ||
|
379 |
|
|
(SEL_O[3] && (((^DAT_I[31:24]) !== 1'b0) && ((^DAT_I[31:24]) !== 1'b1)))
|
380 |
|
|
)
|
381 |
|
|
begin
|
382 |
|
|
$display("*E (%0t) Slave provided invalid data during read and qualified it with ACK_I", $time) ;
|
383 |
|
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Slave provided invalid data during read and qualified it with ACK_I", $time) ;
|
384 |
|
|
$display("*E (%0t) Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;
|
385 |
|
|
$fdisplay(log_file_desc, "*E (%0t)(%m)Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", $time, SEL_O, DAT_I) ;
|
386 |
|
|
end
|
387 |
|
|
end
|
388 |
|
|
end
|
389 |
|
|
end
|
390 |
|
|
|
391 |
|
|
initial
|
392 |
|
|
begin
|
393 |
|
|
previous_data = 0 ;
|
394 |
|
|
previous_address = 0 ;
|
395 |
|
|
can_change = 1 ;
|
396 |
|
|
end
|
397 |
|
|
endmodule // BUS_MON
|