1 |
169 |
mohor |
// WISHBONE frequency in GHz
|
2 |
|
|
`define WB_FREQ 0.100
|
3 |
|
|
|
4 |
|
|
// memory frequency in GHz
|
5 |
|
|
`define MEM_FREQ 0.100
|
6 |
|
|
|
7 |
|
|
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
|
8 |
|
|
`define Tsetup 4
|
9 |
|
|
`define Thold 1
|
10 |
|
|
|
11 |
|
|
// how many clock cycles should model wait for design's response - integer 32 bit value
|
12 |
|
|
`define WAIT_FOR_RESPONSE 1023
|
13 |
|
|
|
14 |
|
|
// maximum number of transactions allowed in single call to block or cab transfer routines
|
15 |
|
|
`define MAX_BLK_SIZE 1024
|
16 |
|
|
|
17 |
|
|
// maximum retry terminations allowed for WISHBONE master to repeat an access
|
18 |
|
|
`define WB_TB_MAX_RTY 0
|
19 |
|
|
|
20 |
|
|
|
21 |
|
|
// some common types and defines
|
22 |
|
|
`define WB_ADDR_WIDTH 32
|
23 |
|
|
`define WB_DATA_WIDTH 32
|
24 |
|
|
`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
|
25 |
|
|
`define WB_TAG_WIDTH 1
|
26 |
|
|
`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
|
27 |
|
|
`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
|
28 |
|
|
`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
|
29 |
|
|
`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
|
30 |
|
|
|
31 |
|
|
// read cycle stimulus - consists of:
|
32 |
|
|
// - address field - which address read will be performed from
|
33 |
|
|
// - sel field - what byte select value should be
|
34 |
|
|
// - tag field - what tag values should be put on the bus
|
35 |
|
|
`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
|
36 |
|
|
`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
|
37 |
|
|
`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
|
38 |
|
|
`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
|
39 |
|
|
`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
|
40 |
|
|
|
41 |
|
|
// read cycle return type consists of:
|
42 |
|
|
// - read data field
|
43 |
|
|
// - tag field received from WISHBONE
|
44 |
|
|
// - wishbone slave response fields - ACK, ERR and RTY
|
45 |
|
|
// - test bench error indicator (when testcase has not used wb master model properly)
|
46 |
|
|
// - how much data was actually transfered
|
47 |
|
|
`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
|
48 |
|
|
`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
|
49 |
|
|
`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
|
50 |
|
|
`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
|
51 |
|
|
|
52 |
|
|
// write cycle stimulus type consists of
|
53 |
|
|
// - address field
|
54 |
|
|
// - data field
|
55 |
|
|
// - sel field
|
56 |
|
|
// - tag field
|
57 |
|
|
`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
|
58 |
|
|
`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
|
59 |
|
|
`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
|
60 |
|
|
`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
|
61 |
|
|
`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
|
62 |
|
|
|
63 |
|
|
// length of WRITE_STIMULUS
|
64 |
|
|
`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
|
65 |
|
|
|
66 |
|
|
// write cycle return type consists of:
|
67 |
|
|
// - test bench error indicator (when testcase has not used wb master model properly)
|
68 |
|
|
// - wishbone slave response fields - ACK, ERR and RTY
|
69 |
|
|
// - tag field received from WISHBONE
|
70 |
|
|
// - how much data was actually transfered
|
71 |
|
|
`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
|
72 |
|
|
`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
|
73 |
|
|
|
74 |
|
|
// this four fields are common to both read and write routines return values
|
75 |
|
|
`define TB_ERROR_BIT [0]
|
76 |
|
|
`define CYC_ACK [1]
|
77 |
|
|
`define CYC_RTY [2]
|
78 |
|
|
`define CYC_ERR [3]
|
79 |
|
|
`define CYC_RESPONSE [3:1]
|
80 |
|
|
`define CYC_ACTUAL_TRANSFER [35:4]
|
81 |
|
|
|
82 |
|
|
// block transfer flags
|
83 |
|
|
`define WB_TRANSFER_FLAGS [41:0]
|
84 |
|
|
// consists of:
|
85 |
|
|
// - number of transfer cycles to perform
|
86 |
|
|
// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
|
87 |
|
|
// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
|
88 |
|
|
// - number of initial wait states to insert
|
89 |
|
|
// - number of subsequent wait states to insert
|
90 |
|
|
`define WB_TRANSFER_SIZE [41:10]
|
91 |
|
|
`define WB_TRANSFER_AUTO_RTY [8]
|
92 |
|
|
`define WB_TRANSFER_CAB [9]
|
93 |
|
|
`define INIT_WAITS [3:0]
|
94 |
|
|
`define SUBSEQ_WAITS [7:4]
|
95 |
|
|
|
96 |
|
|
// wb slave response
|
97 |
|
|
`define ACK_RESPONSE 3'b100
|
98 |
|
|
`define ERR_RESPONSE 3'b010
|
99 |
|
|
`define RTY_RESPONSE 3'b001
|
100 |
|
|
`define NO_RESPONSE 3'b000
|