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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_macstatus.v                                             ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12  2002/09/12 14:50:16  mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
// Revision 1.11  2002/09/04 18:38:03  mohor
// CarrierSenseLost status is not set when working in loopback mode.
//
// Revision 1.10  2002/07/25 18:17:46  mohor
// InvalidSymbol generation changed.
//
// Revision 1.9  2002/04/22 13:51:44  mohor
// Short frame and ReceivedLengthOK were not detected correctly.
//
// Revision 1.8  2002/02/18 10:40:17  mohor
// Small fixes.
//
// Revision 1.7  2002/02/15 17:07:39  mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.6  2002/02/11 09:18:21  mohor
// Tx status is written back to the BD.
//
// Revision 1.5  2002/02/08 16:21:54  mohor
// Rx status is written back to the BD.
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2  2001/09/11 14:17:00  mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
`include "timescale.v"
 
 
module eth_macstatus(
                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,
                      InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
                      r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
                      LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
                      RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,
                      StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
                      r_FullD
                    );
 
 
 
parameter Tp = 1;
 
 
input         MRxClk;
input         Reset;
input         RxCrcError;
input         MRxErr;
input         MRxDV;
 
input         RxStateSFD;
input   [1:0] RxStateData;
input         RxStatePreamble;
input         RxStateIdle;
input         Transmitting;
input  [15:0] RxByteCnt;
input         RxByteCntEq0;
input         RxByteCntGreat2;
input         RxByteCntMaxFrame;
input         ReceivedPauseFrm;
input   [3:0] MRxD;
input         Collision;
input   [5:0] CollValid;
input         r_RecSmall;
input  [15:0] r_MinFL;
input  [15:0] r_MaxFL;
input         r_HugEn;
input         StartTxDone;
input         StartTxAbort;
input   [3:0] RetryCnt;
input         MTxClk;
input         MaxCollisionOccured;
input         LateCollision;
input         StartDefer;
input         TxStartFrm;
input         StatePreamble;
input   [1:0] StateData;
input         CarrierSense;
input         TxUsedData;
input         Loopback;
input         r_FullD;
 
 
output        ReceivedLengthOK;
output        ReceiveEnd;
output        ReceivedPacketGood;
output        InvalidSymbol;
output        LatchedCrcError;
output        RxLateCollision;
output        ShortFrame;
output        DribbleNibble;
output        ReceivedPacketTooBig;
output        LoadRxStatus;
output  [3:0] RetryCntLatched;
output        RetryLimit;
output        LateCollLatched;
output        DeferLatched;
output        CarrierSenseLost;
output        LatchedMRxErr;
 
 
reg           ReceiveEnd;
 
reg           LatchedCrcError;
reg           LatchedMRxErr;
reg           LoadRxStatus;
reg           InvalidSymbol;
reg     [3:0] RetryCntLatched;
reg           RetryLimit;
reg           LateCollLatched;
reg           DeferLatched;
reg           CarrierSenseLost;
 
wire          TakeSample;
wire          SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps 
 
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedCrcError <=#Tp 1'b0;
  else
  if(RxStateSFD)
    LatchedCrcError <=#Tp 1'b0;
  else
  if(RxStateData[0])
    LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
end
 
 
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedMRxErr <=#Tp 1'b0;
  else
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
    LatchedMRxErr <=#Tp 1'b1;
  else
    LatchedMRxErr <=#Tp 1'b0;
end
 
 
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
 
 
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
 
 
 
 
 
// Time to take a sample
//assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
assign TakeSample = (|RxStateData)   & (~MRxDV)                    |
                      RxStateData[0] &   MRxDV & RxByteCntMaxFrame;
 
 
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LoadRxStatus <=#Tp 1'b0;
  else
    LoadRxStatus <=#Tp TakeSample;
end
 
 
 
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceiveEnd  <=#Tp 1'b0;
  else
    ReceiveEnd  <=#Tp LoadRxStatus;
end
 
 
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
 
 
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    InvalidSymbol <=#Tp 1'b0;
  else
  if(LoadRxStatus & ~SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b0;
  else
  if(SetInvalidSymbol)
    InvalidSymbol <=#Tp 1'b1;
end
 
 
// Late Collision
 
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxLateCollision <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    RxLateCollision <=#Tp 1'b0;
  else
  if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
    RxLateCollision <=#Tp 1'b1;
end
 
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxColWindow <=#Tp 1'b1;
  else
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
    RxColWindow <=#Tp 1'b0;
  else
  if(RxStateIdle)
    RxColWindow <=#Tp 1'b1;
end
 
 
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShortFrame <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    ShortFrame <=#Tp 1'b0;
  else
  if(TakeSample)
    ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
end
 
 
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    DribbleNibble <=#Tp 1'b0;
  else
  if(RxStateSFD)
    DribbleNibble <=#Tp 1'b0;
  else
  if(~MRxDV & RxStateData[1])
    DribbleNibble <=#Tp 1'b1;
end
 
 
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceivedPacketTooBig <=#Tp 1'b0;
  else
  if(LoadRxStatus)
    ReceivedPacketTooBig <=#Tp 1'b0;
  else
  if(TakeSample)
    ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
 
 
 
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryCntLatched <=#Tp 4'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryCntLatched <=#Tp RetryCnt;
end
 
 
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryLimit <=#Tp 4'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryLimit <=#Tp MaxCollisionOccured;
end
 
 
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    LateCollLatched <=#Tp 1'b0;
  else
  if(StartTxDone | StartTxAbort)
    LateCollLatched <=#Tp LateCollision;
end
 
 
 
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    DeferLatched <=#Tp 1'b0;
  else
  if(StartDefer & TxUsedData)
    DeferLatched <=#Tp 1'b1;
  else
  if(TxStartFrm)
    DeferLatched <=#Tp 1'b0;
end
 
 
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    CarrierSenseLost <=#Tp 1'b0;
  else
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
    CarrierSenseLost <=#Tp 1'b1;
  else
  if(TxStartFrm)
    CarrierSenseLost <=#Tp 1'b0;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_macstatus.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	37	mohor	`//// http://www.opencores.org/projects/ethmac/ ////`
7	15	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11	168	mohor	`//// All additional information is available in the Readme.txt ////`
12	15	mohor	`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16	168	mohor	`//// Copyright (C) 2001, 2002 Authors ////`
17	15	mohor	`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	242	tadejm	`// Revision 1.12 2002/09/12 14:50:16 mohor`
45			`// CarrierSenseLost bug fixed when operating in full duplex mode.`
46			`//`
47	168	mohor	`// Revision 1.11 2002/09/04 18:38:03 mohor`
48			`// CarrierSenseLost status is not set when working in loopback mode.`
49			`//`
50	146	mohor	`// Revision 1.10 2002/07/25 18:17:46 mohor`
51			`// InvalidSymbol generation changed.`
52			`//`
53	126	mohor	`// Revision 1.9 2002/04/22 13:51:44 mohor`
54			`// Short frame and ReceivedLengthOK were not detected correctly.`
55			`//`
56	101	mohor	`// Revision 1.8 2002/02/18 10:40:17 mohor`
57			`// Small fixes.`
58			`//`
59	70	mohor	`// Revision 1.7 2002/02/15 17:07:39 mohor`
60			`// Status was not written correctly when frames were discarted because of`
61			`// address mismatch.`
62			`//`
63	64	mohor	`// Revision 1.6 2002/02/11 09:18:21 mohor`
64			`// Tx status is written back to the BD.`
65			`//`
66	43	mohor	`// Revision 1.5 2002/02/08 16:21:54 mohor`
67			`// Rx status is written back to the BD.`
68			`//`
69	42	mohor	`// Revision 1.4 2002/01/23 10:28:16 mohor`
70			`// Link in the header changed.`
71			`//`
72	37	mohor	`// Revision 1.3 2001/10/19 08:43:51 mohor`
73			`// eth_timescale.v changed to timescale.v This is done because of the`
74			`// simulation of the few cores in a one joined project.`
75			`//`
76	22	mohor	`// Revision 1.2 2001/09/11 14:17:00 mohor`
77			`// Few little NCSIM warnings fixed.`
78			`//`
79	18	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
80			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
81			`// Include files fixed to contain no path.`
82			`// File names and module names changed ta have a eth_ prologue in the name.`
83			`// File eth_timescale.v is used to define timescale`
84			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
85			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
86			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
87			`// is done due to the ASIC tools.`
88			`//`
89	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
90			`// Directory structure changed. Files checked and joind together.`
91			`//`
92			`//`
93			`//`
94			`//`
95			`//`
96
97	22	mohor	`include "timescale.v"
98	15	mohor
99
100			`module eth_macstatus(`
101	42	mohor	`MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,`
102	15	mohor	`MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,`
103	42	mohor	`RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,`
104			`InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,`
105			`r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,`
106	43	mohor	`LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,`
107			`RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,`
108	168	mohor	`StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,`
109			`r_FullD`
110	15	mohor	`);`
111
112
113
114			`parameter Tp = 1;`
115
116
117			`input MRxClk;`
118			`input Reset;`
119			`input RxCrcError;`
120			`input MRxErr;`
121			`input MRxDV;`
122
123			`input RxStateSFD;`
124			`input [1:0] RxStateData;`
125			`input RxStatePreamble;`
126			`input RxStateIdle;`
127			`input Transmitting;`
128			`input [15:0] RxByteCnt;`
129			`input RxByteCntEq0;`
130			`input RxByteCntGreat2;`
131			`input RxByteCntMaxFrame;`
132			`input ReceivedPauseFrm;`
133	42	mohor	`input [3:0] MRxD;`
134			`input Collision;`
135			`input [5:0] CollValid;`
136			`input r_RecSmall;`
137			`input [15:0] r_MinFL;`
138			`input [15:0] r_MaxFL;`
139			`input r_HugEn;`
140	43	mohor	`input StartTxDone;`
141			`input StartTxAbort;`
142			`input [3:0] RetryCnt;`
143			`input MTxClk;`
144			`input MaxCollisionOccured;`
145			`input LateCollision;`
146			`input StartDefer;`
147			`input TxStartFrm;`
148			`input StatePreamble;`
149			`input [1:0] StateData;`
150			`input CarrierSense;`
151			`input TxUsedData;`
152	146	mohor	`input Loopback;`
153	168	mohor	`input r_FullD;`
154	15	mohor
155	43	mohor
156	15	mohor	`output ReceivedLengthOK;`
157			`output ReceiveEnd;`
158			`output ReceivedPacketGood;`
159	42	mohor	`output InvalidSymbol;`
160			`output LatchedCrcError;`
161			`output RxLateCollision;`
162			`output ShortFrame;`
163			`output DribbleNibble;`
164			`output ReceivedPacketTooBig;`
165			`output LoadRxStatus;`
166	43	mohor	`output [3:0] RetryCntLatched;`
167			`output RetryLimit;`
168			`output LateCollLatched;`
169			`output DeferLatched;`
170			`output CarrierSenseLost;`
171	126	mohor	`output LatchedMRxErr;`
172	15	mohor
173	43	mohor
174	15	mohor	`reg ReceiveEnd;`
175
176			`reg LatchedCrcError;`
177			`reg LatchedMRxErr;`
178	42	mohor	`reg LoadRxStatus;`
179			`reg InvalidSymbol;`
180	43	mohor	`reg [3:0] RetryCntLatched;`
181			`reg RetryLimit;`
182			`reg LateCollLatched;`
183			`reg DeferLatched;`
184			`reg CarrierSenseLost;`
185	15	mohor
186			`wire TakeSample;`
187	42	mohor	`wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps`
188	15	mohor
189			`// Crc error`
190			`always @ (posedge MRxClk or posedge Reset)`
191			`begin`
192			`if(Reset)`
193			`LatchedCrcError <=#Tp 1'b0;`
194			`else`
195	42	mohor	`if(RxStateSFD)`
196			`LatchedCrcError <=#Tp 1'b0;`
197			`else`
198			`if(RxStateData[0])`
199			`LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;`
200	15	mohor	`end`
201
202
203			`// LatchedMRxErr`
204			`always @ (posedge MRxClk or posedge Reset)`
205			`begin`
206			`if(Reset)`
207			`LatchedMRxErr <=#Tp 1'b0;`
208			`else`
209	18	mohor	`if(MRxErr & MRxDV & (RxStatePreamble \| RxStateSFD \| (\|RxStateData) \| RxStateIdle & ~Transmitting))`
210	15	mohor	`LatchedMRxErr <=#Tp 1'b1;`
211	126	mohor	`else`
212			`LatchedMRxErr <=#Tp 1'b0;`
213	15	mohor	`end`
214
215
216			`// ReceivedPacketGood`
217	126	mohor	`assign ReceivedPacketGood = ~LatchedCrcError;`
218	15	mohor
219
220			`// ReceivedLengthOK`
221	101	mohor	`assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];`
222	15	mohor
223
224
225	42	mohor
226
227			`// Time to take a sample`
228	242	tadejm	`//assign TakeSample = \|RxStateData & ~MRxDV & RxByteCntGreat2 \|`
229			`assign TakeSample = (\|RxStateData) & (~MRxDV) \|`
230			`RxStateData[0] & MRxDV & RxByteCntMaxFrame;`
231	42	mohor
232
233			`// LoadRxStatus`
234	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
235			`begin`
236			`if(Reset)`
237	42	mohor	`LoadRxStatus <=#Tp 1'b0;`
238	15	mohor	`else`
239	42	mohor	`LoadRxStatus <=#Tp TakeSample;`
240	15	mohor	`end`
241
242
243
244	42	mohor	`// ReceiveEnd`
245			`always @ (posedge MRxClk or posedge Reset)`
246			`begin`
247			`if(Reset)`
248			`ReceiveEnd <=#Tp 1'b0;`
249			`else`
250			`ReceiveEnd <=#Tp LoadRxStatus;`
251			`end`
252	15	mohor
253
254	42	mohor	`// Invalid Symbol received during 100Mbps mode`
255	126	mohor	`assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;`
256	42	mohor
257
258			`// InvalidSymbol`
259	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
260			`begin`
261			`if(Reset)`
262	42	mohor	`InvalidSymbol <=#Tp 1'b0;`
263	15	mohor	`else`
264	42	mohor	`if(LoadRxStatus & ~SetInvalidSymbol)`
265			`InvalidSymbol <=#Tp 1'b0;`
266			`else`
267			`if(SetInvalidSymbol)`
268			`InvalidSymbol <=#Tp 1'b1;`
269	15	mohor	`end`
270
271
272	42	mohor	`// Late Collision`
273	15	mohor
274	42	mohor	`reg RxLateCollision;`
275			`reg RxColWindow;`
276			`// Collision Window`
277	15	mohor	`always @ (posedge MRxClk or posedge Reset)`
278			`begin`
279			`if(Reset)`
280	42	mohor	`RxLateCollision <=#Tp 1'b0;`
281	15	mohor	`else`
282	42	mohor	`if(LoadRxStatus)`
283			`RxLateCollision <=#Tp 1'b0;`
284			`else`
285	242	tadejm	`if(Collision & (~r_FullD) & (~RxColWindow \| r_RecSmall))`
286	42	mohor	`RxLateCollision <=#Tp 1'b1;`
287	15	mohor	`end`
288
289	42	mohor	`// Collision Window`
290			`always @ (posedge MRxClk or posedge Reset)`
291			`begin`
292			`if(Reset)`
293			`RxColWindow <=#Tp 1'b1;`
294			`else`
295			`if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])`
296			`RxColWindow <=#Tp 1'b0;`
297			`else`
298			`if(RxStateIdle)`
299			`RxColWindow <=#Tp 1'b1;`
300			`end`
301	15	mohor
302	42	mohor
303			`// ShortFrame`
304			`reg ShortFrame;`
305			`always @ (posedge MRxClk or posedge Reset)`
306			`begin`
307			`if(Reset)`
308			`ShortFrame <=#Tp 1'b0;`
309			`else`
310			`if(LoadRxStatus)`
311			`ShortFrame <=#Tp 1'b0;`
312			`else`
313			`if(TakeSample)`
314	101	mohor	`ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];`
315	42	mohor	`end`
316
317
318			`// DribbleNibble`
319			`reg DribbleNibble;`
320			`always @ (posedge MRxClk or posedge Reset)`
321			`begin`
322			`if(Reset)`
323			`DribbleNibble <=#Tp 1'b0;`
324			`else`
325			`if(RxStateSFD)`
326			`DribbleNibble <=#Tp 1'b0;`
327			`else`
328			`if(~MRxDV & RxStateData[1])`
329			`DribbleNibble <=#Tp 1'b1;`
330			`end`
331
332
333			`reg ReceivedPacketTooBig;`
334			`always @ (posedge MRxClk or posedge Reset)`
335			`begin`
336			`if(Reset)`
337			`ReceivedPacketTooBig <=#Tp 1'b0;`
338			`else`
339			`if(LoadRxStatus)`
340			`ReceivedPacketTooBig <=#Tp 1'b0;`
341			`else`
342			`if(TakeSample)`
343			`ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];`
344			`end`
345
346	43	mohor
347
348			`// Latched Retry counter for tx status`
349			`always @ (posedge MTxClk or posedge Reset)`
350			`begin`
351			`if(Reset)`
352			`RetryCntLatched <=#Tp 4'h0;`
353			`else`
354			`if(StartTxDone \| StartTxAbort)`
355			`RetryCntLatched <=#Tp RetryCnt;`
356			`end`
357
358
359			`// Latched Retransmission limit`
360			`always @ (posedge MTxClk or posedge Reset)`
361			`begin`
362			`if(Reset)`
363			`RetryLimit <=#Tp 4'h0;`
364			`else`
365			`if(StartTxDone \| StartTxAbort)`
366			`RetryLimit <=#Tp MaxCollisionOccured;`
367			`end`
368
369
370			`// Latched Late Collision`
371			`always @ (posedge MTxClk or posedge Reset)`
372			`begin`
373			`if(Reset)`
374			`LateCollLatched <=#Tp 1'b0;`
375			`else`
376			`if(StartTxDone \| StartTxAbort)`
377			`LateCollLatched <=#Tp LateCollision;`
378			`end`
379
380
381
382			`// Latched Defer state`
383			`always @ (posedge MTxClk or posedge Reset)`
384			`begin`
385			`if(Reset)`
386			`DeferLatched <=#Tp 1'b0;`
387			`else`
388			`if(StartDefer & TxUsedData)`
389			`DeferLatched <=#Tp 1'b1;`
390			`else`
391			`if(TxStartFrm)`
392			`DeferLatched <=#Tp 1'b0;`
393			`end`
394
395
396			`// CarrierSenseLost`
397			`always @ (posedge MTxClk or posedge Reset)`
398			`begin`
399			`if(Reset)`
400			`CarrierSenseLost <=#Tp 1'b0;`
401			`else`
402	168	mohor	`if((StatePreamble \| (\|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)`
403	43	mohor	`CarrierSenseLost <=#Tp 1'b1;`
404			`else`
405			`if(TxStartFrm)`
406			`CarrierSenseLost <=#Tp 1'b0;`
407			`end`
408
409
410	15	mohor	`endmodule`

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