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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 139

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
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////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
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//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
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////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
45
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
46
//
47 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
48
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
49
// or not.
50
//
51 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
52
// Reset values are passed to registers through parameters
53
//
54 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
55
// Define missmatch fixed.
56
//
57 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
58
// Registered trimmed. Unused registers removed.
59
//
60 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
61
// File format fixed a bit.
62
//
63 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
64
// Modified for Address Checking,
65
// addition of eth_addrcheck.v
66
//
67
// Revision 1.8  2002/02/12 17:01:19  mohor
68
// HASH0 and HASH1 registers added. 
69
 
70 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
71
// Link in the header changed.
72
//
73 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
74
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
75
// instead of the number of RX descriptors).
76
//
77 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
78
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
79
//
80 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
81
// eth_timescale.v changed to timescale.v This is done because of the
82
// simulation of the few cores in a one joined project.
83
//
84 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
85
// Status signals changed, Adress decoding changed, interrupt controller
86
// added.
87
//
88 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
89
// Defines changed (All precede with ETH_). Small changes because some
90
// tools generate warnings when two operands are together. Synchronization
91
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
92
// demands).
93
//
94 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
95
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
96
// Include files fixed to contain no path.
97
// File names and module names changed ta have a eth_ prologue in the name.
98
// File eth_timescale.v is used to define timescale
99
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
100
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
101
// and Mdo_OE. The bidirectional signal must be created on the top level. This
102
// is done due to the ASIC tools.
103
//
104 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
105
// Unconnected signals are now connected.
106
//
107
// Revision 1.1  2001/07/30 21:23:42  mohor
108
// Directory structure changed. Files checked and joind together.
109
//
110
//
111
//
112
//
113
//
114
//
115
 
116
`include "eth_defines.v"
117 22 mohor
`include "timescale.v"
118 15 mohor
 
119
 
120 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
121 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
122
                      r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
123 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
124 74 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
125 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
126 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
127
                      r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
128
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
129
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
130 46 mohor
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
131 56 mohor
                      r_HASH0, r_HASH1
132 15 mohor
                    );
133
 
134
parameter Tp = 1;
135
 
136
input [31:0] DataIn;
137 46 mohor
input [7:0] Address;
138 15 mohor
 
139
input Rw;
140
input Cs;
141
input Clk;
142
input Reset;
143
 
144
input WCtrlDataStart;
145
input RStatStart;
146
 
147
input UpdateMIIRX_DATAReg;
148
input [15:0] Prsd;
149
 
150
output [31:0] DataOut;
151
reg    [31:0] DataOut;
152
 
153
output r_RecSmall;
154
output r_Pad;
155
output r_HugEn;
156
output r_CrcEn;
157
output r_DlyCrcEn;
158
output r_Rst;
159
output r_FullD;
160
output r_ExDfrEn;
161
output r_NoBckof;
162
output r_LoopBck;
163
output r_IFG;
164
output r_Pro;
165
output r_Iam;
166
output r_Bro;
167
output r_NoPre;
168
output r_TxEn;
169
output r_RxEn;
170 52 billditt
output [31:0] r_HASH0;
171
output [31:0] r_HASH1;
172 15 mohor
 
173 21 mohor
input TxB_IRQ;
174
input TxE_IRQ;
175
input RxB_IRQ;
176 74 mohor
input RxE_IRQ;
177 21 mohor
input Busy_IRQ;
178 74 mohor
input TxC_IRQ;
179
input RxC_IRQ;
180 15 mohor
 
181
output [6:0] r_IPGT;
182
 
183
output [6:0] r_IPGR1;
184
 
185
output [6:0] r_IPGR2;
186
 
187
output [15:0] r_MinFL;
188
output [15:0] r_MaxFL;
189
 
190
output [3:0] r_MaxRet;
191
output [5:0] r_CollValid;
192
 
193
output r_TxFlow;
194
output r_RxFlow;
195
output r_PassAll;
196
 
197
output r_MiiMRst;
198
output r_MiiNoPre;
199
output [7:0] r_ClkDiv;
200
 
201
output r_WCtrlData;
202
output r_RStat;
203
output r_ScanStat;
204
 
205
output [4:0] r_RGAD;
206
output [4:0] r_FIAD;
207
 
208 21 mohor
output [15:0]r_CtrlData;
209 15 mohor
 
210
 
211
input NValid_stat;
212
input Busy_stat;
213
input LinkFail;
214
 
215 21 mohor
output [47:0]r_MAC;
216 34 mohor
output [7:0] r_TxBDNum;
217
output       TX_BD_NUM_Wr;
218 21 mohor
output       int_o;
219 15 mohor
 
220 21 mohor
reg          irq_txb;
221
reg          irq_txe;
222
reg          irq_rxb;
223 74 mohor
reg          irq_rxe;
224 21 mohor
reg          irq_busy;
225 74 mohor
reg          irq_txc;
226
reg          irq_rxc;
227 15 mohor
 
228
wire Write = Cs &  Rw;
229
wire Read  = Cs & ~Rw;
230
 
231 21 mohor
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
232
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  )  & Write;
233
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    )  & Write;
234
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        )  & Write;
235
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       )  & Write;
236
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       )  & Write;
237
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   )  & Write;
238
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    )  & Write;
239
 
240
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   )  & Write;
241
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    )  & Write;
242
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  )  & Write;
243
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  )  & Write;
244
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  )  & Write;
245
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
246
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   )  & Write;
247
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   )  & Write;
248 52 billditt
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR   )  & Write;
249
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR   )  & Write;
250 34 mohor
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   )  & Write;
251 15 mohor
 
252
 
253
 
254
wire [31:0] MODEROut;
255
wire [31:0] INT_SOURCEOut;
256
wire [31:0] INT_MASKOut;
257
wire [31:0] IPGTOut;
258
wire [31:0] IPGR1Out;
259
wire [31:0] IPGR2Out;
260
wire [31:0] PACKETLENOut;
261
wire [31:0] COLLCONFOut;
262
wire [31:0] CTRLMODEROut;
263
wire [31:0] MIIMODEROut;
264
wire [31:0] MIICOMMANDOut;
265
wire [31:0] MIIADDRESSOut;
266
wire [31:0] MIITX_DATAOut;
267
wire [31:0] MIIRX_DATAOut;
268
wire [31:0] MIISTATUSOut;
269
wire [31:0] MAC_ADDR0Out;
270
wire [31:0] MAC_ADDR1Out;
271 34 mohor
wire [31:0] TX_BD_NUMOut;
272 52 billditt
wire [31:0] HASH0Out;
273
wire [31:0] HASH1Out;
274 15 mohor
 
275 46 mohor
 
276 139 mohor
// MODER Register
277
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF)        MODER
278
  (
279
   .DataIn    (DataIn[`ETH_MODER_WIDTH-1:0]),
280
   .DataOut   (MODEROut[`ETH_MODER_WIDTH-1:0]),
281
   .Write     (MODER_Wr),
282
   .Clk       (Clk),
283
   .Reset     (Reset),
284
   .SyncReset (0)
285
  );
286
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
287 15 mohor
 
288 139 mohor
// INT_MASK Register
289
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF)  INT_MASK
290
  (
291
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
292
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
293
   .Write     (INT_MASK_Wr),
294
   .Clk       (Clk),
295
   .Reset     (Reset),
296
   .SyncReset (0)
297
  );
298
assign INT_MASKOut[31:ETH_INT_MASK_WIDTH] = 0;
299 52 billditt
 
300 139 mohor
// IPGT Register
301
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF)          IPGT
302
  (
303
   .DataIn    (DataIn[`ETH_IPGT_WIDTH-1:0]),
304
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
305
   .Write     (IPGT_Wr),
306
   .Clk       (Clk),
307
   .Reset     (Reset),
308
   .SyncReset (0)
309
  );
310
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
311 52 billditt
 
312 139 mohor
// IPGR1 Register
313
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF)        IPGR1
314
  (
315
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH-1:0]),
316
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
317
   .Write     (IPGR1_Wr),
318
   .Clk       (Clk),
319
   .Reset     (Reset),
320
   .SyncReset (0)
321
  );
322
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
323 15 mohor
 
324 139 mohor
// IPGR2 Register
325
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF)        IPGR2
326
  (
327
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH-1:0]),
328
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
329
   .Write     (IPGR2_Wr),
330
   .Clk       (Clk),
331
   .Reset     (Reset),
332
   .SyncReset (0)
333
  );
334
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
335 15 mohor
 
336 139 mohor
// PACKETLEN Register
337
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
338
  (
339
   .DataIn    (DataIn),
340
   .DataOut   (PACKETLENOut),
341
   .Write     (PACKETLEN_Wr),
342
   .Clk       (Clk),
343
   .Reset     (Reset),
344
   .SyncReset (0)
345
  );
346 15 mohor
 
347 139 mohor
// COLLCONF Register
348
eth_register #(6, `ETH_COLLCONF0_DEF)                   COLLCONF0
349
  (
350
   .DataIn    (DataIn[5:0]),
351
   .DataOut   (COLLCONFOut[5:0]),
352
   .Write     (COLLCONF_Wr),
353
   .Clk       (Clk),
354
   .Reset     (Reset),
355
   .SyncReset (0)
356
  );
357 68 mohor
assign COLLCONFOut[15:6] = 0;
358 139 mohor
 
359
eth_register #(4, `ETH_COLLCONF1_DEF)                   COLLCONF1
360
  (
361
   .DataIn    (DataIn[19:16]),
362
   .DataOut   (COLLCONFOut[19:16]),
363
   .Write     (COLLCONF_Wr),
364
   .Clk       (Clk),
365
   .Reset     (Reset),
366
   .SyncReset (0)
367
  );
368 68 mohor
assign COLLCONFOut[31:20] = 0;
369 15 mohor
 
370 139 mohor
// TX_BD_NUM Register
371
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
372
  (
373
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
374
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
375
   .Write     (TX_BD_NUM_Wr),
376
   .Clk       (Clk),
377
   .Reset     (Reset),
378
   .SyncReset (0)
379
  );
380
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
381 15 mohor
 
382 139 mohor
// CTRLMODER Register
383
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF)  CTRLMODER2
384
  (
385
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
386
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
387
   .Write     (CTRLMODER_Wr),
388
   .Clk       (Clk),
389
   .Reset     (Reset),
390
   .SyncReset (0)
391
  );
392
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
393 15 mohor
 
394 139 mohor
// MIIMODER Register
395
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF)    MIIMODER
396
  (
397
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
398
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
399
   .Write     (MIIMODER_Wr),
400
   .Clk       (Clk),
401
   .Reset     (Reset),
402
   .SyncReset (0)
403
  );
404
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
405 68 mohor
 
406 139 mohor
// MIICOMMAND Register
407
eth_register #(1, 0)                                      MIICOMMAND0
408
  (
409
   .DataIn    (DataIn[0]),
410
   .DataOut   (MIICOMMANDOut[0]),
411
   .Write     (MIICOMMAND_Wr),
412
   .Clk       (Clk),
413
   .Reset     (Reset),
414
   .SyncReset (0)
415
  );
416
 
417
eth_register #(1, 0)                                      MIICOMMAND1
418
  (
419
   .DataIn    (DataIn[1]),
420
   .DataOut   (MIICOMMANDOut[1]),
421
   .Write     (MIICOMMAND_Wr),
422
   .Clk       (Clk),
423
   .Reset     (Reset),
424
   .SyncReset (RStatStart)
425
  );
426
 
427
eth_register #(1, 0)                                      MIICOMMAND2
428
  (
429
   .DataIn    (DataIn[2]),
430
   .DataOut   (MIICOMMANDOut[2]),
431
   .Write     (MIICOMMAND_Wr),
432
   .Clk       (Clk),
433
   .Reset     (Reset),
434
   .SyncReset (WCtrlDataStart)
435
  );
436 15 mohor
assign MIICOMMANDOut[31:3] = 29'h0;
437
 
438 139 mohor
// MIIADDRESSRegister
439
eth_register #(5, `ETH_MIIADDRESS0_DEF)                   MIIADDRESS0
440
  (
441
   .DataIn    (DataIn[4:0]),
442
   .DataOut   (MIIADDRESSOut[4:0]),
443
   .Write     (MIIADDRESS_Wr),
444
   .Clk       (Clk),
445
   .Reset     (Reset),
446
   .SyncReset (0)
447
  );
448 68 mohor
assign MIIADDRESSOut[7:5] = 0;
449 139 mohor
 
450
eth_register #(5, `ETH_MIIADDRESS1_DEF)                   MIIADDRESS1
451
  (
452
   .DataIn    (DataIn[12:8]),
453
   .DataOut   (MIIADDRESSOut[12:8]),
454
   .Write     (MIIADDRESS_Wr),
455
   .Clk       (Clk),
456
   .Reset     (Reset),
457
   .SyncReset (0)
458
  );
459 68 mohor
assign MIIADDRESSOut[31:13] = 0;
460 15 mohor
 
461 139 mohor
// MIITX_DATA Register
462
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
463
  (
464
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
465
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0])
466
   .Write     (MIITX_DATA_Wr),
467
   .Clk       (Clk),
468
   .Reset     (Reset),
469
   .SyncReset (0)
470
  );
471
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
472 15 mohor
 
473 139 mohor
// MIIRX_DATA Register
474
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
475
  (
476
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
477
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
478
   .Write     (MIIRX_DATA_Wr),
479
   .Clk       (Clk),
480
   .Reset     (Reset),
481
   .SyncReset (0)
482
  );
483
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
484 15 mohor
 
485 139 mohor
// MAC_ADDR0 Register
486
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF)  MAC_ADDR0
487
  (
488
   .DataIn    (DataIn),
489
   .DataOut   (MAC_ADDR0Out),
490
   .Write     (MAC_ADDR0_Wr),
491
   .Clk       (Clk),
492
   .Reset     (Reset),
493
   .SyncReset (0)
494
  );
495 68 mohor
 
496 139 mohor
// MAC_ADDR1 Register
497
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF)  MAC_ADDR1
498
  (
499
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
500
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
501
   .Write     (MAC_ADDR1_Wr),
502
   .Clk       (Clk),
503
   .Reset     (Reset),
504
   .SyncReset (0)
505
  );
506
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
507 68 mohor
 
508 139 mohor
// RXHASH0 Register
509
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF)          RXHASH0
510
  (
511
   .DataIn    (DataIn),
512
   .DataOut   (HASH0Out),
513
   .Write     (HASH0_Wr),
514
   .Clk       (Clk),
515
   .Reset     (Reset),
516
   .SyncReset (0)
517
  );
518 68 mohor
 
519 139 mohor
// RXHASH1 Register
520
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF)          RXHASH1
521
  (
522
   .DataIn    (DataIn),
523
   .DataOut   (HASH1Out),
524
   .Write     (HASH1_Wr),
525
   .Clk       (Clk),
526
   .Reset     (Reset),
527
   .SyncReset (0)
528
  );
529 68 mohor
 
530 15 mohor
 
531 139 mohor
// Reading data from registers
532
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
533
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
534
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
535
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
536
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
537
          HASH0Out      or HASH1Out
538
         )
539 15 mohor
begin
540
  if(Read)  // read
541
    begin
542
      case(Address)
543 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
544
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
545
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
546
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
547
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
548
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
549
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
550
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
551
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
552
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
553
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
554
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
555
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
556
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
557
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
558
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
559
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
560 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
561 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
562
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
563 15 mohor
        default:             DataOut<=32'h0;
564
      endcase
565
    end
566
  else
567
    DataOut<=32'h0;
568
end
569
 
570
 
571
assign r_RecSmall         = MODEROut[16];
572
assign r_Pad              = MODEROut[15];
573
assign r_HugEn            = MODEROut[14];
574
assign r_CrcEn            = MODEROut[13];
575
assign r_DlyCrcEn         = MODEROut[12];
576
assign r_Rst              = MODEROut[11];
577
assign r_FullD            = MODEROut[10];
578
assign r_ExDfrEn          = MODEROut[9];
579
assign r_NoBckof          = MODEROut[8];
580
assign r_LoopBck          = MODEROut[7];
581
assign r_IFG              = MODEROut[6];
582
assign r_Pro              = MODEROut[5];
583
assign r_Iam              = MODEROut[4];
584
assign r_Bro              = MODEROut[3];
585
assign r_NoPre            = MODEROut[2];
586
assign r_TxEn             = MODEROut[1];
587
assign r_RxEn             = MODEROut[0];
588
 
589
assign r_IPGT[6:0]        = IPGTOut[6:0];
590
 
591
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
592
 
593
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
594
 
595
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
596
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
597
 
598 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
599
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
600 15 mohor
 
601
assign r_TxFlow           = CTRLMODEROut[2];
602
assign r_RxFlow           = CTRLMODEROut[1];
603
assign r_PassAll          = CTRLMODEROut[0];
604
 
605 139 mohor
assign r_MiiMRst          = MIIMODEROut[9];
606 15 mohor
assign r_MiiNoPre         = MIIMODEROut[8];
607
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
608
 
609
assign r_WCtrlData        = MIICOMMANDOut[2];
610
assign r_RStat            = MIICOMMANDOut[1];
611
assign r_ScanStat         = MIICOMMANDOut[0];
612
 
613
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
614
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
615
 
616
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
617
 
618 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
619
assign MIISTATUSOut[2]    = NValid_stat         ;
620
assign MIISTATUSOut[1]    = Busy_stat           ;
621
assign MIISTATUSOut[0]    = LinkFail            ;
622 15 mohor
 
623
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
624
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
625 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
626
assign r_HASH0[31:0]      = HASH0Out;
627 15 mohor
 
628 34 mohor
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
629 15 mohor
 
630
 
631 21 mohor
// Interrupt generation
632
always @ (posedge Clk or posedge Reset)
633
begin
634
  if(Reset)
635
    irq_txb <= 1'b0;
636
  else
637 102 mohor
  if(TxB_IRQ)
638 21 mohor
    irq_txb <= #Tp 1'b1;
639
  else
640
  if(INT_SOURCE_Wr & DataIn[0])
641
    irq_txb <= #Tp 1'b0;
642
end
643
 
644
always @ (posedge Clk or posedge Reset)
645
begin
646
  if(Reset)
647
    irq_txe <= 1'b0;
648
  else
649 102 mohor
  if(TxE_IRQ)
650 21 mohor
    irq_txe <= #Tp 1'b1;
651
  else
652
  if(INT_SOURCE_Wr & DataIn[1])
653
    irq_txe <= #Tp 1'b0;
654
end
655
 
656
always @ (posedge Clk or posedge Reset)
657
begin
658
  if(Reset)
659
    irq_rxb <= 1'b0;
660
  else
661 102 mohor
  if(RxB_IRQ)
662 21 mohor
    irq_rxb <= #Tp 1'b1;
663
  else
664
  if(INT_SOURCE_Wr & DataIn[2])
665
    irq_rxb <= #Tp 1'b0;
666
end
667
 
668
always @ (posedge Clk or posedge Reset)
669
begin
670
  if(Reset)
671 74 mohor
    irq_rxe <= 1'b0;
672 21 mohor
  else
673 102 mohor
  if(RxE_IRQ)
674 74 mohor
    irq_rxe <= #Tp 1'b1;
675 21 mohor
  else
676
  if(INT_SOURCE_Wr & DataIn[3])
677 74 mohor
    irq_rxe <= #Tp 1'b0;
678 21 mohor
end
679
 
680
always @ (posedge Clk or posedge Reset)
681
begin
682
  if(Reset)
683
    irq_busy <= 1'b0;
684
  else
685 102 mohor
  if(Busy_IRQ)
686 21 mohor
    irq_busy <= #Tp 1'b1;
687
  else
688
  if(INT_SOURCE_Wr & DataIn[4])
689
    irq_busy <= #Tp 1'b0;
690
end
691
 
692 74 mohor
always @ (posedge Clk or posedge Reset)
693
begin
694
  if(Reset)
695
    irq_txc <= 1'b0;
696
  else
697 102 mohor
  if(TxC_IRQ)
698 74 mohor
    irq_txc <= #Tp 1'b1;
699
  else
700
  if(INT_SOURCE_Wr & DataIn[5])
701
    irq_txc <= #Tp 1'b0;
702
end
703
 
704
always @ (posedge Clk or posedge Reset)
705
begin
706
  if(Reset)
707
    irq_rxc <= 1'b0;
708
  else
709 102 mohor
  if(RxC_IRQ)
710 74 mohor
    irq_rxc <= #Tp 1'b1;
711
  else
712
  if(INT_SOURCE_Wr & DataIn[6])
713
    irq_rxc <= #Tp 1'b0;
714
end
715
 
716 21 mohor
// Generating interrupt signal
717 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
718
               irq_txe  & INT_MASKOut[1] |
719
               irq_rxb  & INT_MASKOut[2] |
720
               irq_rxe  & INT_MASKOut[3] |
721
               irq_busy & INT_MASKOut[4] |
722
               irq_txc  & INT_MASKOut[5] |
723
               irq_rxc  & INT_MASKOut[6] ;
724 21 mohor
 
725
// For reading interrupt status
726 139 mohor
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
727 21 mohor
 
728
 
729
 
730 15 mohor
endmodule

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