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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Blame information for rev 147

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_registers.v                                             ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 147 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 147 mohor
// Revision 1.19  2002/08/19 16:01:40  mohor
45
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
46
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
47
//
48 143 mohor
// Revision 1.18  2002/08/16 22:28:23  mohor
49
// Syntax error fixed.
50
//
51 141 mohor
// Revision 1.17  2002/08/16 22:23:03  mohor
52
// Syntax error fixed.
53
//
54 140 mohor
// Revision 1.16  2002/08/16 22:14:22  mohor
55
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
56
// changed from bit position 10 to 9.
57
//
58 139 mohor
// Revision 1.15  2002/08/14 18:26:37  mohor
59
// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
60
//
61 132 mohor
// Revision 1.14  2002/04/22 14:03:44  mohor
62
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
63
// or not.
64
//
65 102 mohor
// Revision 1.13  2002/02/26 16:18:09  mohor
66
// Reset values are passed to registers through parameters
67
//
68 74 mohor
// Revision 1.12  2002/02/17 13:23:42  mohor
69
// Define missmatch fixed.
70
//
71 69 mohor
// Revision 1.11  2002/02/16 14:03:44  mohor
72
// Registered trimmed. Unused registers removed.
73
//
74 68 mohor
// Revision 1.10  2002/02/15 11:08:25  mohor
75
// File format fixed a bit.
76
//
77 56 mohor
// Revision 1.9  2002/02/14 20:19:41  billditt
78
// Modified for Address Checking,
79
// addition of eth_addrcheck.v
80
//
81
// Revision 1.8  2002/02/12 17:01:19  mohor
82
// HASH0 and HASH1 registers added. 
83
 
84 46 mohor
// Revision 1.7  2002/01/23 10:28:16  mohor
85
// Link in the header changed.
86
//
87 37 mohor
// Revision 1.6  2001/12/05 15:00:16  mohor
88
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
89
// instead of the number of RX descriptors).
90
//
91 34 mohor
// Revision 1.5  2001/12/05 10:22:19  mohor
92
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
93
//
94 32 mohor
// Revision 1.4  2001/10/19 08:43:51  mohor
95
// eth_timescale.v changed to timescale.v This is done because of the
96
// simulation of the few cores in a one joined project.
97
//
98 22 mohor
// Revision 1.3  2001/10/18 12:07:11  mohor
99
// Status signals changed, Adress decoding changed, interrupt controller
100
// added.
101
//
102 21 mohor
// Revision 1.2  2001/09/24 15:02:56  mohor
103
// Defines changed (All precede with ETH_). Small changes because some
104
// tools generate warnings when two operands are together. Synchronization
105
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
106
// demands).
107
//
108 20 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
109
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
110
// Include files fixed to contain no path.
111
// File names and module names changed ta have a eth_ prologue in the name.
112
// File eth_timescale.v is used to define timescale
113
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
114
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
115
// and Mdo_OE. The bidirectional signal must be created on the top level. This
116
// is done due to the ASIC tools.
117
//
118 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
119
// Unconnected signals are now connected.
120
//
121
// Revision 1.1  2001/07/30 21:23:42  mohor
122
// Directory structure changed. Files checked and joind together.
123
//
124
//
125
//
126
//
127
//
128
//
129
 
130
`include "eth_defines.v"
131 22 mohor
`include "timescale.v"
132 15 mohor
 
133
 
134 68 mohor
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
135 15 mohor
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
136
                      r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
137 21 mohor
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
138 147 mohor
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
139 21 mohor
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
140 15 mohor
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
141
                      r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
142
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
143
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
144 46 mohor
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
145 147 mohor
                      r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
146
                      StartTxDone, TxClk, RxClk, ReceivedPauseFrm,
147
                      reg1, reg2, reg3, reg4
148 15 mohor
                    );
149
 
150
parameter Tp = 1;
151
 
152 147 mohor
input [31:0] reg1, reg2, reg3, reg4;
153
 
154 15 mohor
input [31:0] DataIn;
155 46 mohor
input [7:0] Address;
156 15 mohor
 
157
input Rw;
158
input Cs;
159
input Clk;
160
input Reset;
161
 
162
input WCtrlDataStart;
163
input RStatStart;
164
 
165
input UpdateMIIRX_DATAReg;
166
input [15:0] Prsd;
167
 
168
output [31:0] DataOut;
169
reg    [31:0] DataOut;
170
 
171
output r_RecSmall;
172
output r_Pad;
173
output r_HugEn;
174
output r_CrcEn;
175
output r_DlyCrcEn;
176
output r_Rst;
177
output r_FullD;
178
output r_ExDfrEn;
179
output r_NoBckof;
180
output r_LoopBck;
181
output r_IFG;
182
output r_Pro;
183
output r_Iam;
184
output r_Bro;
185
output r_NoPre;
186
output r_TxEn;
187
output r_RxEn;
188 52 billditt
output [31:0] r_HASH0;
189
output [31:0] r_HASH1;
190 15 mohor
 
191 21 mohor
input TxB_IRQ;
192
input TxE_IRQ;
193
input RxB_IRQ;
194 74 mohor
input RxE_IRQ;
195 21 mohor
input Busy_IRQ;
196 15 mohor
 
197
output [6:0] r_IPGT;
198
 
199
output [6:0] r_IPGR1;
200
 
201
output [6:0] r_IPGR2;
202
 
203
output [15:0] r_MinFL;
204
output [15:0] r_MaxFL;
205
 
206
output [3:0] r_MaxRet;
207
output [5:0] r_CollValid;
208
 
209
output r_TxFlow;
210
output r_RxFlow;
211
output r_PassAll;
212
 
213
output r_MiiMRst;
214
output r_MiiNoPre;
215
output [7:0] r_ClkDiv;
216
 
217
output r_WCtrlData;
218
output r_RStat;
219
output r_ScanStat;
220
 
221
output [4:0] r_RGAD;
222
output [4:0] r_FIAD;
223
 
224 21 mohor
output [15:0]r_CtrlData;
225 15 mohor
 
226
 
227
input NValid_stat;
228
input Busy_stat;
229
input LinkFail;
230
 
231 21 mohor
output [47:0]r_MAC;
232 34 mohor
output [7:0] r_TxBDNum;
233
output       TX_BD_NUM_Wr;
234 21 mohor
output       int_o;
235 147 mohor
output [15:0]r_TxPauseTV;
236
output       r_TxPauseRq;
237
input        RstTxPauseRq;
238
input        TxCtrlEndFrm;
239
input        StartTxDone;
240
input        TxClk;
241
input        RxClk;
242
input        ReceivedPauseFrm;      // sinhroniziraj tale shit da bo delal interrupt. Pazi na PassAll bit
243 15 mohor
 
244 21 mohor
reg          irq_txb;
245
reg          irq_txe;
246
reg          irq_rxb;
247 74 mohor
reg          irq_rxe;
248 21 mohor
reg          irq_busy;
249 74 mohor
reg          irq_txc;
250
reg          irq_rxc;
251 15 mohor
 
252 147 mohor
reg SetTxCIrq_txclk;
253
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
254
reg SetTxCIrq;
255
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
256
 
257
reg SetRxCIrq_rxclk;
258
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
259
reg SetRxCIrq;
260
reg ResetRxCIrq_sync1, ResetRxCIrq_sync2;
261
 
262 15 mohor
wire Write = Cs &  Rw;
263
wire Read  = Cs & ~Rw;
264
 
265 21 mohor
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
266
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  )  & Write;
267
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    )  & Write;
268
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        )  & Write;
269
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       )  & Write;
270
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       )  & Write;
271
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   )  & Write;
272
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    )  & Write;
273
 
274
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   )  & Write;
275
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    )  & Write;
276
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  )  & Write;
277
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  )  & Write;
278
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  )  & Write;
279
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
280
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   )  & Write;
281
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   )  & Write;
282 147 mohor
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR       )  & Write;
283
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR       )  & Write;
284
wire TXCTRL_Wr      = (Address == `ETH_TX_CTRL_ADR     )  & Write;
285
wire RXCTRL_Wr      = (Address == `ETH_RX_CTRL_ADR     )  & Write;
286 34 mohor
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   )  & Write;
287 15 mohor
 
288
 
289
 
290
wire [31:0] MODEROut;
291
wire [31:0] INT_SOURCEOut;
292
wire [31:0] INT_MASKOut;
293
wire [31:0] IPGTOut;
294
wire [31:0] IPGR1Out;
295
wire [31:0] IPGR2Out;
296
wire [31:0] PACKETLENOut;
297
wire [31:0] COLLCONFOut;
298
wire [31:0] CTRLMODEROut;
299
wire [31:0] MIIMODEROut;
300
wire [31:0] MIICOMMANDOut;
301
wire [31:0] MIIADDRESSOut;
302
wire [31:0] MIITX_DATAOut;
303
wire [31:0] MIIRX_DATAOut;
304
wire [31:0] MIISTATUSOut;
305
wire [31:0] MAC_ADDR0Out;
306
wire [31:0] MAC_ADDR1Out;
307 34 mohor
wire [31:0] TX_BD_NUMOut;
308 52 billditt
wire [31:0] HASH0Out;
309
wire [31:0] HASH1Out;
310 147 mohor
wire [31:0] TXCTRLOut;
311
wire [31:0] RXCTRLOut;
312 15 mohor
 
313 46 mohor
 
314 139 mohor
// MODER Register
315
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF)        MODER
316
  (
317
   .DataIn    (DataIn[`ETH_MODER_WIDTH-1:0]),
318
   .DataOut   (MODEROut[`ETH_MODER_WIDTH-1:0]),
319
   .Write     (MODER_Wr),
320
   .Clk       (Clk),
321
   .Reset     (Reset),
322 141 mohor
   .SyncReset (1'b0)
323 139 mohor
  );
324
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
325 15 mohor
 
326 139 mohor
// INT_MASK Register
327
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF)  INT_MASK
328
  (
329
   .DataIn    (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
330
   .DataOut   (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
331
   .Write     (INT_MASK_Wr),
332
   .Clk       (Clk),
333
   .Reset     (Reset),
334 141 mohor
   .SyncReset (1'b0)
335 139 mohor
  );
336 141 mohor
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH] = 0;
337 52 billditt
 
338 139 mohor
// IPGT Register
339
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF)          IPGT
340
  (
341
   .DataIn    (DataIn[`ETH_IPGT_WIDTH-1:0]),
342
   .DataOut   (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
343
   .Write     (IPGT_Wr),
344
   .Clk       (Clk),
345
   .Reset     (Reset),
346 141 mohor
   .SyncReset (1'b0)
347 139 mohor
  );
348
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
349 52 billditt
 
350 139 mohor
// IPGR1 Register
351
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF)        IPGR1
352
  (
353
   .DataIn    (DataIn[`ETH_IPGR1_WIDTH-1:0]),
354
   .DataOut   (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
355
   .Write     (IPGR1_Wr),
356
   .Clk       (Clk),
357
   .Reset     (Reset),
358 141 mohor
   .SyncReset (1'b0)
359 139 mohor
  );
360
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
361 15 mohor
 
362 139 mohor
// IPGR2 Register
363
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF)        IPGR2
364
  (
365
   .DataIn    (DataIn[`ETH_IPGR2_WIDTH-1:0]),
366
   .DataOut   (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
367
   .Write     (IPGR2_Wr),
368
   .Clk       (Clk),
369
   .Reset     (Reset),
370 141 mohor
   .SyncReset (1'b0)
371 139 mohor
  );
372
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
373 15 mohor
 
374 139 mohor
// PACKETLEN Register
375
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
376
  (
377
   .DataIn    (DataIn),
378
   .DataOut   (PACKETLENOut),
379
   .Write     (PACKETLEN_Wr),
380
   .Clk       (Clk),
381
   .Reset     (Reset),
382 141 mohor
   .SyncReset (1'b0)
383 139 mohor
  );
384 15 mohor
 
385 139 mohor
// COLLCONF Register
386
eth_register #(6, `ETH_COLLCONF0_DEF)                   COLLCONF0
387
  (
388
   .DataIn    (DataIn[5:0]),
389
   .DataOut   (COLLCONFOut[5:0]),
390
   .Write     (COLLCONF_Wr),
391
   .Clk       (Clk),
392
   .Reset     (Reset),
393 141 mohor
   .SyncReset (1'b0)
394 139 mohor
  );
395 68 mohor
assign COLLCONFOut[15:6] = 0;
396 139 mohor
 
397
eth_register #(4, `ETH_COLLCONF1_DEF)                   COLLCONF1
398
  (
399
   .DataIn    (DataIn[19:16]),
400
   .DataOut   (COLLCONFOut[19:16]),
401
   .Write     (COLLCONF_Wr),
402
   .Clk       (Clk),
403
   .Reset     (Reset),
404 141 mohor
   .SyncReset (1'b0)
405 139 mohor
  );
406 68 mohor
assign COLLCONFOut[31:20] = 0;
407 15 mohor
 
408 139 mohor
// TX_BD_NUM Register
409
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
410
  (
411
   .DataIn    (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
412
   .DataOut   (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
413 143 mohor
   .Write     (TX_BD_NUM_Wr & (DataIn<='h80)),
414 139 mohor
   .Clk       (Clk),
415
   .Reset     (Reset),
416 141 mohor
   .SyncReset (1'b0)
417 139 mohor
  );
418
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
419 15 mohor
 
420 139 mohor
// CTRLMODER Register
421
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF)  CTRLMODER2
422
  (
423
   .DataIn    (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
424
   .DataOut   (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
425
   .Write     (CTRLMODER_Wr),
426
   .Clk       (Clk),
427
   .Reset     (Reset),
428 141 mohor
   .SyncReset (1'b0)
429 139 mohor
  );
430
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
431 15 mohor
 
432 139 mohor
// MIIMODER Register
433
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF)    MIIMODER
434
  (
435
   .DataIn    (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
436
   .DataOut   (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
437
   .Write     (MIIMODER_Wr),
438
   .Clk       (Clk),
439
   .Reset     (Reset),
440 141 mohor
   .SyncReset (1'b0)
441 139 mohor
  );
442
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
443 68 mohor
 
444 139 mohor
// MIICOMMAND Register
445
eth_register #(1, 0)                                      MIICOMMAND0
446
  (
447
   .DataIn    (DataIn[0]),
448
   .DataOut   (MIICOMMANDOut[0]),
449
   .Write     (MIICOMMAND_Wr),
450
   .Clk       (Clk),
451
   .Reset     (Reset),
452 141 mohor
   .SyncReset (1'b0)
453 139 mohor
  );
454
 
455
eth_register #(1, 0)                                      MIICOMMAND1
456
  (
457
   .DataIn    (DataIn[1]),
458
   .DataOut   (MIICOMMANDOut[1]),
459
   .Write     (MIICOMMAND_Wr),
460
   .Clk       (Clk),
461
   .Reset     (Reset),
462
   .SyncReset (RStatStart)
463
  );
464
 
465
eth_register #(1, 0)                                      MIICOMMAND2
466
  (
467
   .DataIn    (DataIn[2]),
468
   .DataOut   (MIICOMMANDOut[2]),
469
   .Write     (MIICOMMAND_Wr),
470
   .Clk       (Clk),
471
   .Reset     (Reset),
472
   .SyncReset (WCtrlDataStart)
473
  );
474 15 mohor
assign MIICOMMANDOut[31:3] = 29'h0;
475
 
476 139 mohor
// MIIADDRESSRegister
477
eth_register #(5, `ETH_MIIADDRESS0_DEF)                   MIIADDRESS0
478
  (
479
   .DataIn    (DataIn[4:0]),
480
   .DataOut   (MIIADDRESSOut[4:0]),
481
   .Write     (MIIADDRESS_Wr),
482
   .Clk       (Clk),
483
   .Reset     (Reset),
484 141 mohor
   .SyncReset (1'b0)
485 139 mohor
  );
486 68 mohor
assign MIIADDRESSOut[7:5] = 0;
487 139 mohor
 
488
eth_register #(5, `ETH_MIIADDRESS1_DEF)                   MIIADDRESS1
489
  (
490
   .DataIn    (DataIn[12:8]),
491
   .DataOut   (MIIADDRESSOut[12:8]),
492
   .Write     (MIIADDRESS_Wr),
493
   .Clk       (Clk),
494
   .Reset     (Reset),
495 141 mohor
   .SyncReset (1'b0)
496 139 mohor
  );
497 68 mohor
assign MIIADDRESSOut[31:13] = 0;
498 15 mohor
 
499 139 mohor
// MIITX_DATA Register
500
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
501
  (
502
   .DataIn    (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
503 140 mohor
   .DataOut   (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
504 139 mohor
   .Write     (MIITX_DATA_Wr),
505
   .Clk       (Clk),
506
   .Reset     (Reset),
507 141 mohor
   .SyncReset (1'b0)
508 139 mohor
  );
509
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
510 15 mohor
 
511 139 mohor
// MIIRX_DATA Register
512
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
513
  (
514
   .DataIn    (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
515
   .DataOut   (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
516
   .Write     (MIIRX_DATA_Wr),
517
   .Clk       (Clk),
518
   .Reset     (Reset),
519 141 mohor
   .SyncReset (1'b0)
520 139 mohor
  );
521
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
522 15 mohor
 
523 139 mohor
// MAC_ADDR0 Register
524
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF)  MAC_ADDR0
525
  (
526
   .DataIn    (DataIn),
527
   .DataOut   (MAC_ADDR0Out),
528
   .Write     (MAC_ADDR0_Wr),
529
   .Clk       (Clk),
530
   .Reset     (Reset),
531 141 mohor
   .SyncReset (1'b0)
532 139 mohor
  );
533 68 mohor
 
534 139 mohor
// MAC_ADDR1 Register
535
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF)  MAC_ADDR1
536
  (
537
   .DataIn    (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
538
   .DataOut   (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
539
   .Write     (MAC_ADDR1_Wr),
540
   .Clk       (Clk),
541
   .Reset     (Reset),
542 141 mohor
   .SyncReset (1'b0)
543 139 mohor
  );
544
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
545 68 mohor
 
546 139 mohor
// RXHASH0 Register
547
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF)          RXHASH0
548
  (
549
   .DataIn    (DataIn),
550
   .DataOut   (HASH0Out),
551
   .Write     (HASH0_Wr),
552
   .Clk       (Clk),
553
   .Reset     (Reset),
554 141 mohor
   .SyncReset (1'b0)
555 139 mohor
  );
556 68 mohor
 
557 139 mohor
// RXHASH1 Register
558
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF)          RXHASH1
559
  (
560
   .DataIn    (DataIn),
561
   .DataOut   (HASH1Out),
562
   .Write     (HASH1_Wr),
563
   .Clk       (Clk),
564
   .Reset     (Reset),
565 141 mohor
   .SyncReset (1'b0)
566 139 mohor
  );
567 68 mohor
 
568 15 mohor
 
569 147 mohor
// TXCTRL Register
570
eth_register #((`ETH_TX_CTRL_WIDTH-1), {(`ETH_TX_CTRL_WIDTH-1){1'b0}})      TXCTRL0
571
  (
572
   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH-2:0]),
573
   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH-2:0]),
574
   .Write     (TXCTRL_Wr),
575
   .Clk       (Clk),
576
   .Reset     (Reset),
577
   .SyncReset (1'b0)
578
  );
579
 
580
eth_register #(1, 1'b0)                                   TXCTRL1     // Request bit is synchronously reset
581
  (
582
   .DataIn    (DataIn[16]),
583
   .DataOut   (TXCTRLOut[16]),
584
   .Write     (TXCTRL_Wr),
585
   .Clk       (Clk),
586
   .Reset     (Reset),
587
   .SyncReset (RstTxPauseRq)
588
  );
589
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH] = 0;
590
 
591
 
592
// RXCTRL Register
593
eth_register #(`ETH_RX_CTRL_WIDTH, `ETH_RX_CTRL_DEF)      RXCTRL
594
  (
595
   .DataIn    (DataIn[`ETH_RX_CTRL_WIDTH-1:0]),
596
   .DataOut   (RXCTRLOut[`ETH_RX_CTRL_WIDTH-1:0]),
597
   .Write     (RXCTRL_Wr),
598
   .Clk       (Clk),
599
   .Reset     (Reset),
600
   .SyncReset (1'b0)
601
  );
602
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH] = 0;
603
 
604
 
605 139 mohor
// Reading data from registers
606
always @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or
607
          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or
608
          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or
609
          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or
610
          MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or
611 147 mohor
          HASH0Out      or HASH1Out       or TXCTRLOut      or RXCTRLOut
612
          or reg1 or reg2 or reg3 or reg4
613 139 mohor
         )
614 15 mohor
begin
615
  if(Read)  // read
616
    begin
617
      case(Address)
618 20 mohor
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
619
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
620
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
621
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
622
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
623
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
624
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
625
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
626
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
627
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
628
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
629
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
630
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
631
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
632
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
633
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
634
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
635 34 mohor
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
636 56 mohor
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
637
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
638 147 mohor
        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;
639
        `ETH_RX_CTRL_ADR      :  DataOut<=RXCTRLOut;
640
 
641
        8'h16   /* 0x58 */    :  DataOut<=reg1;
642
        8'h17   /* 0x5c */    :  DataOut<=reg2;
643
        8'h18   /* 0x60 */    :  DataOut<=reg3;
644
        8'h19   /* 0x64 */    :  DataOut<=reg4;
645
 
646 15 mohor
        default:             DataOut<=32'h0;
647
      endcase
648
    end
649
  else
650
    DataOut<=32'h0;
651
end
652
 
653
 
654
assign r_RecSmall         = MODEROut[16];
655
assign r_Pad              = MODEROut[15];
656
assign r_HugEn            = MODEROut[14];
657
assign r_CrcEn            = MODEROut[13];
658
assign r_DlyCrcEn         = MODEROut[12];
659
assign r_Rst              = MODEROut[11];
660
assign r_FullD            = MODEROut[10];
661
assign r_ExDfrEn          = MODEROut[9];
662
assign r_NoBckof          = MODEROut[8];
663
assign r_LoopBck          = MODEROut[7];
664
assign r_IFG              = MODEROut[6];
665
assign r_Pro              = MODEROut[5];
666
assign r_Iam              = MODEROut[4];
667
assign r_Bro              = MODEROut[3];
668
assign r_NoPre            = MODEROut[2];
669 143 mohor
assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.
670
assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.
671 15 mohor
 
672
assign r_IPGT[6:0]        = IPGTOut[6:0];
673
 
674
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
675
 
676
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
677
 
678
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
679
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
680
 
681 56 mohor
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
682
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
683 15 mohor
 
684
assign r_TxFlow           = CTRLMODEROut[2];
685
assign r_RxFlow           = CTRLMODEROut[1];
686
assign r_PassAll          = CTRLMODEROut[0];
687
 
688 139 mohor
assign r_MiiMRst          = MIIMODEROut[9];
689 15 mohor
assign r_MiiNoPre         = MIIMODEROut[8];
690
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
691
 
692
assign r_WCtrlData        = MIICOMMANDOut[2];
693
assign r_RStat            = MIICOMMANDOut[1];
694
assign r_ScanStat         = MIICOMMANDOut[0];
695
 
696
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
697
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
698
 
699
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
700
 
701 139 mohor
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
702
assign MIISTATUSOut[2]    = NValid_stat         ;
703
assign MIISTATUSOut[1]    = Busy_stat           ;
704
assign MIISTATUSOut[0]    = LinkFail            ;
705 15 mohor
 
706
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
707
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
708 52 billditt
assign r_HASH1[31:0]      = HASH1Out;
709
assign r_HASH0[31:0]      = HASH0Out;
710 15 mohor
 
711 147 mohor
assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];
712 15 mohor
 
713 147 mohor
assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];
714
assign r_TxPauseRq        = TXCTRLOut[16];
715 15 mohor
 
716 147 mohor
 
717
// Synchronizing TxC Interrupt
718
always @ (posedge TxClk or posedge Reset)
719
begin
720
  if(Reset)
721
    SetTxCIrq_txclk <=#Tp 1'b0;
722
  else
723
  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
724
    SetTxCIrq_txclk <=#Tp 1'b1;
725
  else
726
  if(ResetTxCIrq_sync2)
727
    SetTxCIrq_txclk <=#Tp 1'b0;
728
end
729
 
730
 
731
always @ (posedge Clk or posedge Reset)
732
begin
733
  if(Reset)
734
    SetTxCIrq_sync1 <=#Tp 1'b0;
735
  else
736
    SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
737
end
738
 
739
always @ (posedge Clk or posedge Reset)
740
begin
741
  if(Reset)
742
    SetTxCIrq_sync2 <=#Tp 1'b0;
743
  else
744
    SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
745
end
746
 
747
always @ (posedge Clk or posedge Reset)
748
begin
749
  if(Reset)
750
    SetTxCIrq_sync3 <=#Tp 1'b0;
751
  else
752
    SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
753
end
754
 
755
always @ (posedge Clk or posedge Reset)
756
begin
757
  if(Reset)
758
    SetTxCIrq <=#Tp 1'b0;
759
  else
760
    SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
761
end
762
 
763
always @ (posedge TxClk or posedge Reset)
764
begin
765
  if(Reset)
766
    ResetTxCIrq_sync1 <=#Tp 1'b0;
767
  else
768
    ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
769
end
770
 
771
always @ (posedge TxClk or posedge Reset)
772
begin
773
  if(Reset)
774
    ResetTxCIrq_sync2 <=#Tp 1'b0;
775
  else
776
    ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
777
end
778
 
779
 
780
// Synchronizing RxC Interrupt
781
always @ (posedge RxClk or posedge Reset)
782
begin
783
  if(Reset)
784
    SetRxCIrq_rxclk <=#Tp 1'b0;
785
  else
786
  if(ReceivedPauseFrm & r_RxFlow)
787
    SetRxCIrq_rxclk <=#Tp 1'b1;
788
  else
789
  if(ResetRxCIrq_sync2)
790
    SetRxCIrq_rxclk <=#Tp 1'b0;
791
end
792
 
793
 
794
always @ (posedge Clk or posedge Reset)
795
begin
796
  if(Reset)
797
    SetRxCIrq_sync1 <=#Tp 1'b0;
798
  else
799
    SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
800
end
801
 
802
always @ (posedge Clk or posedge Reset)
803
begin
804
  if(Reset)
805
    SetRxCIrq_sync2 <=#Tp 1'b0;
806
  else
807
    SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
808
end
809
 
810
always @ (posedge Clk or posedge Reset)
811
begin
812
  if(Reset)
813
    SetRxCIrq_sync3 <=#Tp 1'b0;
814
  else
815
    SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
816
end
817
 
818
always @ (posedge Clk or posedge Reset)
819
begin
820
  if(Reset)
821
    SetRxCIrq <=#Tp 1'b0;
822
  else
823
    SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
824
end
825
 
826
always @ (posedge RxClk or posedge Reset)
827
begin
828
  if(Reset)
829
    ResetRxCIrq_sync1 <=#Tp 1'b0;
830
  else
831
    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
832
end
833
 
834
always @ (posedge TxClk or posedge Reset)
835
begin
836
  if(Reset)
837
    ResetRxCIrq_sync2 <=#Tp 1'b0;
838
  else
839
    ResetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
840
end
841
 
842
 
843
 
844
 
845
 
846
 
847
 
848 21 mohor
// Interrupt generation
849
always @ (posedge Clk or posedge Reset)
850
begin
851
  if(Reset)
852
    irq_txb <= 1'b0;
853
  else
854 102 mohor
  if(TxB_IRQ)
855 21 mohor
    irq_txb <= #Tp 1'b1;
856
  else
857
  if(INT_SOURCE_Wr & DataIn[0])
858
    irq_txb <= #Tp 1'b0;
859
end
860
 
861
always @ (posedge Clk or posedge Reset)
862
begin
863
  if(Reset)
864
    irq_txe <= 1'b0;
865
  else
866 102 mohor
  if(TxE_IRQ)
867 21 mohor
    irq_txe <= #Tp 1'b1;
868
  else
869
  if(INT_SOURCE_Wr & DataIn[1])
870
    irq_txe <= #Tp 1'b0;
871
end
872
 
873
always @ (posedge Clk or posedge Reset)
874
begin
875
  if(Reset)
876
    irq_rxb <= 1'b0;
877
  else
878 102 mohor
  if(RxB_IRQ)
879 21 mohor
    irq_rxb <= #Tp 1'b1;
880
  else
881
  if(INT_SOURCE_Wr & DataIn[2])
882
    irq_rxb <= #Tp 1'b0;
883
end
884
 
885
always @ (posedge Clk or posedge Reset)
886
begin
887
  if(Reset)
888 74 mohor
    irq_rxe <= 1'b0;
889 21 mohor
  else
890 102 mohor
  if(RxE_IRQ)
891 74 mohor
    irq_rxe <= #Tp 1'b1;
892 21 mohor
  else
893
  if(INT_SOURCE_Wr & DataIn[3])
894 74 mohor
    irq_rxe <= #Tp 1'b0;
895 21 mohor
end
896
 
897
always @ (posedge Clk or posedge Reset)
898
begin
899
  if(Reset)
900
    irq_busy <= 1'b0;
901
  else
902 102 mohor
  if(Busy_IRQ)
903 21 mohor
    irq_busy <= #Tp 1'b1;
904
  else
905
  if(INT_SOURCE_Wr & DataIn[4])
906
    irq_busy <= #Tp 1'b0;
907
end
908
 
909 74 mohor
always @ (posedge Clk or posedge Reset)
910
begin
911
  if(Reset)
912
    irq_txc <= 1'b0;
913
  else
914 147 mohor
  if(SetTxCIrq)
915 74 mohor
    irq_txc <= #Tp 1'b1;
916
  else
917
  if(INT_SOURCE_Wr & DataIn[5])
918
    irq_txc <= #Tp 1'b0;
919
end
920
 
921
always @ (posedge Clk or posedge Reset)
922
begin
923
  if(Reset)
924
    irq_rxc <= 1'b0;
925
  else
926 147 mohor
  if(SetRxCIrq)
927 74 mohor
    irq_rxc <= #Tp 1'b1;
928
  else
929
  if(INT_SOURCE_Wr & DataIn[6])
930
    irq_rxc <= #Tp 1'b0;
931
end
932
 
933 21 mohor
// Generating interrupt signal
934 102 mohor
assign int_o = irq_txb  & INT_MASKOut[0] |
935
               irq_txe  & INT_MASKOut[1] |
936
               irq_rxb  & INT_MASKOut[2] |
937
               irq_rxe  & INT_MASKOut[3] |
938
               irq_busy & INT_MASKOut[4] |
939
               irq_txc  & INT_MASKOut[5] |
940
               irq_rxc  & INT_MASKOut[6] ;
941 21 mohor
 
942
// For reading interrupt status
943 139 mohor
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
944 21 mohor
 
945
 
946
 
947 15 mohor
endmodule

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