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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 106

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Line No. Rev Author Line
1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
45
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
46
// bug fixed.
47
//
48 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
49
// Small typo fixed.
50
//
51 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
52
// Any address can be used for Tx and Rx BD pointers. Address does not need
53
// to be aligned.
54
//
55 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
56
// Comments in Slovene language removed.
57
//
58 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
59
// casex changed with case, fifo reset changed.
60
//
61 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
62
// rx_fifo was not always cleared ok. Fixed.
63
//
64 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
65
// Status was not latched correctly sometimes. Fixed.
66
//
67 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
68
// Big Endian problem when sending frames fixed.
69
//
70 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
71
// Byte ordering changed (Big Endian used). casex changed with case because
72
// Xilinx Foundation had problems. Tested in HW. It WORKS.
73
//
74 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
75
// Small fixes for external/internal DMA missmatches.
76
//
77 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
78
// Interrupts changed
79
//
80 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
81
// Status was not written correctly when frames were discarted because of
82
// address mismatch.
83
//
84 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
85
// RxStartFrm cleared when abort or retry comes.
86
//
87 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
88
// Changes that were lost when updating from 1.5 to 1.8 fixed.
89
//
90 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
91
// Addition  of new module eth_addrcheck.v
92
//
93
// Revision 1.7  2002/02/12 17:03:47  mohor
94
// RxOverRun added to statuses.
95
//
96
// Revision 1.6  2002/02/11 09:18:22  mohor
97
// Tx status is written back to the BD.
98
//
99 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
100
// Rx status is written back to the BD.
101
//
102 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
103
// non-DMA host interface added. Select the right configutation in eth_defines.
104
//
105 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
106
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
107
// MHz. Statuses, overrun, control frame transmission and reception still  need
108
// to be fixed.
109
//
110 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
111
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
112
// added.
113
//
114 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
115
// Initial version. Equals to eth_wishbonedma.v at this moment.
116 38 mohor
//
117
//
118
//
119 39 mohor
//
120 38 mohor
 
121 77 mohor
// Build pause frame
122
// Check GotData and evaluate data (abort or something like that comes before StartFrm)
123
// m_wb_err_i should start status underrun or uverrun
124
// r_RecSmall not used
125 38 mohor
 
126
`include "eth_defines.v"
127
`include "timescale.v"
128
 
129
 
130
module eth_wishbone
131
   (
132
 
133
    // WISHBONE common
134 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
135 38 mohor
 
136
    // WISHBONE slave
137 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
138 40 mohor
    BDCs,
139 38 mohor
 
140 40 mohor
    Reset,
141
 
142 39 mohor
    // WISHBONE master
143
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
144
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
145
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
146
 
147 38 mohor
    //TX
148 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
149 38 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,
150
    PerPacketPad,
151
 
152
    //RX
153 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
154 38 mohor
 
155
    // Register
156 77 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RecSmall,
157 38 mohor
 
158 91 mohor
    WillSendControlFrame, TxCtrlEndFrm, // WillSendControlFrame out ?
159 38 mohor
 
160
    // Interrupts
161 77 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
162 42 mohor
 
163 60 mohor
    // Rx Status
164 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
165 77 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
166 60 mohor
 
167
    // Tx Status
168
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
169 38 mohor
                );
170
 
171
 
172
parameter Tp = 1;
173
 
174
// WISHBONE common
175
input           WB_CLK_I;       // WISHBONE clock
176
input  [31:0]   WB_DAT_I;       // WISHBONE data input
177
output [31:0]   WB_DAT_O;       // WISHBONE data output
178
 
179
// WISHBONE slave
180
input   [9:2]   WB_ADR_I;       // WISHBONE address input
181
input           WB_WE_I;        // WISHBONE write enable input
182
input           BDCs;           // Buffer descriptors are selected
183
output          WB_ACK_O;       // WISHBONE acknowledge output
184
 
185 39 mohor
// WISHBONE master
186
output  [31:0]  m_wb_adr_o;     // 
187
output   [3:0]  m_wb_sel_o;     // 
188
output          m_wb_we_o;      // 
189
output  [31:0]  m_wb_dat_o;     // 
190
output          m_wb_cyc_o;     // 
191
output          m_wb_stb_o;     // 
192
input   [31:0]  m_wb_dat_i;     // 
193
input           m_wb_ack_i;     // 
194
input           m_wb_err_i;     // 
195
 
196 40 mohor
input           Reset;       // Reset signal
197 39 mohor
 
198 60 mohor
// Rx Status signals
199 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
200
input           LatchedCrcError;  // CRC error
201
input           RxLateCollision;  // Late collision occured while receiving frame
202
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
203
input           DribbleNibble;    // Extra nibble received
204
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
205
input    [15:0] RxLength;         // Length of the incoming frame
206
input           LoadRxStatus;     // Rx status was loaded
207 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
208 39 mohor
 
209 60 mohor
// Tx Status signals
210
input     [3:0] RetryCntLatched;  // Latched Retry Counter
211
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
212
input           LateCollLatched;  // Late collision occured
213
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
214
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
215
 
216 38 mohor
// Tx
217
input           MTxClk;         // Transmit clock (from PHY)
218
input           TxUsedData;     // Transmit packet used data
219
input           TxRetry;        // Transmit packet retry
220
input           TxAbort;        // Transmit packet abort
221
input           TxDone;         // Transmission ended
222
output          TxStartFrm;     // Transmit packet start frame
223
output          TxEndFrm;       // Transmit packet end frame
224
output  [7:0]   TxData;         // Transmit packet data byte
225
output          TxUnderRun;     // Transmit packet under-run
226
output          PerPacketCrcEn; // Per packet crc enable
227
output          PerPacketPad;   // Per packet pading
228
output          TPauseRq;       // Tx PAUSE control frame
229
output [15:0]   TxPauseTV;      // PAUSE timer value
230
input           WillSendControlFrame;
231
input           TxCtrlEndFrm;
232
 
233
// Rx
234
input           MRxClk;         // Receive clock (from PHY)
235
input   [7:0]   RxData;         // Received data byte (from PHY)
236
input           RxValid;        // 
237
input           RxStartFrm;     // 
238
input           RxEndFrm;       // 
239 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
240 38 mohor
 
241
//Register
242
input           r_TxEn;         // Transmit enable
243
input           r_RxEn;         // Receive enable
244
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
245
input           TX_BD_NUM_Wr;   // RxBDNumber written
246 42 mohor
input           r_RecSmall;     // Receive small frames igor !!! tega uporabi
247 38 mohor
 
248
// Interrupts
249
output TxB_IRQ;
250
output TxE_IRQ;
251
output RxB_IRQ;
252 77 mohor
output RxE_IRQ;
253 38 mohor
output Busy_IRQ;
254 77 mohor
output TxC_IRQ;
255
output RxC_IRQ;
256 38 mohor
 
257 77 mohor
 
258
reg TxB_IRQ;
259
reg TxE_IRQ;
260
reg RxB_IRQ;
261
reg RxE_IRQ;
262
 
263
 
264 38 mohor
reg             TxStartFrm;
265
reg             TxEndFrm;
266
reg     [7:0]   TxData;
267
 
268
reg             TxUnderRun;
269 60 mohor
reg             TxUnderRun_wb;
270 38 mohor
 
271
reg             TxBDRead;
272 39 mohor
wire            TxStatusWrite;
273 38 mohor
 
274
reg     [1:0]   TxValidBytesLatched;
275
 
276
reg    [15:0]   TxLength;
277 60 mohor
reg    [15:0]   LatchedTxLength;
278
reg   [14:11]   TxStatus;
279 38 mohor
 
280 60 mohor
reg   [14:13]   RxStatus;
281 38 mohor
 
282
reg             TxStartFrm_wb;
283
reg             TxRetry_wb;
284 39 mohor
reg             TxAbort_wb;
285 38 mohor
reg             TxDone_wb;
286
 
287
reg             TxDone_wb_q;
288
reg             TxAbort_wb_q;
289 39 mohor
reg             TxRetry_wb_q;
290 105 mohor
reg             TxDone_wb_q2;
291
reg             TxAbort_wb_q2;
292
reg             TxRetry_wb_q2;
293 38 mohor
reg             RxBDReady;
294
reg             TxBDReady;
295
 
296
reg             RxBDRead;
297 40 mohor
wire            RxStatusWrite;
298 38 mohor
 
299
reg    [31:0]   TxDataLatched;
300
reg     [1:0]   TxByteCnt;
301
reg             LastWord;
302 39 mohor
reg             ReadTxDataFromFifo_tck;
303 38 mohor
 
304
reg             BlockingTxStatusWrite;
305
reg             BlockingTxBDRead;
306
 
307 40 mohor
reg             Flop;
308 38 mohor
 
309
reg     [7:0]   TxBDAddress;
310
reg     [7:0]   RxBDAddress;
311
 
312
reg             TxRetrySync1;
313
reg             TxAbortSync1;
314 39 mohor
reg             TxDoneSync1;
315 38 mohor
 
316
reg             TxAbort_q;
317
reg             TxRetry_q;
318
reg             TxUsedData_q;
319
 
320
reg    [31:0]   RxDataLatched2;
321 82 mohor
 
322
// reg    [23:0]   RxDataLatched1;
323
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
324
 
325 38 mohor
reg     [1:0]   RxValidBytes;
326
reg     [1:0]   RxByteCnt;
327
reg             LastByteIn;
328
reg             ShiftWillEnd;
329
 
330 40 mohor
reg             WriteRxDataToFifo;
331 42 mohor
reg    [15:0]   LatchedRxLength;
332 64 mohor
reg             RxAbortLatched;
333 38 mohor
 
334 40 mohor
reg             ShiftEnded;
335 60 mohor
reg             RxOverrun;
336 38 mohor
 
337 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
338
reg             BDRead;                     // BD Read access from WISHBONE side
339 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
340
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
341 38 mohor
 
342 39 mohor
reg             TxEndFrm_wb;
343 38 mohor
 
344 39 mohor
wire            TxRetryPulse;
345 38 mohor
wire            TxDonePulse;
346
wire            TxAbortPulse;
347 105 mohor
wire            TxRetryPulse_q;
348
wire            TxDonePulse_q;
349
wire            TxAbortPulse_q;
350 38 mohor
 
351
wire            StartRxBDRead;
352
 
353
wire            StartTxBDRead;
354
 
355
wire            TxIRQEn;
356
wire            WrapTxStatusBit;
357
 
358 77 mohor
wire            RxIRQEn;
359 38 mohor
wire            WrapRxStatusBit;
360
 
361
wire    [1:0]   TxValidBytes;
362
 
363
wire    [7:0]   TempTxBDAddress;
364
wire    [7:0]   TempRxBDAddress;
365
 
366
wire            SetGotData;
367
wire            GotDataEvaluate;
368
 
369 106 mohor
reg             WB_ACK_O;
370 38 mohor
 
371 60 mohor
wire    [6:0]   RxStatusIn;
372
reg     [6:0]   RxStatusInLatched;
373 42 mohor
 
374 39 mohor
reg WbEn, WbEn_q;
375
reg RxEn, RxEn_q;
376
reg TxEn, TxEn_q;
377 38 mohor
 
378 39 mohor
wire ram_ce;
379
wire ram_we;
380
wire ram_oe;
381
reg [7:0]   ram_addr;
382
reg [31:0]  ram_di;
383
wire [31:0] ram_do;
384 38 mohor
 
385 39 mohor
wire StartTxPointerRead;
386
reg  TxPointerRead;
387
reg TxEn_needed;
388 40 mohor
reg RxEn_needed;
389 38 mohor
 
390 40 mohor
wire StartRxPointerRead;
391
reg RxPointerRead;
392 38 mohor
 
393 39 mohor
 
394 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
395
begin
396
  if(Reset)
397
    begin
398 106 mohor
      WB_ACK_O <=#Tp 1'b0;
399 40 mohor
    end
400
  else
401
    begin
402 106 mohor
      WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
403 40 mohor
    end
404
end
405 39 mohor
 
406 106 mohor
assign WB_DAT_O = ram_do;
407 39 mohor
 
408 41 mohor
// Generic synchronous single-port RAM interface
409 39 mohor
generic_spram #(8, 32) ram (
410
        // Generic synchronous single-port RAM interface
411 40 mohor
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
412 39 mohor
);
413 41 mohor
 
414 39 mohor
assign ram_ce = 1'b1;
415 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
416 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
417 39 mohor
 
418
 
419 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
420 38 mohor
begin
421 40 mohor
  if(Reset)
422 39 mohor
    TxEn_needed <=#Tp 1'b0;
423 38 mohor
  else
424 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
425 39 mohor
    TxEn_needed <=#Tp 1'b1;
426
  else
427
  if(TxPointerRead & TxEn & TxEn_q)
428
    TxEn_needed <=#Tp 1'b0;
429 38 mohor
end
430
 
431 106 mohor
reg [3:0] stm_status;
432 39 mohor
// Enabling access to the RAM for three devices.
433 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
434 39 mohor
begin
435 40 mohor
  if(Reset)
436 39 mohor
    begin
437
      WbEn <=#Tp 1'b1;
438
      RxEn <=#Tp 1'b0;
439
      TxEn <=#Tp 1'b0;
440
      ram_addr <=#Tp 8'h0;
441
      ram_di <=#Tp 32'h0;
442 77 mohor
      BDRead <=#Tp 1'b0;
443
      BDWrite <=#Tp 1'b0;
444 106 mohor
stm_status <=#Tp 4'h0;
445 39 mohor
    end
446
  else
447
    begin
448
      // Switching between three stages depends on enable signals
449 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
450
        5'b100_10, 5'b100_11 :
451 39 mohor
          begin
452 106 mohor
stm_status <=#Tp 4'h1;
453 39 mohor
            WbEn <=#Tp 1'b0;
454
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
455
            TxEn <=#Tp 1'b0;
456 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
457 39 mohor
            ram_di <=#Tp RxBDDataIn;
458
          end
459
        5'b100_01 :
460
          begin
461 106 mohor
stm_status <=#Tp 4'h2;
462 39 mohor
            WbEn <=#Tp 1'b0;
463
            RxEn <=#Tp 1'b0;
464
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
465
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
466
            ram_di <=#Tp TxBDDataIn;
467
          end
468 90 mohor
        5'b010_00, 5'b010_10 :
469 39 mohor
          begin
470 106 mohor
stm_status <=#Tp 4'h3;
471 39 mohor
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
472
            RxEn <=#Tp 1'b0;
473
            TxEn <=#Tp 1'b0;
474
            ram_addr <=#Tp WB_ADR_I[9:2];
475
            ram_di <=#Tp WB_DAT_I;
476 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
477
            BDRead <=#Tp BDCs & ~WB_WE_I;
478 39 mohor
          end
479 90 mohor
        5'b010_01, 5'b010_11 :
480 39 mohor
          begin
481 106 mohor
stm_status <=#Tp 4'h4;
482 39 mohor
            WbEn <=#Tp 1'b0;
483
            RxEn <=#Tp 1'b0;
484
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
485
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
486
            ram_di <=#Tp TxBDDataIn;
487
          end
488 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
489 39 mohor
          begin
490 106 mohor
stm_status <=#Tp 4'h5;
491 39 mohor
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
492
            RxEn <=#Tp 1'b0;
493
            TxEn <=#Tp 1'b0;
494
            ram_addr <=#Tp WB_ADR_I[9:2];
495
            ram_di <=#Tp WB_DAT_I;
496 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
497
            BDRead <=#Tp BDCs & ~WB_WE_I;
498 39 mohor
          end
499
        5'b100_00 :
500
          begin
501 106 mohor
stm_status <=#Tp 4'h6;
502 39 mohor
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
503
          end
504
        5'b000_00 :
505
          begin
506 106 mohor
stm_status <=#Tp 4'h7;
507 39 mohor
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
508
            RxEn <=#Tp 1'b0;
509
            TxEn <=#Tp 1'b0;
510
            ram_addr <=#Tp WB_ADR_I[9:2];
511
            ram_di <=#Tp WB_DAT_I;
512 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
513
            BDRead <=#Tp BDCs & ~WB_WE_I;
514 39 mohor
          end
515
        default :
516
          begin
517
            WbEn <=#Tp 1'b1;  // We go to wb access stage
518
            RxEn <=#Tp 1'b0;
519
            TxEn <=#Tp 1'b0;
520
            ram_addr <=#Tp WB_ADR_I[9:2];
521
            ram_di <=#Tp WB_DAT_I;
522 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
523
            BDRead <=#Tp BDCs & ~WB_WE_I;
524 39 mohor
          end
525
      endcase
526
    end
527
end
528
 
529
 
530
// Delayed stage signals
531 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
532 39 mohor
begin
533 40 mohor
  if(Reset)
534 39 mohor
    begin
535
      WbEn_q <=#Tp 1'b0;
536
      RxEn_q <=#Tp 1'b0;
537
      TxEn_q <=#Tp 1'b0;
538
    end
539
  else
540
    begin
541
      WbEn_q <=#Tp WbEn;
542
      RxEn_q <=#Tp RxEn;
543
      TxEn_q <=#Tp TxEn;
544
    end
545
end
546
 
547 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
548 40 mohor
always @ (posedge MTxClk or posedge Reset)
549 38 mohor
begin
550 40 mohor
  if(Reset)
551 38 mohor
    Flop <=#Tp 1'b0;
552
  else
553
  if(TxDone | TxAbort | TxRetry_q)
554
    Flop <=#Tp 1'b0;
555
  else
556
  if(TxUsedData)
557
    Flop <=#Tp ~Flop;
558
end
559
 
560 39 mohor
wire ResetTxBDReady;
561
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
562 38 mohor
 
563
// Latching READY status of the Tx buffer descriptor
564 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
565 38 mohor
begin
566 40 mohor
  if(Reset)
567 38 mohor
    TxBDReady <=#Tp 1'b0;
568
  else
569 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
570
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
571
  else                                                // Only packets larger then 4 bytes are transmitted.
572 39 mohor
  if(ResetTxBDReady)
573 38 mohor
    TxBDReady <=#Tp 1'b0;
574
end
575
 
576
 
577 39 mohor
// Reading the Tx buffer descriptor
578
assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead;
579
 
580 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
581 38 mohor
begin
582 40 mohor
  if(Reset)
583 39 mohor
    TxBDRead <=#Tp 1'b1;
584 38 mohor
  else
585 90 mohor
  if(StartTxBDRead & ~TxBDReady)
586 39 mohor
    TxBDRead <=#Tp 1'b1;
587 38 mohor
  else
588 39 mohor
  if(TxBDReady)
589
    TxBDRead <=#Tp 1'b0;
590 38 mohor
end
591
 
592
 
593 39 mohor
// Reading Tx BD pointer
594
assign StartTxPointerRead = TxBDRead & TxBDReady;
595 38 mohor
 
596 39 mohor
// Reading Tx BD Pointer
597 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
598 38 mohor
begin
599 40 mohor
  if(Reset)
600 39 mohor
    TxPointerRead <=#Tp 1'b0;
601 38 mohor
  else
602 39 mohor
  if(StartTxPointerRead)
603
    TxPointerRead <=#Tp 1'b1;
604 38 mohor
  else
605 39 mohor
  if(TxEn_q)
606
    TxPointerRead <=#Tp 1'b0;
607 38 mohor
end
608
 
609
 
610 39 mohor
// Writing status back to the Tx buffer descriptor
611
assign TxStatusWrite = (TxDone_wb | TxAbort_wb) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
612 38 mohor
 
613
 
614
 
615 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
616 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
617 38 mohor
begin
618 40 mohor
  if(Reset)
619 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
620 38 mohor
  else
621 39 mohor
  if(TxStatusWrite)
622
    BlockingTxStatusWrite <=#Tp 1'b1;
623 38 mohor
  else
624 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
625
    BlockingTxStatusWrite <=#Tp 1'b0;
626 38 mohor
end
627
 
628
 
629 39 mohor
// TxBDRead state is activated only once. 
630 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
631 39 mohor
begin
632 40 mohor
  if(Reset)
633 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
634
  else
635 90 mohor
  if(StartTxBDRead & ~TxBDReady)
636 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
637
  else
638
  if(TxStartFrm_wb)
639
    BlockingTxBDRead <=#Tp 1'b0;
640
end
641 38 mohor
 
642
 
643 39 mohor
// Latching status from the tx buffer descriptor
644
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
645 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
646 38 mohor
begin
647 40 mohor
  if(Reset)
648 60 mohor
    TxStatus <=#Tp 4'h0;
649 38 mohor
  else
650 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
651 60 mohor
    TxStatus <=#Tp ram_do[14:11];
652 38 mohor
end
653
 
654 40 mohor
reg ReadTxDataFromMemory;
655
wire WriteRxDataToMemory;
656 38 mohor
 
657 39 mohor
reg MasterWbTX;
658
reg MasterWbRX;
659
 
660
reg [31:0] m_wb_adr_o;
661
reg        m_wb_cyc_o;
662
reg        m_wb_stb_o;
663 96 mohor
reg  [3:0] m_wb_sel_o;
664 39 mohor
reg        m_wb_we_o;
665 40 mohor
 
666 39 mohor
wire TxLengthEq0;
667
wire TxLengthLt4;
668
 
669 96 mohor
wire WordAccFinished;
670
wire HalfAccFinished;
671 39 mohor
 
672
//Latching length from the buffer descriptor;
673 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
674 38 mohor
begin
675 40 mohor
  if(Reset)
676 39 mohor
    TxLength <=#Tp 16'h0;
677 38 mohor
  else
678 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
679
    TxLength <=#Tp ram_do[31:16];
680 38 mohor
  else
681 39 mohor
  if(MasterWbTX & m_wb_ack_i)
682
    begin
683
      if(TxLengthLt4)
684
        TxLength <=#Tp 16'h0;
685 96 mohor
      else if(WordAccFinished)
686
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
687
      else if(HalfAccFinished)
688
        TxLength <=#Tp TxLength - 2'h2;    // Length is subtracted at the data request
689 39 mohor
      else
690 96 mohor
        TxLength <=#Tp TxLength - 1'h1;    // Length is subtracted at the data request
691 39 mohor
    end
692 38 mohor
end
693
 
694 96 mohor
assign WordAccFinished = &m_wb_sel_o[3:0];
695
assign HalfAccFinished = &m_wb_sel_o[1:0];
696
 
697
 
698
 
699 60 mohor
//Latching length from the buffer descriptor;
700
always @ (posedge WB_CLK_I or posedge Reset)
701
begin
702
  if(Reset)
703
    LatchedTxLength <=#Tp 16'h0;
704
  else
705
  if(TxEn & TxEn_q & TxBDRead)
706
    LatchedTxLength <=#Tp ram_do[31:16];
707
end
708
 
709 39 mohor
assign TxLengthEq0 = TxLength == 0;
710
assign TxLengthLt4 = TxLength < 4;
711 38 mohor
 
712 39 mohor
 
713
reg BlockingIncrementTxPointer;
714
 
715
reg [31:0] TxPointer;
716 96 mohor
reg [1:0]  TxPointerLatched;
717 39 mohor
reg [31:0] RxPointer;
718 96 mohor
reg [1:0]  RxPointerLatched;
719 39 mohor
 
720 96 mohor
wire TxBurstAcc;
721
wire TxWordAcc;
722
wire TxHalfAcc;
723
wire TxByteAcc;
724
 
725
wire RxBurstAcc;
726
wire RxWordAcc;
727
wire RxHalfAcc;
728
wire RxByteAcc;
729
 
730
 
731 39 mohor
//Latching Tx buffer pointer from buffer descriptor;
732 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
733 38 mohor
begin
734 40 mohor
  if(Reset)
735 39 mohor
    TxPointer <=#Tp 0;
736 38 mohor
  else
737 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
738
    TxPointer <=#Tp ram_do;
739 38 mohor
  else
740 39 mohor
  if(MasterWbTX & ~BlockingIncrementTxPointer)
741 96 mohor
    if(TxWordAcc)
742
      TxPointer <=#Tp TxPointer + 3'h4; // Word access
743
    else if(TxHalfAcc)
744
      TxPointer <=#Tp TxPointer + 2'h2; // Half access
745
    else
746
      TxPointer <=#Tp TxPointer + 1'h1; // Byte access
747 38 mohor
end
748
 
749 96 mohor
 
750
 
751
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
752
always @ (posedge WB_CLK_I or posedge Reset)
753
begin
754
  if(Reset)
755
    TxPointerLatched[1:0] <=#Tp 0;
756
  else
757
  if(TxEn & TxEn_q & TxPointerRead)
758
    TxPointerLatched[1:0] <=#Tp ram_do[1:0];
759
end
760
 
761
 
762
assign TxBurstAcc = ~TxPointer[3] & ~TxPointer[2] & ~TxPointer[1] & ~TxPointer[0]; // Add a counter that count burst to 4
763
assign TxWordAcc  = ~TxPointer[1] & ~TxPointer[0];
764
assign TxHalfAcc  =  TxPointer[1] & ~TxPointer[0];
765
assign TxByteAcc  =  TxPointer[0];
766
 
767
wire [3:0] m_wb_sel_tmp_tx;
768
reg  [3:0] m_wb_sel_tmp_rx;
769
 
770
 
771
assign m_wb_sel_tmp_tx[0] = TxWordAcc | TxHalfAcc | TxByteAcc &  TxPointer[1];
772
assign m_wb_sel_tmp_tx[1] = TxWordAcc | TxHalfAcc;
773 105 mohor
assign m_wb_sel_tmp_tx[2] = TxWordAcc |             TxByteAcc & ~TxPointer[1];
774 96 mohor
assign m_wb_sel_tmp_tx[3] = TxWordAcc;
775
 
776
 
777 39 mohor
wire MasterAccessFinished;
778 38 mohor
 
779 39 mohor
 
780 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
781 38 mohor
begin
782 40 mohor
  if(Reset)
783 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
784 38 mohor
  else
785 39 mohor
  if(MasterAccessFinished)
786
    BlockingIncrementTxPointer <=#Tp 0;
787 38 mohor
  else
788 39 mohor
  if(MasterWbTX)
789
    BlockingIncrementTxPointer <=#Tp 1'b1;
790 38 mohor
end
791
 
792
 
793 39 mohor
wire TxBufferAlmostFull;
794
wire TxBufferFull;
795
wire TxBufferEmpty;
796
wire TxBufferAlmostEmpty;
797 40 mohor
wire ResetReadTxDataFromMemory;
798
wire SetReadTxDataFromMemory;
799 39 mohor
 
800 40 mohor
reg BlockReadTxDataFromMemory;
801 39 mohor
 
802 105 mohor
assign ResetReadTxDataFromMemory = (TxLengthEq0) | TxAbortPulse_q | TxRetryPulse_q;
803 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
804 39 mohor
 
805 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
806 38 mohor
begin
807 40 mohor
  if(Reset)
808
    ReadTxDataFromMemory <=#Tp 1'b0;
809 38 mohor
  else
810 40 mohor
  if(ResetReadTxDataFromMemory)
811
    ReadTxDataFromMemory <=#Tp 1'b0;
812 39 mohor
  else
813 40 mohor
  if(SetReadTxDataFromMemory)
814
    ReadTxDataFromMemory <=#Tp 1'b1;
815 38 mohor
end
816
 
817 40 mohor
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
818 39 mohor
wire [31:0] TxData_wb;
819
wire ReadTxDataFromFifo_wb;
820 38 mohor
 
821 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
822 38 mohor
begin
823 40 mohor
  if(Reset)
824
    BlockReadTxDataFromMemory <=#Tp 1'b0;
825 38 mohor
  else
826 90 mohor
  if(ReadTxDataFromFifo_wb | ResetReadTxDataFromMemory)
827 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
828 38 mohor
  else
829 39 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
830 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
831 39 mohor
end
832
 
833
 
834
 
835
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
836
 
837 96 mohor
//assign m_wb_sel_o = 4'hf;
838 39 mohor
 
839
// Enabling master wishbone access to the memory for two devices TX and RX.
840 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
841 39 mohor
begin
842 40 mohor
  if(Reset)
843 38 mohor
    begin
844 39 mohor
      MasterWbTX <=#Tp 1'b0;
845
      MasterWbRX <=#Tp 1'b0;
846
      m_wb_adr_o <=#Tp 32'h0;
847
      m_wb_cyc_o <=#Tp 1'b0;
848
      m_wb_stb_o <=#Tp 1'b0;
849
      m_wb_we_o  <=#Tp 1'b0;
850 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
851 38 mohor
    end
852 39 mohor
  else
853
    begin
854
      // Switching between two stages depends on enable signals
855 105 mohor
      case ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})  // synopsys parallel_case
856 82 mohor
        5'b00_01_0, 5'b00_11_0 :
857 39 mohor
          begin
858
            MasterWbTX <=#Tp 1'b0;  // idle and master write is needed (data write to rx buffer)
859
            MasterWbRX <=#Tp 1'b1;
860
            m_wb_adr_o <=#Tp RxPointer;
861
            m_wb_cyc_o <=#Tp 1'b1;
862
            m_wb_stb_o <=#Tp 1'b1;
863
            m_wb_we_o  <=#Tp 1'b1;
864 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
865 39 mohor
          end
866 82 mohor
        5'b00_10_0, 5'b00_10_1 :
867 39 mohor
          begin
868
            MasterWbTX <=#Tp 1'b1;  // idle and master read is needed (data read from tx buffer)
869
            MasterWbRX <=#Tp 1'b0;
870
            m_wb_adr_o <=#Tp TxPointer;
871
            m_wb_cyc_o <=#Tp 1'b1;
872
            m_wb_stb_o <=#Tp 1'b1;
873
            m_wb_we_o  <=#Tp 1'b0;
874 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
875 39 mohor
          end
876
        5'b10_10_1 :
877
          begin
878
            MasterWbTX <=#Tp 1'b1;  // master read and master read is needed (data read from tx buffer)
879
            MasterWbRX <=#Tp 1'b0;
880
            m_wb_adr_o <=#Tp TxPointer;
881
            m_wb_cyc_o <=#Tp 1'b1;
882
            m_wb_stb_o <=#Tp 1'b1;
883
            m_wb_we_o  <=#Tp 1'b0;
884 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
885 39 mohor
          end
886
        5'b01_01_1 :
887
          begin
888
            MasterWbTX <=#Tp 1'b0;  // master write and master write is needed (data write to rx buffer)
889
            MasterWbRX <=#Tp 1'b1;
890
            m_wb_adr_o <=#Tp RxPointer;
891
            m_wb_we_o  <=#Tp 1'b1;
892 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
893 39 mohor
          end
894 82 mohor
        5'b10_01_1, 5'b10_11_1 :
895 39 mohor
          begin
896
            MasterWbTX <=#Tp 1'b0;  // master read and master write is needed (data write to rx buffer)
897
            MasterWbRX <=#Tp 1'b1;
898
            m_wb_adr_o <=#Tp RxPointer;
899
            m_wb_we_o  <=#Tp 1'b1;
900 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
901 39 mohor
          end
902 82 mohor
        5'b01_10_1, 5'b01_11_1 :
903 39 mohor
          begin
904
            MasterWbTX <=#Tp 1'b1;  // master write and master read is needed (data read from tx buffer)
905
            MasterWbRX <=#Tp 1'b0;
906
            m_wb_adr_o <=#Tp TxPointer;
907
            m_wb_we_o  <=#Tp 1'b0;
908 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
909 39 mohor
          end
910 82 mohor
        5'b10_00_1, 5'b01_00_1 :
911 39 mohor
          begin
912
            MasterWbTX <=#Tp 1'b0;  // whatever and no master read or write is needed (ack or err comes finishing previous access)
913
            MasterWbRX <=#Tp 1'b0;
914
            m_wb_cyc_o <=#Tp 1'b0;
915
            m_wb_stb_o <=#Tp 1'b0;
916
          end
917 82 mohor
        default:                            // Don't touch
918
          begin
919
            MasterWbTX <=#Tp MasterWbTX;
920
            MasterWbRX <=#Tp MasterWbRX;
921
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
922
            m_wb_stb_o <=#Tp m_wb_stb_o;
923 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
924 82 mohor
          end
925 39 mohor
      endcase
926
    end
927 38 mohor
end
928
 
929 39 mohor
wire TxFifoClear;
930 96 mohor
wire [31:0] tx_fifo_dat_i;
931
 
932 39 mohor
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
933 38 mohor
 
934 96 mohor
reg  [23:16] LatchedData;
935
wire [23:16] TempData;
936
 
937
always @ (posedge WB_CLK_I or posedge Reset)
938
begin
939
  if(Reset)
940
    LatchedData[23:16] <=#Tp 0;
941
  else
942
  if(MasterWbTX & m_wb_ack_i & m_wb_sel_o[2])
943
    LatchedData[23:16] <=#Tp m_wb_dat_i[23:16];
944
end
945
 
946
assign TempData[23:16] = m_wb_sel_o[2]? m_wb_dat_i[23:16] : LatchedData[23:16];
947
 
948
assign tx_fifo_dat_i[31:0] = {m_wb_dat_i[31:24], TempData[23:16], m_wb_dat_i[15:8], m_wb_dat_i[7:0]};
949
 
950
 
951 40 mohor
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
952 96 mohor
tx_fifo ( .data_in(tx_fifo_dat_i),                          .data_out(TxData_wb),
953
          .clk(WB_CLK_I),                                   .reset(Reset),
954
          .write(MasterWbTX & m_wb_ack_i & m_wb_sel_o[0]),  .read(ReadTxDataFromFifo_wb),
955
          .clear(TxFifoClear),                              .full(TxBufferFull),
956
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
957 105 mohor
          .empty(TxBufferEmpty),                            .cnt()
958 96 mohor
        );
959 39 mohor
 
960
 
961
reg StartOccured;
962
reg TxStartFrm_sync1;
963
reg TxStartFrm_sync2;
964
reg TxStartFrm_syncb1;
965
reg TxStartFrm_syncb2;
966
 
967
 
968
 
969
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
970 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
971 38 mohor
begin
972 40 mohor
  if(Reset)
973 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
974 38 mohor
  else
975 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
976
    TxStartFrm_wb <=#Tp 1'b1;
977 38 mohor
  else
978 39 mohor
  if(TxStartFrm_syncb2)
979
    TxStartFrm_wb <=#Tp 1'b0;
980 38 mohor
end
981
 
982 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
983 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
984 38 mohor
begin
985 40 mohor
  if(Reset)
986 39 mohor
    StartOccured <=#Tp 1'b0;
987 38 mohor
  else
988 39 mohor
  if(TxStartFrm_wb)
989
    StartOccured <=#Tp 1'b1;
990 38 mohor
  else
991 39 mohor
  if(ResetTxBDReady)
992
    StartOccured <=#Tp 1'b0;
993 38 mohor
end
994
 
995 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
996 40 mohor
always @ (posedge MTxClk or posedge Reset)
997 39 mohor
begin
998 40 mohor
  if(Reset)
999 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1000
  else
1001
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1002
end
1003 38 mohor
 
1004 40 mohor
always @ (posedge MTxClk or posedge Reset)
1005 39 mohor
begin
1006 40 mohor
  if(Reset)
1007 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1008
  else
1009
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1010
end
1011
 
1012 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1013 38 mohor
begin
1014 40 mohor
  if(Reset)
1015 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1016 38 mohor
  else
1017 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1018 38 mohor
end
1019
 
1020 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1021 38 mohor
begin
1022 40 mohor
  if(Reset)
1023 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1024 38 mohor
  else
1025 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1026
end
1027
 
1028 40 mohor
always @ (posedge MTxClk or posedge Reset)
1029 39 mohor
begin
1030 40 mohor
  if(Reset)
1031 39 mohor
    TxStartFrm <=#Tp 1'b0;
1032 38 mohor
  else
1033 39 mohor
  if(TxStartFrm_sync2)
1034 61 mohor
    TxStartFrm <=#Tp 1'b1;
1035 39 mohor
  else
1036 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1037 39 mohor
    TxStartFrm <=#Tp 1'b0;
1038 38 mohor
end
1039 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1040 38 mohor
 
1041
 
1042 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1043 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1044 38 mohor
begin
1045 40 mohor
  if(Reset)
1046 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1047 38 mohor
  else
1048 39 mohor
  if(TxLengthLt4 & TxBufferAlmostEmpty & TxUsedData)
1049
    TxEndFrm_wb <=#Tp 1'b1;
1050 38 mohor
  else
1051 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1052
    TxEndFrm_wb <=#Tp 1'b0;
1053 38 mohor
end
1054
 
1055
 
1056
// Marks which bytes are valid within the word.
1057 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1058 38 mohor
 
1059 39 mohor
reg LatchValidBytes;
1060
reg LatchValidBytes_q;
1061 38 mohor
 
1062 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1063 38 mohor
begin
1064 40 mohor
  if(Reset)
1065 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1066 38 mohor
  else
1067 39 mohor
  if(TxLengthLt4 & TxBDReady)
1068
    LatchValidBytes <=#Tp 1'b1;
1069 38 mohor
  else
1070 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1071 38 mohor
end
1072
 
1073 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1074 38 mohor
begin
1075 40 mohor
  if(Reset)
1076 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1077 38 mohor
  else
1078 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1079 38 mohor
end
1080
 
1081
 
1082 39 mohor
// Latching valid bytes
1083 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1084 38 mohor
begin
1085 40 mohor
  if(Reset)
1086 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1087 38 mohor
  else
1088 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1089
    TxValidBytesLatched <=#Tp TxValidBytes;
1090
  else
1091
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1092
    TxValidBytesLatched <=#Tp 2'h0;
1093 38 mohor
end
1094
 
1095
 
1096
assign TxIRQEn          = TxStatus[14];
1097 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1098
assign PerPacketPad     = TxStatus[12];
1099
assign PerPacketCrcEn   = TxStatus[11];
1100 38 mohor
 
1101
 
1102 77 mohor
assign RxIRQEn         = RxStatus[14];
1103 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1104 38 mohor
 
1105
 
1106
// Temporary Tx and Rx buffer descriptor address 
1107 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1108 38 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum)       | // Using first Rx BD
1109 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1110 38 mohor
 
1111
 
1112
// Latching Tx buffer descriptor address
1113 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1114 38 mohor
begin
1115 40 mohor
  if(Reset)
1116 38 mohor
    TxBDAddress <=#Tp 8'h0;
1117
  else
1118
  if(TxStatusWrite)
1119
    TxBDAddress <=#Tp TempTxBDAddress;
1120
end
1121
 
1122
 
1123
// Latching Rx buffer descriptor address
1124 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1125 38 mohor
begin
1126 40 mohor
  if(Reset)
1127 38 mohor
    RxBDAddress <=#Tp 8'h0;
1128
  else
1129 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1130 38 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0];
1131
  else
1132
  if(RxStatusWrite)
1133
    RxBDAddress <=#Tp TempRxBDAddress;
1134
end
1135
 
1136 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1137 38 mohor
 
1138 60 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
1139
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1140 38 mohor
 
1141 60 mohor
 
1142 38 mohor
// Signals used for various purposes
1143 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1144 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1145
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1146 105 mohor
assign TxRetryPulse_q = TxRetry_wb_q & ~TxRetry_wb_q2;
1147
assign TxDonePulse_q  = TxDone_wb_q  & ~TxDone_wb_q2;
1148
assign TxAbortPulse_q = TxAbort_wb_q & ~TxAbort_wb_q2;
1149 38 mohor
 
1150
 
1151 91 mohor
assign TPauseRq = 0;
1152
assign TxPauseTV[15:0] = TxLength[15:0];
1153 38 mohor
 
1154
 
1155 39 mohor
// Generating delayed signals
1156 40 mohor
always @ (posedge MTxClk or posedge Reset)
1157 38 mohor
begin
1158 40 mohor
  if(Reset)
1159 39 mohor
    begin
1160
      TxAbort_q      <=#Tp 1'b0;
1161
      TxRetry_q      <=#Tp 1'b0;
1162
      TxUsedData_q   <=#Tp 1'b0;
1163
    end
1164 38 mohor
  else
1165 39 mohor
    begin
1166
      TxAbort_q      <=#Tp TxAbort;
1167
      TxRetry_q      <=#Tp TxRetry;
1168
      TxUsedData_q   <=#Tp TxUsedData;
1169
    end
1170 38 mohor
end
1171
 
1172
// Generating delayed signals
1173 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1174 38 mohor
begin
1175 40 mohor
  if(Reset)
1176 38 mohor
    begin
1177 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1178
      TxAbort_wb_q  <=#Tp 1'b0;
1179 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1180 105 mohor
      TxDone_wb_q2  <=#Tp 1'b0;
1181
      TxAbort_wb_q2 <=#Tp 1'b0;
1182
      TxRetry_wb_q2 <=#Tp 1'b0;
1183 38 mohor
    end
1184
  else
1185
    begin
1186 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1187
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1188 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1189 105 mohor
      TxDone_wb_q2  <=#Tp TxDone_wb_q;
1190
      TxAbort_wb_q2 <=#Tp TxAbort_wb_q;
1191
      TxRetry_wb_q2 <=#Tp TxRetry_wb_q;
1192 38 mohor
    end
1193
end
1194
 
1195
 
1196
// Sinchronizing and evaluating tx data
1197 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1198
assign SetGotData = (TxStartFrm_wb); // igor namesto zgornje
1199 38 mohor
 
1200
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1201 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1202
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1203 38 mohor
 
1204
 
1205
// Indication of the last word
1206 40 mohor
always @ (posedge MTxClk or posedge Reset)
1207 38 mohor
begin
1208 40 mohor
  if(Reset)
1209 38 mohor
    LastWord <=#Tp 1'b0;
1210
  else
1211
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1212
    LastWord <=#Tp 1'b0;
1213
  else
1214
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1215 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1216 38 mohor
end
1217
 
1218
 
1219
// Tx end frame generation
1220 40 mohor
always @ (posedge MTxClk or posedge Reset)
1221 38 mohor
begin
1222 40 mohor
  if(Reset)
1223 38 mohor
    TxEndFrm <=#Tp 1'b0;
1224
  else
1225 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1226 38 mohor
    TxEndFrm <=#Tp 1'b0;
1227
  else
1228
  if(Flop & LastWord)
1229
    begin
1230 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1231 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1232
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1233
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1234
 
1235
        default : TxEndFrm <=#Tp 1'b0;
1236
      endcase
1237
    end
1238
end
1239
 
1240
 
1241
// Tx data selection (latching)
1242 40 mohor
always @ (posedge MTxClk or posedge Reset)
1243 38 mohor
begin
1244 40 mohor
  if(Reset)
1245 96 mohor
    TxData <=#Tp 0;
1246 38 mohor
  else
1247 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1248 105 mohor
    case(TxPointerLatched)  // synopsys parallel_case
1249 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1250
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1251
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1252
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1253
    endcase
1254 38 mohor
  else
1255 96 mohor
  if(TxStartFrm & TxUsedData & TxPointerLatched==2'h3)
1256
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1257
  else
1258 38 mohor
  if(TxUsedData & Flop)
1259
    begin
1260 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1261 82 mohor
 
1262
        1 : TxData <=#Tp TxDataLatched[23:16];
1263
        2 : TxData <=#Tp TxDataLatched[15:8];
1264
        3 : TxData <=#Tp TxDataLatched[7:0];
1265 38 mohor
      endcase
1266
    end
1267
end
1268
 
1269
 
1270
// Latching tx data
1271 40 mohor
always @ (posedge MTxClk or posedge Reset)
1272 38 mohor
begin
1273 40 mohor
  if(Reset)
1274 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1275
  else
1276 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1277 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1278 38 mohor
end
1279
 
1280
 
1281
// Tx under run
1282 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1283 38 mohor
begin
1284 40 mohor
  if(Reset)
1285 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1286 38 mohor
  else
1287 39 mohor
  if(TxAbortPulse)
1288 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1289
  else
1290
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1291
    TxUnderRun_wb <=#Tp 1'b1;
1292
end
1293
 
1294
 
1295
// Tx under run
1296
always @ (posedge MTxClk or posedge Reset)
1297
begin
1298
  if(Reset)
1299 54 billditt
    TxUnderRun <=#Tp 1'b0;
1300 43 mohor
  else
1301 60 mohor
  if(TxUnderRun_wb)
1302 38 mohor
    TxUnderRun <=#Tp 1'b1;
1303 60 mohor
  else
1304
  if(BlockingTxStatusWrite)
1305
    TxUnderRun <=#Tp 1'b0;
1306 38 mohor
end
1307
 
1308
 
1309
// Tx Byte counter
1310 40 mohor
always @ (posedge MTxClk or posedge Reset)
1311 38 mohor
begin
1312 40 mohor
  if(Reset)
1313 38 mohor
    TxByteCnt <=#Tp 2'h0;
1314
  else
1315
  if(TxAbort_q | TxRetry_q)
1316
    TxByteCnt <=#Tp 2'h0;
1317
  else
1318
  if(TxStartFrm & ~TxUsedData)
1319 105 mohor
    case(TxPointerLatched)  // synopsys parallel_case
1320 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1321
      2'h1 : TxByteCnt <=#Tp 2'h2;
1322
      2'h2 : TxByteCnt <=#Tp 2'h3;
1323
      2'h3 : TxByteCnt <=#Tp 2'h0;
1324
    endcase
1325 38 mohor
  else
1326
  if(TxUsedData & Flop)
1327 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1328 38 mohor
end
1329
 
1330
 
1331 39 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1332
reg ReadTxDataFromFifo_sync1;
1333
reg ReadTxDataFromFifo_sync2;
1334
reg ReadTxDataFromFifo_sync3;
1335
reg ReadTxDataFromFifo_syncb1;
1336
reg ReadTxDataFromFifo_syncb2;
1337
 
1338
 
1339 40 mohor
always @ (posedge MTxClk or posedge Reset)
1340 38 mohor
begin
1341 40 mohor
  if(Reset)
1342 39 mohor
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1343 38 mohor
  else
1344 39 mohor
  if(ReadTxDataFromFifo_syncb2)
1345
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1346 38 mohor
  else
1347 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1348 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1349 38 mohor
end
1350
 
1351 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1352 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1353 38 mohor
begin
1354 40 mohor
  if(Reset)
1355 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1356 38 mohor
  else
1357 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1358
end
1359 38 mohor
 
1360 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1361 38 mohor
begin
1362 40 mohor
  if(Reset)
1363 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1364 38 mohor
  else
1365 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1366 38 mohor
end
1367
 
1368 40 mohor
always @ (posedge MTxClk or posedge Reset)
1369 38 mohor
begin
1370 40 mohor
  if(Reset)
1371 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1372 38 mohor
  else
1373 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1374 38 mohor
end
1375
 
1376 40 mohor
always @ (posedge MTxClk or posedge Reset)
1377 38 mohor
begin
1378 40 mohor
  if(Reset)
1379 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1380 38 mohor
  else
1381 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1382 38 mohor
end
1383
 
1384 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1385 38 mohor
begin
1386 40 mohor
  if(Reset)
1387 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1388 38 mohor
  else
1389 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1390 38 mohor
end
1391
 
1392 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1393
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1394 38 mohor
 
1395
 
1396 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1397 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1398 38 mohor
begin
1399 40 mohor
  if(Reset)
1400 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1401 38 mohor
  else
1402 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1403 38 mohor
end
1404
 
1405 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1406 38 mohor
begin
1407 40 mohor
  if(Reset)
1408 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1409 38 mohor
  else
1410 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1411 38 mohor
end
1412
 
1413
 
1414 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1415 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1416 38 mohor
begin
1417 40 mohor
  if(Reset)
1418 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1419 38 mohor
  else
1420 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1421 38 mohor
end
1422
 
1423 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1424 38 mohor
begin
1425 40 mohor
  if(Reset)
1426 39 mohor
    TxDone_wb <=#Tp 1'b0;
1427 38 mohor
  else
1428 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1429 38 mohor
end
1430
 
1431 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1432 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1433 38 mohor
begin
1434 40 mohor
  if(Reset)
1435 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1436 38 mohor
  else
1437 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1438 38 mohor
end
1439
 
1440 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1441 38 mohor
begin
1442 40 mohor
  if(Reset)
1443 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1444
  else
1445 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1446 38 mohor
end
1447
 
1448
 
1449 90 mohor
assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1450 39 mohor
 
1451 40 mohor
// Reading the Rx buffer descriptor
1452
always @ (posedge WB_CLK_I or posedge Reset)
1453
begin
1454
  if(Reset)
1455
    RxBDRead <=#Tp 1'b1;
1456
  else
1457 90 mohor
  if(StartRxBDRead & ~RxBDReady)
1458 40 mohor
    RxBDRead <=#Tp 1'b1;
1459
  else
1460
  if(RxBDReady)
1461
    RxBDRead <=#Tp 1'b0;
1462
end
1463 39 mohor
 
1464
 
1465 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1466
// written to the previous one.
1467
 
1468
// Latching READY status of the Rx buffer descriptor
1469 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1470 38 mohor
begin
1471 40 mohor
  if(Reset)
1472 38 mohor
    RxBDReady <=#Tp 1'b0;
1473
  else
1474 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1475
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1476 38 mohor
  else
1477 61 mohor
  if(ShiftEnded | RxAbort)
1478 38 mohor
    RxBDReady <=#Tp 1'b0;
1479
end
1480
 
1481 40 mohor
// Latching Rx buffer descriptor status
1482
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1483
always @ (posedge WB_CLK_I or posedge Reset)
1484 38 mohor
begin
1485 40 mohor
  if(Reset)
1486 60 mohor
    RxStatus <=#Tp 2'h0;
1487 38 mohor
  else
1488 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1489 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1490 38 mohor
end
1491
 
1492
 
1493
 
1494
 
1495 40 mohor
// Reading Rx BD pointer
1496
 
1497
 
1498
assign StartRxPointerRead = RxBDRead & RxBDReady;
1499
 
1500
// Reading Tx BD Pointer
1501
always @ (posedge WB_CLK_I or posedge Reset)
1502 38 mohor
begin
1503 40 mohor
  if(Reset)
1504
    RxPointerRead <=#Tp 1'b0;
1505 38 mohor
  else
1506 40 mohor
  if(StartRxPointerRead)
1507
    RxPointerRead <=#Tp 1'b1;
1508 38 mohor
  else
1509 40 mohor
  if(RxEn_q)
1510
    RxPointerRead <=#Tp 1'b0;
1511 38 mohor
end
1512
 
1513 40 mohor
reg BlockingIncrementRxPointer;
1514
//Latching Rx buffer pointer from buffer descriptor;
1515
always @ (posedge WB_CLK_I or posedge Reset)
1516
begin
1517
  if(Reset)
1518
    RxPointer <=#Tp 32'h0;
1519
  else
1520
  if(RxEn & RxEn_q & RxPointerRead)
1521 96 mohor
    RxPointer <=#Tp {ram_do[31:2], 2'h0};
1522 40 mohor
  else
1523
  if(MasterWbRX & ~BlockingIncrementRxPointer)
1524 96 mohor
      RxPointer <=#Tp RxPointer + 3'h4; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1525 40 mohor
end
1526 38 mohor
 
1527
 
1528 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1529 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1530
begin
1531
  if(Reset)
1532 96 mohor
    RxPointerLatched[1:0] <=#Tp 0;
1533
  else
1534
  if(MasterWbRX & m_wb_ack_i)                 // After first write all m_wb_sel_tmp_rx are active
1535
    RxPointerLatched[1:0] <=#Tp 0;
1536
  else
1537
  if(RxEn & RxEn_q & RxPointerRead)
1538
    RxPointerLatched[1:0] <=#Tp ram_do[1:0];
1539
end
1540
 
1541
 
1542
always @ (RxPointerLatched)
1543
begin
1544 105 mohor
  case(RxPointerLatched[1:0])  // synopsys parallel_case
1545 96 mohor
    2'h0 : m_wb_sel_tmp_rx[3:0] = 4'hf;
1546
    2'h1 : m_wb_sel_tmp_rx[3:0] = 4'h7;
1547
    2'h2 : m_wb_sel_tmp_rx[3:0] = 4'h3;
1548
    2'h3 : m_wb_sel_tmp_rx[3:0] = 4'h1;
1549
  endcase
1550
end
1551
 
1552
 
1553
always @ (posedge WB_CLK_I or posedge Reset)
1554
begin
1555
  if(Reset)
1556 40 mohor
    BlockingIncrementRxPointer <=#Tp 0;
1557
  else
1558
  if(MasterAccessFinished)
1559
    BlockingIncrementRxPointer <=#Tp 0;
1560
  else
1561
  if(MasterWbRX)
1562
    BlockingIncrementRxPointer <=#Tp 1'b1;
1563
end
1564
 
1565 38 mohor
 
1566 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1567 38 mohor
begin
1568 40 mohor
  if(Reset)
1569
    RxEn_needed <=#Tp 1'b0;
1570 38 mohor
  else
1571 40 mohor
  if(~RxBDReady & r_RxEn & WbEn & ~WbEn_q)
1572
    RxEn_needed <=#Tp 1'b1;
1573 38 mohor
  else
1574 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1575
    RxEn_needed <=#Tp 1'b0;
1576 38 mohor
end
1577
 
1578
 
1579 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1580
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1581 38 mohor
 
1582 42 mohor
reg RxStatusWriteLatched;
1583
reg RxStatusWrite_rck;
1584
 
1585
always @ (posedge WB_CLK_I or posedge Reset)
1586
begin
1587
  if(Reset)
1588
    RxStatusWriteLatched <=#Tp 1'b0;
1589
  else
1590 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
1591 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
1592
  else
1593
  if(RxStatusWrite_rck)
1594
    RxStatusWriteLatched <=#Tp 1'b0;
1595
end
1596
 
1597
 
1598
always @ (posedge MRxClk or posedge Reset)
1599
begin
1600
  if(Reset)
1601
    RxStatusWrite_rck <=#Tp 1'b0;
1602
  else
1603 87 mohor
  if(RxStatusWriteLatched)
1604
    RxStatusWrite_rck <=#Tp 1'b1;
1605
  else
1606
    RxStatusWrite_rck <=#Tp 1'b0;
1607 42 mohor
end
1608
 
1609
 
1610 40 mohor
reg RxEnableWindow;
1611 38 mohor
 
1612
// Indicating that last byte is being reveived
1613 40 mohor
always @ (posedge MRxClk or posedge Reset)
1614 38 mohor
begin
1615 40 mohor
  if(Reset)
1616 38 mohor
    LastByteIn <=#Tp 1'b0;
1617
  else
1618 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1619 38 mohor
    LastByteIn <=#Tp 1'b0;
1620
  else
1621 40 mohor
  if(RxValid & RxBDReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1622 38 mohor
    LastByteIn <=#Tp 1'b1;
1623
end
1624
 
1625 40 mohor
reg ShiftEnded_tck;
1626
reg ShiftEndedSync1;
1627
reg ShiftEndedSync2;
1628
wire StartShiftWillEnd;
1629 96 mohor
//assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1630
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1631 38 mohor
 
1632
// Indicating that data reception will end
1633 40 mohor
always @ (posedge MRxClk or posedge Reset)
1634 38 mohor
begin
1635 40 mohor
  if(Reset)
1636 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1637
  else
1638 40 mohor
  if(ShiftEnded_tck | RxAbort)
1639 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1640
  else
1641 40 mohor
  if(StartShiftWillEnd)
1642 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1643
end
1644
 
1645
 
1646 40 mohor
 
1647 38 mohor
// Receive byte counter
1648 40 mohor
always @ (posedge MRxClk or posedge Reset)
1649 38 mohor
begin
1650 40 mohor
  if(Reset)
1651 38 mohor
    RxByteCnt <=#Tp 2'h0;
1652
  else
1653 40 mohor
  if(ShiftEnded_tck | RxAbort)
1654 38 mohor
    RxByteCnt <=#Tp 2'h0;
1655 97 lampret
  else
1656 96 mohor
  if(RxValid & RxStartFrm & RxBDReady)
1657 105 mohor
    case(RxPointerLatched)  // synopsys parallel_case
1658 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
1659
      2'h1 : RxByteCnt <=#Tp 2'h2;
1660
      2'h2 : RxByteCnt <=#Tp 2'h3;
1661
      2'h3 : RxByteCnt <=#Tp 2'h0;
1662
    endcase
1663 38 mohor
  else
1664 96 mohor
  if(RxValid & RxEnableWindow & RxBDReady | LastByteIn)
1665 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
1666 38 mohor
end
1667
 
1668
 
1669
// Indicates how many bytes are valid within the last word
1670 40 mohor
always @ (posedge MRxClk or posedge Reset)
1671 38 mohor
begin
1672 40 mohor
  if(Reset)
1673 38 mohor
    RxValidBytes <=#Tp 2'h1;
1674
  else
1675 96 mohor
  if(RxValid & RxStartFrm)
1676 105 mohor
    case(RxPointerLatched)  // synopsys parallel_case
1677 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
1678
      2'h1 : RxValidBytes <=#Tp 2'h2;
1679
      2'h2 : RxValidBytes <=#Tp 2'h3;
1680
      2'h3 : RxValidBytes <=#Tp 2'h0;
1681
    endcase
1682 38 mohor
  else
1683 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
1684 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
1685
end
1686
 
1687
 
1688 40 mohor
always @ (posedge MRxClk or posedge Reset)
1689 38 mohor
begin
1690 40 mohor
  if(Reset)
1691
    RxDataLatched1       <=#Tp 24'h0;
1692 38 mohor
  else
1693 96 mohor
  if(RxValid & RxBDReady & ~LastByteIn)
1694
    if(RxStartFrm)
1695 40 mohor
    begin
1696 96 mohor
      case(RxPointerLatched)     // synopsys parallel_case
1697
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1698
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1699
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1700
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1701
      endcase
1702
    end
1703
    else if (RxEnableWindow)
1704
    begin
1705 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
1706 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1707
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1708
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1709 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1710
      endcase
1711
    end
1712 38 mohor
end
1713
 
1714 40 mohor
wire SetWriteRxDataToFifo;
1715 38 mohor
 
1716 40 mohor
// Assembling data that will be written to the rx_fifo
1717
always @ (posedge MRxClk or posedge Reset)
1718 38 mohor
begin
1719 40 mohor
  if(Reset)
1720
    RxDataLatched2 <=#Tp 32'h0;
1721 38 mohor
  else
1722 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
1723 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
1724 38 mohor
  else
1725 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
1726 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
1727 96 mohor
//      0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],  RxData};       // Big Endian Byte Ordering
1728
//      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
1729
//      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
1730
//      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
1731 82 mohor
 
1732
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
1733
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
1734
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
1735 40 mohor
    endcase
1736 38 mohor
end
1737
 
1738
 
1739 40 mohor
reg WriteRxDataToFifoSync1;
1740
reg WriteRxDataToFifoSync2;
1741 38 mohor
 
1742
 
1743 40 mohor
// Indicating start of the reception process
1744 96 mohor
//assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
1745
assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (RxValid & RxBDReady & RxStartFrm & (&RxPointerLatched)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
1746 38 mohor
 
1747 40 mohor
always @ (posedge MRxClk or posedge Reset)
1748 38 mohor
begin
1749 40 mohor
  if(Reset)
1750
    WriteRxDataToFifo <=#Tp 1'b0;
1751 38 mohor
  else
1752 40 mohor
  if(SetWriteRxDataToFifo & ~RxAbort)
1753
    WriteRxDataToFifo <=#Tp 1'b1;
1754 38 mohor
  else
1755 40 mohor
  if(WriteRxDataToFifoSync1 | RxAbort)
1756
    WriteRxDataToFifo <=#Tp 1'b0;
1757 38 mohor
end
1758
 
1759
 
1760
 
1761 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1762
begin
1763
  if(Reset)
1764
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
1765
  else
1766
  if(WriteRxDataToFifo)
1767
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
1768
  else
1769
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
1770
end
1771 38 mohor
 
1772 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1773 38 mohor
begin
1774 40 mohor
  if(Reset)
1775
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
1776 38 mohor
  else
1777 40 mohor
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
1778 38 mohor
end
1779
 
1780 40 mohor
wire WriteRxDataToFifo_wb;
1781
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync1 & ~WriteRxDataToFifoSync2;
1782 38 mohor
 
1783 40 mohor
reg RxAbortSync1;
1784
reg RxAbortSync2;
1785
reg RxAbortSyncb1;
1786
reg RxAbortSyncb2;
1787
 
1788 90 mohor
reg LatchedRxStartFrm;
1789
reg SyncRxStartFrm;
1790
reg SyncRxStartFrm_q;
1791
wire RxFifoReset;
1792 40 mohor
 
1793 90 mohor
always @ (posedge MRxClk or posedge Reset)
1794
begin
1795
  if(Reset)
1796
    LatchedRxStartFrm <=#Tp 0;
1797
  else
1798
  if(RxStartFrm & ~SyncRxStartFrm)
1799
    LatchedRxStartFrm <=#Tp 1;
1800
  else
1801
  if(SyncRxStartFrm)
1802
    LatchedRxStartFrm <=#Tp 0;
1803
end
1804
 
1805
 
1806
always @ (posedge WB_CLK_I or posedge Reset)
1807
begin
1808
  if(Reset)
1809
    SyncRxStartFrm <=#Tp 0;
1810
  else
1811
  if(LatchedRxStartFrm)
1812
    SyncRxStartFrm <=#Tp 1;
1813
  else
1814
    SyncRxStartFrm <=#Tp 0;
1815
end
1816
 
1817
 
1818
always @ (posedge WB_CLK_I or posedge Reset)
1819
begin
1820
  if(Reset)
1821
    SyncRxStartFrm_q <=#Tp 0;
1822
  else
1823
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
1824
end
1825
 
1826
 
1827
assign RxFifoReset = SyncRxStartFrm & ~SyncRxStartFrm_q;
1828
 
1829
 
1830 40 mohor
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
1831 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
1832
         .clk(WB_CLK_I),                                .reset(Reset),
1833
         .write(WriteRxDataToFifo_wb),                  .read(MasterWbRX & m_wb_ack_i),
1834 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
1835 88 mohor
         .almost_full(RxBufferAlmostFull),              .almost_empty(RxBufferAlmostEmpty),
1836 105 mohor
         .empty(RxBufferEmpty),                         .cnt()
1837 88 mohor
        );
1838 40 mohor
 
1839
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
1840
 
1841
 
1842
 
1843
// Generation of the end-of-frame signal
1844
always @ (posedge MRxClk or posedge Reset)
1845 38 mohor
begin
1846 40 mohor
  if(Reset)
1847
    ShiftEnded_tck <=#Tp 1'b0;
1848 38 mohor
  else
1849 90 mohor
  if(SetWriteRxDataToFifo & StartShiftWillEnd & ~RxAbort & ~ShiftEnded_tck)
1850 40 mohor
    ShiftEnded_tck <=#Tp 1'b1;
1851 38 mohor
  else
1852 90 mohor
  if(ShiftEnded | RxAbort)
1853 40 mohor
    ShiftEnded_tck <=#Tp 1'b0;
1854 38 mohor
end
1855
 
1856 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1857
begin
1858
  if(Reset)
1859
    ShiftEndedSync1 <=#Tp 1'b0;
1860
  else
1861
    ShiftEndedSync1 <=#Tp ShiftEnded_tck;
1862
end
1863 38 mohor
 
1864 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1865 38 mohor
begin
1866 40 mohor
  if(Reset)
1867
    ShiftEndedSync2 <=#Tp 1'b0;
1868 38 mohor
  else
1869 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
1870 40 mohor
end
1871 38 mohor
 
1872
 
1873 40 mohor
// Generation of the end-of-frame signal
1874
always @ (posedge WB_CLK_I or posedge Reset)
1875 38 mohor
begin
1876 40 mohor
  if(Reset)
1877
    ShiftEnded <=#Tp 1'b0;
1878 38 mohor
  else
1879 90 mohor
  if(ShiftEndedSync2 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
1880 40 mohor
    ShiftEnded <=#Tp 1'b1;
1881 38 mohor
  else
1882 40 mohor
  if(RxStatusWrite)
1883
    ShiftEnded <=#Tp 1'b0;
1884 38 mohor
end
1885
 
1886
 
1887 40 mohor
// Generation of the end-of-frame signal
1888
always @ (posedge MRxClk or posedge Reset)
1889 38 mohor
begin
1890 40 mohor
  if(Reset)
1891
    RxEnableWindow <=#Tp 1'b0;
1892 38 mohor
  else
1893 40 mohor
  if(RxStartFrm)
1894
    RxEnableWindow <=#Tp 1'b1;
1895 38 mohor
  else
1896 40 mohor
  if(RxEndFrm | RxAbort)
1897
    RxEnableWindow <=#Tp 1'b0;
1898 38 mohor
end
1899
 
1900
 
1901 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1902 38 mohor
begin
1903 40 mohor
  if(Reset)
1904
    RxAbortSync1 <=#Tp 1'b0;
1905 38 mohor
  else
1906 40 mohor
    RxAbortSync1 <=#Tp RxAbort;
1907
end
1908
 
1909
always @ (posedge WB_CLK_I or posedge Reset)
1910
begin
1911
  if(Reset)
1912
    RxAbortSync2 <=#Tp 1'b0;
1913 38 mohor
  else
1914 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
1915 38 mohor
end
1916
 
1917 40 mohor
always @ (posedge MRxClk or posedge Reset)
1918
begin
1919
  if(Reset)
1920
    RxAbortSyncb1 <=#Tp 1'b0;
1921
  else
1922
    RxAbortSyncb1 <=#Tp RxAbortSync2;
1923
end
1924 38 mohor
 
1925 40 mohor
always @ (posedge MRxClk or posedge Reset)
1926 38 mohor
begin
1927 40 mohor
  if(Reset)
1928
    RxAbortSyncb2 <=#Tp 1'b0;
1929 38 mohor
  else
1930 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
1931 38 mohor
end
1932
 
1933
 
1934 64 mohor
always @ (posedge MRxClk or posedge Reset)
1935
begin
1936
  if(Reset)
1937
    RxAbortLatched <=#Tp 1'b0;
1938
  else
1939
  if(RxAbort)
1940
    RxAbortLatched <=#Tp 1'b1;
1941
  else
1942
  if(RxStartFrm)
1943
    RxAbortLatched <=#Tp 1'b0;
1944
end
1945 40 mohor
 
1946
 
1947 42 mohor
reg LoadStatusBlocked;
1948 64 mohor
 
1949 42 mohor
always @ (posedge MRxClk or posedge Reset)
1950
begin
1951
  if(Reset)
1952
    LoadStatusBlocked <=#Tp 1'b0;
1953
  else
1954 64 mohor
  if(LoadRxStatus & ~RxAbortLatched)
1955 42 mohor
    LoadStatusBlocked <=#Tp 1'b1;
1956
  else
1957 87 mohor
  if(RxStatusWrite_rck | RxStartFrm)
1958 42 mohor
    LoadStatusBlocked <=#Tp 1'b0;
1959
end
1960
 
1961
// LatchedRxLength[15:0]
1962
always @ (posedge MRxClk or posedge Reset)
1963
begin
1964
  if(Reset)
1965
    LatchedRxLength[15:0] <=#Tp 16'h0;
1966
  else
1967 64 mohor
  if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
1968 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
1969
end
1970
 
1971
 
1972 60 mohor
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
1973 42 mohor
 
1974
always @ (posedge MRxClk or posedge Reset)
1975
begin
1976
  if(Reset)
1977
    RxStatusInLatched <=#Tp 'h0;
1978
  else
1979 64 mohor
  if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
1980 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
1981
end
1982
 
1983
 
1984 60 mohor
// Rx overrun
1985
always @ (posedge WB_CLK_I or posedge Reset)
1986
begin
1987
  if(Reset)
1988
    RxOverrun <=#Tp 1'b0;
1989
  else
1990
  if(RxStatusWrite)
1991
    RxOverrun <=#Tp 1'b0;
1992
  else
1993
  if(RxBufferFull & WriteRxDataToFifo_wb)
1994
    RxOverrun <=#Tp 1'b1;
1995
end
1996 48 mohor
 
1997 77 mohor
 
1998
 
1999
wire TxError;
2000
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2001
 
2002
wire RxError;
2003
assign RxError = |RxStatusInLatched[6:0];
2004
 
2005
// Tx Done Interrupt
2006
always @ (posedge WB_CLK_I or posedge Reset)
2007
begin
2008
  if(Reset)
2009
    TxB_IRQ <=#Tp 1'b0;
2010
  else
2011
  if(TxStatusWrite & TxIRQEn)
2012
    TxB_IRQ <=#Tp ~TxError;
2013
  else
2014
    TxB_IRQ <=#Tp 1'b0;
2015
end
2016
 
2017
 
2018
// Tx Error Interrupt
2019
always @ (posedge WB_CLK_I or posedge Reset)
2020
begin
2021
  if(Reset)
2022
    TxE_IRQ <=#Tp 1'b0;
2023
  else
2024
  if(TxStatusWrite & TxIRQEn)
2025
    TxE_IRQ <=#Tp TxError;
2026
  else
2027
    TxE_IRQ <=#Tp 1'b0;
2028
end
2029
 
2030
 
2031
// Rx Done Interrupt
2032
always @ (posedge WB_CLK_I or posedge Reset)
2033
begin
2034
  if(Reset)
2035
    RxB_IRQ <=#Tp 1'b0;
2036
  else
2037
  if(RxStatusWrite & RxIRQEn)
2038
    RxB_IRQ <=#Tp ReceivedPacketGood;
2039
  else
2040
    RxB_IRQ <=#Tp 1'b0;
2041
end
2042
 
2043
 
2044
// Rx Error Interrupt
2045
always @ (posedge WB_CLK_I or posedge Reset)
2046
begin
2047
  if(Reset)
2048
    RxE_IRQ <=#Tp 1'b0;
2049
  else
2050
  if(RxStatusWrite & RxIRQEn)
2051
    RxE_IRQ <=#Tp RxError;
2052
  else
2053
    RxE_IRQ <=#Tp 1'b0;
2054
end
2055
 
2056
 
2057
assign RxC_IRQ = 1'b0;
2058
assign TxC_IRQ = 1'b0;
2059
assign Busy_IRQ = 1'b0;
2060
 
2061
 
2062
 
2063
 
2064 60 mohor
 
2065
// TX
2066 61 mohor
// bit 15 ready
2067
// bit 14 interrupt
2068
// bit 13 wrap
2069
// bit 12 pad
2070
// bit 11 crc
2071
// bit 10 last
2072
// bit 9  pause request (control frame)
2073
// bit 8  TxUnderRun          
2074
// bit 7-4 RetryCntLatched    
2075
// bit 3  retransmittion limit
2076
// bit 2  LateCollLatched        
2077
// bit 1  DeferLatched        
2078
// bit 0  CarrierSenseLost    
2079 60 mohor
 
2080
 
2081
// RX
2082
// bit 15 od rx je empty
2083 61 mohor
// bit 14 od rx je interrupt
2084 60 mohor
// bit 13 od rx je wrap
2085
// bit 12 od rx je reserved
2086
// bit 11 od rx je reserved
2087
// bit 10 od rx je reserved
2088
// bit 9  od rx je reserved
2089
// bit 8  od rx je reserved
2090 80 mohor
// bit 7  od rx je Miss               still needs to be done
2091 60 mohor
// bit 6  od rx je RxOverrun
2092
// bit 5  od rx je InvalidSymbol
2093
// bit 4  od rx je DribbleNibble
2094
// bit 3  od rx je ReceivedPacketTooBig
2095
// bit 2  od rx je ShortFrame
2096
// bit 1  od rx je LatchedCrcError
2097
// bit 0  od rx je RxLateCollision
2098
 
2099 38 mohor
endmodule
2100
 

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