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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Blame information for rev 119

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1 38 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_wishbone.v                                              ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 118 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 38 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 119 mohor
// Revision 1.29  2002/07/20 00:41:32  mohor
45
// ShiftEnded synchronization changed.
46
//
47 118 mohor
// Revision 1.28  2002/07/18 16:11:46  mohor
48
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
49
//
50 115 mohor
// Revision 1.27  2002/07/11 02:53:20  mohor
51
// RxPointer bug fixed.
52
//
53 113 mohor
// Revision 1.26  2002/07/10 13:12:38  mohor
54
// Previous bug wasn't succesfully removed. Now fixed.
55
//
56 112 mohor
// Revision 1.25  2002/07/09 23:53:24  mohor
57
// Master state machine had a bug when switching from master write to
58
// master read.
59
//
60 111 mohor
// Revision 1.24  2002/07/09 20:44:41  mohor
61
// m_wb_cyc_o signal released after every single transfer.
62
//
63 110 mohor
// Revision 1.23  2002/05/03 10:15:50  mohor
64
// Outputs registered. Reset changed for eth_wishbone module.
65
//
66 106 mohor
// Revision 1.22  2002/04/24 08:52:19  mohor
67
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
68
// bug fixed.
69
//
70 105 mohor
// Revision 1.21  2002/03/29 16:18:11  lampret
71
// Small typo fixed.
72
//
73 97 lampret
// Revision 1.20  2002/03/25 16:19:12  mohor
74
// Any address can be used for Tx and Rx BD pointers. Address does not need
75
// to be aligned.
76
//
77 96 mohor
// Revision 1.19  2002/03/19 12:51:50  mohor
78
// Comments in Slovene language removed.
79
//
80 91 mohor
// Revision 1.18  2002/03/19 12:46:52  mohor
81
// casex changed with case, fifo reset changed.
82
//
83 90 mohor
// Revision 1.17  2002/03/09 16:08:45  mohor
84
// rx_fifo was not always cleared ok. Fixed.
85
//
86 88 mohor
// Revision 1.16  2002/03/09 13:51:20  mohor
87
// Status was not latched correctly sometimes. Fixed.
88
//
89 87 mohor
// Revision 1.15  2002/03/08 06:56:46  mohor
90
// Big Endian problem when sending frames fixed.
91
//
92 86 mohor
// Revision 1.14  2002/03/02 19:12:40  mohor
93
// Byte ordering changed (Big Endian used). casex changed with case because
94
// Xilinx Foundation had problems. Tested in HW. It WORKS.
95
//
96 82 mohor
// Revision 1.13  2002/02/26 16:59:55  mohor
97
// Small fixes for external/internal DMA missmatches.
98
//
99 80 mohor
// Revision 1.12  2002/02/26 16:22:07  mohor
100
// Interrupts changed
101
//
102 77 mohor
// Revision 1.11  2002/02/15 17:07:39  mohor
103
// Status was not written correctly when frames were discarted because of
104
// address mismatch.
105
//
106 64 mohor
// Revision 1.10  2002/02/15 12:17:39  mohor
107
// RxStartFrm cleared when abort or retry comes.
108
//
109 61 mohor
// Revision 1.9  2002/02/15 11:59:10  mohor
110
// Changes that were lost when updating from 1.5 to 1.8 fixed.
111
//
112 60 mohor
// Revision 1.8  2002/02/14 20:54:33  billditt
113
// Addition  of new module eth_addrcheck.v
114
//
115
// Revision 1.7  2002/02/12 17:03:47  mohor
116
// RxOverRun added to statuses.
117
//
118
// Revision 1.6  2002/02/11 09:18:22  mohor
119
// Tx status is written back to the BD.
120
//
121 43 mohor
// Revision 1.5  2002/02/08 16:21:54  mohor
122
// Rx status is written back to the BD.
123
//
124 42 mohor
// Revision 1.4  2002/02/06 14:10:21  mohor
125
// non-DMA host interface added. Select the right configutation in eth_defines.
126
//
127 41 mohor
// Revision 1.3  2002/02/05 16:44:39  mohor
128
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
129
// MHz. Statuses, overrun, control frame transmission and reception still  need
130
// to be fixed.
131
//
132 40 mohor
// Revision 1.2  2002/02/01 12:46:51  mohor
133
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
134
// added.
135
//
136 39 mohor
// Revision 1.1  2002/01/23 10:47:59  mohor
137
// Initial version. Equals to eth_wishbonedma.v at this moment.
138 38 mohor
//
139
//
140
//
141 39 mohor
//
142 38 mohor
 
143 77 mohor
// Build pause frame
144
// Check GotData and evaluate data (abort or something like that comes before StartFrm)
145
// m_wb_err_i should start status underrun or uverrun
146
// r_RecSmall not used
147 38 mohor
 
148
`include "eth_defines.v"
149
`include "timescale.v"
150
 
151
 
152
module eth_wishbone
153
   (
154
 
155
    // WISHBONE common
156 40 mohor
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
157 38 mohor
 
158
    // WISHBONE slave
159 77 mohor
                WB_ADR_I, WB_WE_I, WB_ACK_O,
160 40 mohor
    BDCs,
161 38 mohor
 
162 40 mohor
    Reset,
163
 
164 39 mohor
    // WISHBONE master
165
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
166
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
167
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
168
 
169 38 mohor
    //TX
170 60 mohor
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
171 38 mohor
    TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,
172
    PerPacketPad,
173
 
174
    //RX
175 40 mohor
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
176 38 mohor
 
177
    // Register
178 77 mohor
    r_TxEn, r_RxEn, r_TxBDNum, TX_BD_NUM_Wr, r_RecSmall,
179 38 mohor
 
180 91 mohor
    WillSendControlFrame, TxCtrlEndFrm, // WillSendControlFrame out ?
181 38 mohor
 
182
    // Interrupts
183 77 mohor
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
184 42 mohor
 
185 60 mohor
    // Rx Status
186 42 mohor
    InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
187 77 mohor
    ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
188 60 mohor
 
189
    // Tx Status
190
    RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
191 110 mohor
 
192 38 mohor
                );
193
 
194
 
195
parameter Tp = 1;
196
 
197
// WISHBONE common
198
input           WB_CLK_I;       // WISHBONE clock
199
input  [31:0]   WB_DAT_I;       // WISHBONE data input
200
output [31:0]   WB_DAT_O;       // WISHBONE data output
201
 
202
// WISHBONE slave
203
input   [9:2]   WB_ADR_I;       // WISHBONE address input
204
input           WB_WE_I;        // WISHBONE write enable input
205
input           BDCs;           // Buffer descriptors are selected
206
output          WB_ACK_O;       // WISHBONE acknowledge output
207
 
208 39 mohor
// WISHBONE master
209
output  [31:0]  m_wb_adr_o;     // 
210
output   [3:0]  m_wb_sel_o;     // 
211
output          m_wb_we_o;      // 
212
output  [31:0]  m_wb_dat_o;     // 
213
output          m_wb_cyc_o;     // 
214
output          m_wb_stb_o;     // 
215
input   [31:0]  m_wb_dat_i;     // 
216
input           m_wb_ack_i;     // 
217
input           m_wb_err_i;     // 
218
 
219 40 mohor
input           Reset;       // Reset signal
220 39 mohor
 
221 60 mohor
// Rx Status signals
222 42 mohor
input           InvalidSymbol;    // Invalid symbol was received during reception in 100 Mbps mode
223
input           LatchedCrcError;  // CRC error
224
input           RxLateCollision;  // Late collision occured while receiving frame
225
input           ShortFrame;       // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
226
input           DribbleNibble;    // Extra nibble received
227
input           ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
228
input    [15:0] RxLength;         // Length of the incoming frame
229
input           LoadRxStatus;     // Rx status was loaded
230 77 mohor
input           ReceivedPacketGood;// Received packet's length and CRC are good
231 39 mohor
 
232 60 mohor
// Tx Status signals
233
input     [3:0] RetryCntLatched;  // Latched Retry Counter
234
input           RetryLimit;       // Retry limit reached (Retry Max value + 1 attempts were made)
235
input           LateCollLatched;  // Late collision occured
236
input           DeferLatched;     // Defer indication (Frame was defered before sucessfully sent)
237
input           CarrierSenseLost; // Carrier Sense was lost during the frame transmission
238
 
239 38 mohor
// Tx
240
input           MTxClk;         // Transmit clock (from PHY)
241
input           TxUsedData;     // Transmit packet used data
242
input           TxRetry;        // Transmit packet retry
243
input           TxAbort;        // Transmit packet abort
244
input           TxDone;         // Transmission ended
245
output          TxStartFrm;     // Transmit packet start frame
246
output          TxEndFrm;       // Transmit packet end frame
247
output  [7:0]   TxData;         // Transmit packet data byte
248
output          TxUnderRun;     // Transmit packet under-run
249
output          PerPacketCrcEn; // Per packet crc enable
250
output          PerPacketPad;   // Per packet pading
251
output          TPauseRq;       // Tx PAUSE control frame
252
output [15:0]   TxPauseTV;      // PAUSE timer value
253
input           WillSendControlFrame;
254
input           TxCtrlEndFrm;
255
 
256
// Rx
257
input           MRxClk;         // Receive clock (from PHY)
258
input   [7:0]   RxData;         // Received data byte (from PHY)
259
input           RxValid;        // 
260
input           RxStartFrm;     // 
261
input           RxEndFrm;       // 
262 40 mohor
input           RxAbort;        // This signal is set when address doesn't match.
263 38 mohor
 
264
//Register
265
input           r_TxEn;         // Transmit enable
266
input           r_RxEn;         // Receive enable
267
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
268
input           TX_BD_NUM_Wr;   // RxBDNumber written
269 42 mohor
input           r_RecSmall;     // Receive small frames igor !!! tega uporabi
270 38 mohor
 
271
// Interrupts
272
output TxB_IRQ;
273
output TxE_IRQ;
274
output RxB_IRQ;
275 77 mohor
output RxE_IRQ;
276 38 mohor
output Busy_IRQ;
277 77 mohor
output TxC_IRQ;
278
output RxC_IRQ;
279 38 mohor
 
280 77 mohor
 
281
reg TxB_IRQ;
282
reg TxE_IRQ;
283
reg RxB_IRQ;
284
reg RxE_IRQ;
285
 
286
 
287 38 mohor
reg             TxStartFrm;
288
reg             TxEndFrm;
289
reg     [7:0]   TxData;
290
 
291
reg             TxUnderRun;
292 60 mohor
reg             TxUnderRun_wb;
293 38 mohor
 
294
reg             TxBDRead;
295 39 mohor
wire            TxStatusWrite;
296 38 mohor
 
297
reg     [1:0]   TxValidBytesLatched;
298
 
299
reg    [15:0]   TxLength;
300 60 mohor
reg    [15:0]   LatchedTxLength;
301
reg   [14:11]   TxStatus;
302 38 mohor
 
303 60 mohor
reg   [14:13]   RxStatus;
304 38 mohor
 
305
reg             TxStartFrm_wb;
306
reg             TxRetry_wb;
307 39 mohor
reg             TxAbort_wb;
308 38 mohor
reg             TxDone_wb;
309
 
310
reg             TxDone_wb_q;
311
reg             TxAbort_wb_q;
312 39 mohor
reg             TxRetry_wb_q;
313 105 mohor
reg             TxDone_wb_q2;
314
reg             TxAbort_wb_q2;
315
reg             TxRetry_wb_q2;
316 38 mohor
reg             RxBDReady;
317
reg             TxBDReady;
318
 
319
reg             RxBDRead;
320 40 mohor
wire            RxStatusWrite;
321 38 mohor
 
322
reg    [31:0]   TxDataLatched;
323
reg     [1:0]   TxByteCnt;
324
reg             LastWord;
325 39 mohor
reg             ReadTxDataFromFifo_tck;
326 38 mohor
 
327
reg             BlockingTxStatusWrite;
328
reg             BlockingTxBDRead;
329
 
330 40 mohor
reg             Flop;
331 38 mohor
 
332
reg     [7:0]   TxBDAddress;
333
reg     [7:0]   RxBDAddress;
334
 
335
reg             TxRetrySync1;
336
reg             TxAbortSync1;
337 39 mohor
reg             TxDoneSync1;
338 38 mohor
 
339
reg             TxAbort_q;
340
reg             TxRetry_q;
341
reg             TxUsedData_q;
342
 
343
reg    [31:0]   RxDataLatched2;
344 82 mohor
 
345
// reg    [23:0]   RxDataLatched1;
346
reg    [31:8]   RxDataLatched1;     // Big Endian Byte Ordering
347
 
348 38 mohor
reg     [1:0]   RxValidBytes;
349
reg     [1:0]   RxByteCnt;
350
reg             LastByteIn;
351
reg             ShiftWillEnd;
352
 
353 40 mohor
reg             WriteRxDataToFifo;
354 42 mohor
reg    [15:0]   LatchedRxLength;
355 64 mohor
reg             RxAbortLatched;
356 38 mohor
 
357 40 mohor
reg             ShiftEnded;
358 60 mohor
reg             RxOverrun;
359 38 mohor
 
360 40 mohor
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
361
reg             BDRead;                     // BD Read access from WISHBONE side
362 39 mohor
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
363
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
364 38 mohor
 
365 39 mohor
reg             TxEndFrm_wb;
366 38 mohor
 
367 39 mohor
wire            TxRetryPulse;
368 38 mohor
wire            TxDonePulse;
369
wire            TxAbortPulse;
370 105 mohor
wire            TxRetryPulse_q;
371
wire            TxDonePulse_q;
372
wire            TxAbortPulse_q;
373 38 mohor
 
374
wire            StartRxBDRead;
375
 
376
wire            StartTxBDRead;
377
 
378
wire            TxIRQEn;
379
wire            WrapTxStatusBit;
380
 
381 77 mohor
wire            RxIRQEn;
382 38 mohor
wire            WrapRxStatusBit;
383
 
384
wire    [1:0]   TxValidBytes;
385
 
386
wire    [7:0]   TempTxBDAddress;
387
wire    [7:0]   TempRxBDAddress;
388
 
389
wire            SetGotData;
390
wire            GotDataEvaluate;
391
 
392 106 mohor
reg             WB_ACK_O;
393 38 mohor
 
394 60 mohor
wire    [6:0]   RxStatusIn;
395
reg     [6:0]   RxStatusInLatched;
396 42 mohor
 
397 39 mohor
reg WbEn, WbEn_q;
398
reg RxEn, RxEn_q;
399
reg TxEn, TxEn_q;
400 38 mohor
 
401 39 mohor
wire ram_ce;
402
wire ram_we;
403
wire ram_oe;
404
reg [7:0]   ram_addr;
405
reg [31:0]  ram_di;
406
wire [31:0] ram_do;
407 38 mohor
 
408 39 mohor
wire StartTxPointerRead;
409
reg  TxPointerRead;
410
reg TxEn_needed;
411 40 mohor
reg RxEn_needed;
412 38 mohor
 
413 40 mohor
wire StartRxPointerRead;
414
reg RxPointerRead;
415 38 mohor
 
416 39 mohor
 
417 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
418
begin
419
  if(Reset)
420
    begin
421 106 mohor
      WB_ACK_O <=#Tp 1'b0;
422 40 mohor
    end
423
  else
424
    begin
425 106 mohor
      WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
426 40 mohor
    end
427
end
428 39 mohor
 
429 106 mohor
assign WB_DAT_O = ram_do;
430 39 mohor
 
431 41 mohor
// Generic synchronous single-port RAM interface
432 119 mohor
eth_spram_256x32 bd_ram (
433 39 mohor
        // Generic synchronous single-port RAM interface
434 40 mohor
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
435 39 mohor
);
436 41 mohor
 
437 39 mohor
assign ram_ce = 1'b1;
438 40 mohor
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
439 61 mohor
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
440 39 mohor
 
441
 
442 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
443 38 mohor
begin
444 40 mohor
  if(Reset)
445 39 mohor
    TxEn_needed <=#Tp 1'b0;
446 38 mohor
  else
447 40 mohor
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
448 39 mohor
    TxEn_needed <=#Tp 1'b1;
449
  else
450
  if(TxPointerRead & TxEn & TxEn_q)
451
    TxEn_needed <=#Tp 1'b0;
452 38 mohor
end
453
 
454 39 mohor
// Enabling access to the RAM for three devices.
455 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
456 39 mohor
begin
457 40 mohor
  if(Reset)
458 39 mohor
    begin
459
      WbEn <=#Tp 1'b1;
460
      RxEn <=#Tp 1'b0;
461
      TxEn <=#Tp 1'b0;
462
      ram_addr <=#Tp 8'h0;
463
      ram_di <=#Tp 32'h0;
464 77 mohor
      BDRead <=#Tp 1'b0;
465
      BDWrite <=#Tp 1'b0;
466 39 mohor
    end
467
  else
468
    begin
469
      // Switching between three stages depends on enable signals
470 90 mohor
      case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
471
        5'b100_10, 5'b100_11 :
472 39 mohor
          begin
473
            WbEn <=#Tp 1'b0;
474
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
475
            TxEn <=#Tp 1'b0;
476 40 mohor
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
477 39 mohor
            ram_di <=#Tp RxBDDataIn;
478
          end
479
        5'b100_01 :
480
          begin
481
            WbEn <=#Tp 1'b0;
482
            RxEn <=#Tp 1'b0;
483
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
484
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
485
            ram_di <=#Tp TxBDDataIn;
486
          end
487 90 mohor
        5'b010_00, 5'b010_10 :
488 39 mohor
          begin
489
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
490
            RxEn <=#Tp 1'b0;
491
            TxEn <=#Tp 1'b0;
492
            ram_addr <=#Tp WB_ADR_I[9:2];
493
            ram_di <=#Tp WB_DAT_I;
494 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
495
            BDRead <=#Tp BDCs & ~WB_WE_I;
496 39 mohor
          end
497 90 mohor
        5'b010_01, 5'b010_11 :
498 39 mohor
          begin
499
            WbEn <=#Tp 1'b0;
500
            RxEn <=#Tp 1'b0;
501
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
502
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
503
            ram_di <=#Tp TxBDDataIn;
504
          end
505 90 mohor
        5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
506 39 mohor
          begin
507
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
508
            RxEn <=#Tp 1'b0;
509
            TxEn <=#Tp 1'b0;
510
            ram_addr <=#Tp WB_ADR_I[9:2];
511
            ram_di <=#Tp WB_DAT_I;
512 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
513
            BDRead <=#Tp BDCs & ~WB_WE_I;
514 39 mohor
          end
515
        5'b100_00 :
516
          begin
517
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
518
          end
519
        5'b000_00 :
520
          begin
521
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
522
            RxEn <=#Tp 1'b0;
523
            TxEn <=#Tp 1'b0;
524
            ram_addr <=#Tp WB_ADR_I[9:2];
525
            ram_di <=#Tp WB_DAT_I;
526 40 mohor
            BDWrite <=#Tp BDCs & WB_WE_I;
527
            BDRead <=#Tp BDCs & ~WB_WE_I;
528 39 mohor
          end
529
      endcase
530
    end
531
end
532
 
533
 
534
// Delayed stage signals
535 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
536 39 mohor
begin
537 40 mohor
  if(Reset)
538 39 mohor
    begin
539
      WbEn_q <=#Tp 1'b0;
540
      RxEn_q <=#Tp 1'b0;
541
      TxEn_q <=#Tp 1'b0;
542
    end
543
  else
544
    begin
545
      WbEn_q <=#Tp WbEn;
546
      RxEn_q <=#Tp RxEn;
547
      TxEn_q <=#Tp TxEn;
548
    end
549
end
550
 
551 38 mohor
// Changes for tx occur every second clock. Flop is used for this manner.
552 40 mohor
always @ (posedge MTxClk or posedge Reset)
553 38 mohor
begin
554 40 mohor
  if(Reset)
555 38 mohor
    Flop <=#Tp 1'b0;
556
  else
557
  if(TxDone | TxAbort | TxRetry_q)
558
    Flop <=#Tp 1'b0;
559
  else
560
  if(TxUsedData)
561
    Flop <=#Tp ~Flop;
562
end
563
 
564 39 mohor
wire ResetTxBDReady;
565
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
566 38 mohor
 
567
// Latching READY status of the Tx buffer descriptor
568 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
569 38 mohor
begin
570 40 mohor
  if(Reset)
571 38 mohor
    TxBDReady <=#Tp 1'b0;
572
  else
573 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
574
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
575
  else                                                // Only packets larger then 4 bytes are transmitted.
576 39 mohor
  if(ResetTxBDReady)
577 38 mohor
    TxBDReady <=#Tp 1'b0;
578
end
579
 
580
 
581 39 mohor
// Reading the Tx buffer descriptor
582 110 mohor
assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
583 39 mohor
 
584 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
585 38 mohor
begin
586 40 mohor
  if(Reset)
587 39 mohor
    TxBDRead <=#Tp 1'b1;
588 38 mohor
  else
589 110 mohor
  if(StartTxBDRead)
590 39 mohor
    TxBDRead <=#Tp 1'b1;
591 38 mohor
  else
592 39 mohor
  if(TxBDReady)
593
    TxBDRead <=#Tp 1'b0;
594 38 mohor
end
595
 
596
 
597 39 mohor
// Reading Tx BD pointer
598
assign StartTxPointerRead = TxBDRead & TxBDReady;
599 38 mohor
 
600 39 mohor
// Reading Tx BD Pointer
601 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
602 38 mohor
begin
603 40 mohor
  if(Reset)
604 39 mohor
    TxPointerRead <=#Tp 1'b0;
605 38 mohor
  else
606 39 mohor
  if(StartTxPointerRead)
607
    TxPointerRead <=#Tp 1'b1;
608 38 mohor
  else
609 39 mohor
  if(TxEn_q)
610
    TxPointerRead <=#Tp 1'b0;
611 38 mohor
end
612
 
613
 
614 39 mohor
// Writing status back to the Tx buffer descriptor
615
assign TxStatusWrite = (TxDone_wb | TxAbort_wb) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
616 38 mohor
 
617
 
618
 
619 39 mohor
// Status writing must occur only once. Meanwhile it is blocked.
620 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
621 38 mohor
begin
622 40 mohor
  if(Reset)
623 39 mohor
    BlockingTxStatusWrite <=#Tp 1'b0;
624 38 mohor
  else
625 39 mohor
  if(TxStatusWrite)
626
    BlockingTxStatusWrite <=#Tp 1'b1;
627 38 mohor
  else
628 39 mohor
  if(~TxDone_wb & ~TxAbort_wb)
629
    BlockingTxStatusWrite <=#Tp 1'b0;
630 38 mohor
end
631
 
632
 
633 39 mohor
// TxBDRead state is activated only once. 
634 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
635 39 mohor
begin
636 40 mohor
  if(Reset)
637 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
638
  else
639 110 mohor
  if(StartTxBDRead)
640 39 mohor
    BlockingTxBDRead <=#Tp 1'b1;
641
  else
642 110 mohor
  if(~StartTxBDRead & ~TxBDReady)
643 39 mohor
    BlockingTxBDRead <=#Tp 1'b0;
644
end
645 38 mohor
 
646
 
647 39 mohor
// Latching status from the tx buffer descriptor
648
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
649 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
650 38 mohor
begin
651 40 mohor
  if(Reset)
652 60 mohor
    TxStatus <=#Tp 4'h0;
653 38 mohor
  else
654 40 mohor
  if(TxEn & TxEn_q & TxBDRead)
655 60 mohor
    TxStatus <=#Tp ram_do[14:11];
656 38 mohor
end
657
 
658 40 mohor
reg ReadTxDataFromMemory;
659
wire WriteRxDataToMemory;
660 38 mohor
 
661 39 mohor
reg MasterWbTX;
662
reg MasterWbRX;
663
 
664
reg [31:0] m_wb_adr_o;
665
reg        m_wb_cyc_o;
666
reg        m_wb_stb_o;
667 96 mohor
reg  [3:0] m_wb_sel_o;
668 39 mohor
reg        m_wb_we_o;
669 40 mohor
 
670 39 mohor
wire TxLengthEq0;
671
wire TxLengthLt4;
672
 
673 96 mohor
wire WordAccFinished;
674
wire HalfAccFinished;
675 39 mohor
 
676
//Latching length from the buffer descriptor;
677 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
678 38 mohor
begin
679 40 mohor
  if(Reset)
680 39 mohor
    TxLength <=#Tp 16'h0;
681 38 mohor
  else
682 39 mohor
  if(TxEn & TxEn_q & TxBDRead)
683
    TxLength <=#Tp ram_do[31:16];
684 38 mohor
  else
685 39 mohor
  if(MasterWbTX & m_wb_ack_i)
686
    begin
687
      if(TxLengthLt4)
688
        TxLength <=#Tp 16'h0;
689 96 mohor
      else if(WordAccFinished)
690
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
691
      else if(HalfAccFinished)
692
        TxLength <=#Tp TxLength - 2'h2;    // Length is subtracted at the data request
693 39 mohor
      else
694 96 mohor
        TxLength <=#Tp TxLength - 1'h1;    // Length is subtracted at the data request
695 39 mohor
    end
696 38 mohor
end
697
 
698 96 mohor
assign WordAccFinished = &m_wb_sel_o[3:0];
699
assign HalfAccFinished = &m_wb_sel_o[1:0];
700
 
701
 
702
 
703 60 mohor
//Latching length from the buffer descriptor;
704
always @ (posedge WB_CLK_I or posedge Reset)
705
begin
706
  if(Reset)
707
    LatchedTxLength <=#Tp 16'h0;
708
  else
709
  if(TxEn & TxEn_q & TxBDRead)
710
    LatchedTxLength <=#Tp ram_do[31:16];
711
end
712
 
713 39 mohor
assign TxLengthEq0 = TxLength == 0;
714
assign TxLengthLt4 = TxLength < 4;
715 38 mohor
 
716 39 mohor
 
717
reg BlockingIncrementTxPointer;
718
 
719
reg [31:0] TxPointer;
720 96 mohor
reg [1:0]  TxPointerLatched;
721 39 mohor
reg [31:0] RxPointer;
722 96 mohor
reg [1:0]  RxPointerLatched;
723 39 mohor
 
724 96 mohor
wire TxBurstAcc;
725
wire TxWordAcc;
726
wire TxHalfAcc;
727
wire TxByteAcc;
728
 
729
wire RxBurstAcc;
730
wire RxWordAcc;
731
wire RxHalfAcc;
732
wire RxByteAcc;
733
 
734
 
735 39 mohor
//Latching Tx buffer pointer from buffer descriptor;
736 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
737 38 mohor
begin
738 40 mohor
  if(Reset)
739 39 mohor
    TxPointer <=#Tp 0;
740 38 mohor
  else
741 39 mohor
  if(TxEn & TxEn_q & TxPointerRead)
742
    TxPointer <=#Tp ram_do;
743 38 mohor
  else
744 39 mohor
  if(MasterWbTX & ~BlockingIncrementTxPointer)
745 96 mohor
    if(TxWordAcc)
746
      TxPointer <=#Tp TxPointer + 3'h4; // Word access
747
    else if(TxHalfAcc)
748
      TxPointer <=#Tp TxPointer + 2'h2; // Half access
749
    else
750
      TxPointer <=#Tp TxPointer + 1'h1; // Byte access
751 38 mohor
end
752
 
753 96 mohor
 
754
 
755
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
756
always @ (posedge WB_CLK_I or posedge Reset)
757
begin
758
  if(Reset)
759
    TxPointerLatched[1:0] <=#Tp 0;
760
  else
761
  if(TxEn & TxEn_q & TxPointerRead)
762
    TxPointerLatched[1:0] <=#Tp ram_do[1:0];
763
end
764
 
765
 
766
assign TxBurstAcc = ~TxPointer[3] & ~TxPointer[2] & ~TxPointer[1] & ~TxPointer[0]; // Add a counter that count burst to 4
767
assign TxWordAcc  = ~TxPointer[1] & ~TxPointer[0];
768
assign TxHalfAcc  =  TxPointer[1] & ~TxPointer[0];
769
assign TxByteAcc  =  TxPointer[0];
770
 
771
wire [3:0] m_wb_sel_tmp_tx;
772
reg  [3:0] m_wb_sel_tmp_rx;
773
 
774
 
775
assign m_wb_sel_tmp_tx[0] = TxWordAcc | TxHalfAcc | TxByteAcc &  TxPointer[1];
776
assign m_wb_sel_tmp_tx[1] = TxWordAcc | TxHalfAcc;
777 105 mohor
assign m_wb_sel_tmp_tx[2] = TxWordAcc |             TxByteAcc & ~TxPointer[1];
778 96 mohor
assign m_wb_sel_tmp_tx[3] = TxWordAcc;
779
 
780
 
781 39 mohor
wire MasterAccessFinished;
782 38 mohor
 
783 39 mohor
 
784 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
785 38 mohor
begin
786 40 mohor
  if(Reset)
787 39 mohor
    BlockingIncrementTxPointer <=#Tp 0;
788 38 mohor
  else
789 39 mohor
  if(MasterAccessFinished)
790
    BlockingIncrementTxPointer <=#Tp 0;
791 38 mohor
  else
792 39 mohor
  if(MasterWbTX)
793
    BlockingIncrementTxPointer <=#Tp 1'b1;
794 38 mohor
end
795
 
796
 
797 39 mohor
wire TxBufferAlmostFull;
798
wire TxBufferFull;
799
wire TxBufferEmpty;
800
wire TxBufferAlmostEmpty;
801 40 mohor
wire ResetReadTxDataFromMemory;
802
wire SetReadTxDataFromMemory;
803 39 mohor
 
804 40 mohor
reg BlockReadTxDataFromMemory;
805 39 mohor
 
806 105 mohor
assign ResetReadTxDataFromMemory = (TxLengthEq0) | TxAbortPulse_q | TxRetryPulse_q;
807 40 mohor
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
808 39 mohor
 
809 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
810 38 mohor
begin
811 40 mohor
  if(Reset)
812
    ReadTxDataFromMemory <=#Tp 1'b0;
813 38 mohor
  else
814 40 mohor
  if(ResetReadTxDataFromMemory)
815
    ReadTxDataFromMemory <=#Tp 1'b0;
816 39 mohor
  else
817 40 mohor
  if(SetReadTxDataFromMemory)
818
    ReadTxDataFromMemory <=#Tp 1'b1;
819 38 mohor
end
820
 
821 40 mohor
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
822 39 mohor
wire [31:0] TxData_wb;
823
wire ReadTxDataFromFifo_wb;
824 38 mohor
 
825 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
826 38 mohor
begin
827 40 mohor
  if(Reset)
828
    BlockReadTxDataFromMemory <=#Tp 1'b0;
829 38 mohor
  else
830 90 mohor
  if(ReadTxDataFromFifo_wb | ResetReadTxDataFromMemory)
831 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b0;
832 38 mohor
  else
833 39 mohor
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
834 40 mohor
    BlockReadTxDataFromMemory <=#Tp 1'b1;
835 39 mohor
end
836
 
837
 
838
 
839
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
840 110 mohor
reg cyc_cleared;
841 118 mohor
 
842 39 mohor
// Enabling master wishbone access to the memory for two devices TX and RX.
843 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
844 39 mohor
begin
845 40 mohor
  if(Reset)
846 38 mohor
    begin
847 39 mohor
      MasterWbTX <=#Tp 1'b0;
848
      MasterWbRX <=#Tp 1'b0;
849
      m_wb_adr_o <=#Tp 32'h0;
850
      m_wb_cyc_o <=#Tp 1'b0;
851
      m_wb_stb_o <=#Tp 1'b0;
852
      m_wb_we_o  <=#Tp 1'b0;
853 96 mohor
      m_wb_sel_o <=#Tp 4'h0;
854 110 mohor
      cyc_cleared<=#Tp 1'b0;
855 38 mohor
    end
856 39 mohor
  else
857
    begin
858
      // Switching between two stages depends on enable signals
859 110 mohor
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared})  // synopsys parallel_case
860
        6'b00_01_0_x, 6'b00_11_0_x :
861 39 mohor
          begin
862
            MasterWbTX <=#Tp 1'b0;  // idle and master write is needed (data write to rx buffer)
863
            MasterWbRX <=#Tp 1'b1;
864
            m_wb_adr_o <=#Tp RxPointer;
865
            m_wb_cyc_o <=#Tp 1'b1;
866
            m_wb_stb_o <=#Tp 1'b1;
867
            m_wb_we_o  <=#Tp 1'b1;
868 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
869 39 mohor
          end
870 110 mohor
        6'b00_10_0_x, 6'b00_10_1_x :
871 39 mohor
          begin
872
            MasterWbTX <=#Tp 1'b1;  // idle and master read is needed (data read from tx buffer)
873
            MasterWbRX <=#Tp 1'b0;
874
            m_wb_adr_o <=#Tp TxPointer;
875
            m_wb_cyc_o <=#Tp 1'b1;
876
            m_wb_stb_o <=#Tp 1'b1;
877
            m_wb_we_o  <=#Tp 1'b0;
878 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
879 39 mohor
          end
880 110 mohor
        6'b10_10_0_1 :
881 39 mohor
          begin
882
            MasterWbTX <=#Tp 1'b1;  // master read and master read is needed (data read from tx buffer)
883
            MasterWbRX <=#Tp 1'b0;
884
            m_wb_adr_o <=#Tp TxPointer;
885
            m_wb_cyc_o <=#Tp 1'b1;
886
            m_wb_stb_o <=#Tp 1'b1;
887
            m_wb_we_o  <=#Tp 1'b0;
888 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
889 110 mohor
            cyc_cleared<=#Tp 1'b0;
890 39 mohor
          end
891 110 mohor
        6'b01_01_0_1 :
892 39 mohor
          begin
893
            MasterWbTX <=#Tp 1'b0;  // master write and master write is needed (data write to rx buffer)
894
            MasterWbRX <=#Tp 1'b1;
895
            m_wb_adr_o <=#Tp RxPointer;
896 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
897
            m_wb_stb_o <=#Tp 1'b1;
898 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
899 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
900 110 mohor
            cyc_cleared<=#Tp 1'b0;
901 39 mohor
          end
902 110 mohor
        6'b10_01_0_1, 6'b10_11_0_1 :
903 39 mohor
          begin
904
            MasterWbTX <=#Tp 1'b0;  // master read and master write is needed (data write to rx buffer)
905
            MasterWbRX <=#Tp 1'b1;
906
            m_wb_adr_o <=#Tp RxPointer;
907 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
908
            m_wb_stb_o <=#Tp 1'b1;
909 39 mohor
            m_wb_we_o  <=#Tp 1'b1;
910 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
911 110 mohor
            cyc_cleared<=#Tp 1'b0;
912 39 mohor
          end
913 111 mohor
        6'b01_10_0_1, 6'b01_11_0_1 :
914 39 mohor
          begin
915
            MasterWbTX <=#Tp 1'b1;  // master write and master read is needed (data read from tx buffer)
916
            MasterWbRX <=#Tp 1'b0;
917
            m_wb_adr_o <=#Tp TxPointer;
918 112 mohor
            m_wb_cyc_o <=#Tp 1'b1;
919
            m_wb_stb_o <=#Tp 1'b1;
920 39 mohor
            m_wb_we_o  <=#Tp 1'b0;
921 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_tmp_tx;
922 110 mohor
            cyc_cleared<=#Tp 1'b0;
923 39 mohor
          end
924 110 mohor
        6'b10_10_1_0, 6'b01_01_1_0, 6'b10_01_1_0, 6'b10_11_1_0, 6'b01_10_1_0, 6'b01_11_1_0 :
925 39 mohor
          begin
926 110 mohor
            m_wb_cyc_o <=#Tp 1'b0;  // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
927
            m_wb_stb_o <=#Tp 1'b0;
928
            cyc_cleared<=#Tp 1'b1;
929
          end
930
        6'b10_00_1_x, 6'b01_00_1_x :
931
          begin
932 39 mohor
            MasterWbTX <=#Tp 1'b0;  // whatever and no master read or write is needed (ack or err comes finishing previous access)
933
            MasterWbRX <=#Tp 1'b0;
934
            m_wb_cyc_o <=#Tp 1'b0;
935
            m_wb_stb_o <=#Tp 1'b0;
936
          end
937 82 mohor
        default:                            // Don't touch
938
          begin
939
            MasterWbTX <=#Tp MasterWbTX;
940
            MasterWbRX <=#Tp MasterWbRX;
941
            m_wb_cyc_o <=#Tp m_wb_cyc_o;
942
            m_wb_stb_o <=#Tp m_wb_stb_o;
943 96 mohor
            m_wb_sel_o <=#Tp m_wb_sel_o;
944 82 mohor
          end
945 39 mohor
      endcase
946
    end
947 38 mohor
end
948
 
949 110 mohor
 
950
 
951 39 mohor
wire TxFifoClear;
952 96 mohor
wire [31:0] tx_fifo_dat_i;
953
 
954 39 mohor
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
955 38 mohor
 
956 96 mohor
reg  [23:16] LatchedData;
957
wire [23:16] TempData;
958
 
959
always @ (posedge WB_CLK_I or posedge Reset)
960
begin
961
  if(Reset)
962
    LatchedData[23:16] <=#Tp 0;
963
  else
964
  if(MasterWbTX & m_wb_ack_i & m_wb_sel_o[2])
965
    LatchedData[23:16] <=#Tp m_wb_dat_i[23:16];
966
end
967
 
968
assign TempData[23:16] = m_wb_sel_o[2]? m_wb_dat_i[23:16] : LatchedData[23:16];
969
 
970
assign tx_fifo_dat_i[31:0] = {m_wb_dat_i[31:24], TempData[23:16], m_wb_dat_i[15:8], m_wb_dat_i[7:0]};
971
 
972
 
973 40 mohor
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
974 96 mohor
tx_fifo ( .data_in(tx_fifo_dat_i),                          .data_out(TxData_wb),
975
          .clk(WB_CLK_I),                                   .reset(Reset),
976
          .write(MasterWbTX & m_wb_ack_i & m_wb_sel_o[0]),  .read(ReadTxDataFromFifo_wb),
977
          .clear(TxFifoClear),                              .full(TxBufferFull),
978
          .almost_full(TxBufferAlmostFull),                 .almost_empty(TxBufferAlmostEmpty),
979 105 mohor
          .empty(TxBufferEmpty),                            .cnt()
980 96 mohor
        );
981 39 mohor
 
982
 
983
reg StartOccured;
984
reg TxStartFrm_sync1;
985
reg TxStartFrm_sync2;
986
reg TxStartFrm_syncb1;
987
reg TxStartFrm_syncb2;
988
 
989
 
990
 
991
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
992 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
993 38 mohor
begin
994 40 mohor
  if(Reset)
995 39 mohor
    TxStartFrm_wb <=#Tp 1'b0;
996 38 mohor
  else
997 39 mohor
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
998
    TxStartFrm_wb <=#Tp 1'b1;
999 38 mohor
  else
1000 39 mohor
  if(TxStartFrm_syncb2)
1001
    TxStartFrm_wb <=#Tp 1'b0;
1002 38 mohor
end
1003
 
1004 39 mohor
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
1005 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1006 38 mohor
begin
1007 40 mohor
  if(Reset)
1008 39 mohor
    StartOccured <=#Tp 1'b0;
1009 38 mohor
  else
1010 39 mohor
  if(TxStartFrm_wb)
1011
    StartOccured <=#Tp 1'b1;
1012 38 mohor
  else
1013 39 mohor
  if(ResetTxBDReady)
1014
    StartOccured <=#Tp 1'b0;
1015 38 mohor
end
1016
 
1017 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1018 40 mohor
always @ (posedge MTxClk or posedge Reset)
1019 39 mohor
begin
1020 40 mohor
  if(Reset)
1021 39 mohor
    TxStartFrm_sync1 <=#Tp 1'b0;
1022
  else
1023
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
1024
end
1025 38 mohor
 
1026 40 mohor
always @ (posedge MTxClk or posedge Reset)
1027 39 mohor
begin
1028 40 mohor
  if(Reset)
1029 39 mohor
    TxStartFrm_sync2 <=#Tp 1'b0;
1030
  else
1031
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
1032
end
1033
 
1034 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1035 38 mohor
begin
1036 40 mohor
  if(Reset)
1037 39 mohor
    TxStartFrm_syncb1 <=#Tp 1'b0;
1038 38 mohor
  else
1039 39 mohor
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
1040 38 mohor
end
1041
 
1042 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1043 38 mohor
begin
1044 40 mohor
  if(Reset)
1045 39 mohor
    TxStartFrm_syncb2 <=#Tp 1'b0;
1046 38 mohor
  else
1047 39 mohor
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
1048
end
1049
 
1050 40 mohor
always @ (posedge MTxClk or posedge Reset)
1051 39 mohor
begin
1052 40 mohor
  if(Reset)
1053 39 mohor
    TxStartFrm <=#Tp 1'b0;
1054 38 mohor
  else
1055 39 mohor
  if(TxStartFrm_sync2)
1056 61 mohor
    TxStartFrm <=#Tp 1'b1;
1057 39 mohor
  else
1058 61 mohor
  if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry | TxAbort))
1059 39 mohor
    TxStartFrm <=#Tp 1'b0;
1060 38 mohor
end
1061 39 mohor
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
1062 38 mohor
 
1063
 
1064 39 mohor
// TxEndFrm_wb: indicator of the end of frame
1065 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1066 38 mohor
begin
1067 40 mohor
  if(Reset)
1068 39 mohor
    TxEndFrm_wb <=#Tp 1'b0;
1069 38 mohor
  else
1070 39 mohor
  if(TxLengthLt4 & TxBufferAlmostEmpty & TxUsedData)
1071
    TxEndFrm_wb <=#Tp 1'b1;
1072 38 mohor
  else
1073 39 mohor
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1074
    TxEndFrm_wb <=#Tp 1'b0;
1075 38 mohor
end
1076
 
1077
 
1078
// Marks which bytes are valid within the word.
1079 39 mohor
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
1080 38 mohor
 
1081 39 mohor
reg LatchValidBytes;
1082
reg LatchValidBytes_q;
1083 38 mohor
 
1084 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1085 38 mohor
begin
1086 40 mohor
  if(Reset)
1087 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1088 38 mohor
  else
1089 39 mohor
  if(TxLengthLt4 & TxBDReady)
1090
    LatchValidBytes <=#Tp 1'b1;
1091 38 mohor
  else
1092 39 mohor
    LatchValidBytes <=#Tp 1'b0;
1093 38 mohor
end
1094
 
1095 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1096 38 mohor
begin
1097 40 mohor
  if(Reset)
1098 39 mohor
    LatchValidBytes_q <=#Tp 1'b0;
1099 38 mohor
  else
1100 39 mohor
    LatchValidBytes_q <=#Tp LatchValidBytes;
1101 38 mohor
end
1102
 
1103
 
1104 39 mohor
// Latching valid bytes
1105 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1106 38 mohor
begin
1107 40 mohor
  if(Reset)
1108 39 mohor
    TxValidBytesLatched <=#Tp 2'h0;
1109 38 mohor
  else
1110 39 mohor
  if(LatchValidBytes & ~LatchValidBytes_q)
1111
    TxValidBytesLatched <=#Tp TxValidBytes;
1112
  else
1113
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
1114
    TxValidBytesLatched <=#Tp 2'h0;
1115 38 mohor
end
1116
 
1117
 
1118
assign TxIRQEn          = TxStatus[14];
1119 60 mohor
assign WrapTxStatusBit  = TxStatus[13];
1120
assign PerPacketPad     = TxStatus[12];
1121
assign PerPacketCrcEn   = TxStatus[11];
1122 38 mohor
 
1123
 
1124 77 mohor
assign RxIRQEn         = RxStatus[14];
1125 60 mohor
assign WrapRxStatusBit = RxStatus[13];
1126 38 mohor
 
1127
 
1128
// Temporary Tx and Rx buffer descriptor address 
1129 39 mohor
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
1130 38 mohor
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum)       | // Using first Rx BD
1131 39 mohor
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
1132 38 mohor
 
1133
 
1134
// Latching Tx buffer descriptor address
1135 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1136 38 mohor
begin
1137 40 mohor
  if(Reset)
1138 38 mohor
    TxBDAddress <=#Tp 8'h0;
1139
  else
1140
  if(TxStatusWrite)
1141
    TxBDAddress <=#Tp TempTxBDAddress;
1142
end
1143
 
1144
 
1145
// Latching Rx buffer descriptor address
1146 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1147 38 mohor
begin
1148 40 mohor
  if(Reset)
1149 115 mohor
    RxBDAddress <=#Tp `ETH_TX_BD_NUM_DEF;
1150 38 mohor
  else
1151 77 mohor
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
1152 38 mohor
    RxBDAddress <=#Tp WB_DAT_I[7:0];
1153
  else
1154
  if(RxStatusWrite)
1155
    RxBDAddress <=#Tp TempRxBDAddress;
1156
end
1157
 
1158 60 mohor
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
1159 38 mohor
 
1160 60 mohor
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
1161
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
1162 38 mohor
 
1163 60 mohor
 
1164 38 mohor
// Signals used for various purposes
1165 39 mohor
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
1166 38 mohor
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
1167
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
1168 105 mohor
assign TxRetryPulse_q = TxRetry_wb_q & ~TxRetry_wb_q2;
1169
assign TxDonePulse_q  = TxDone_wb_q  & ~TxDone_wb_q2;
1170
assign TxAbortPulse_q = TxAbort_wb_q & ~TxAbort_wb_q2;
1171 38 mohor
 
1172
 
1173 91 mohor
assign TPauseRq = 0;
1174
assign TxPauseTV[15:0] = TxLength[15:0];
1175 38 mohor
 
1176
 
1177 39 mohor
// Generating delayed signals
1178 40 mohor
always @ (posedge MTxClk or posedge Reset)
1179 38 mohor
begin
1180 40 mohor
  if(Reset)
1181 39 mohor
    begin
1182
      TxAbort_q      <=#Tp 1'b0;
1183
      TxRetry_q      <=#Tp 1'b0;
1184
      TxUsedData_q   <=#Tp 1'b0;
1185
    end
1186 38 mohor
  else
1187 39 mohor
    begin
1188
      TxAbort_q      <=#Tp TxAbort;
1189
      TxRetry_q      <=#Tp TxRetry;
1190
      TxUsedData_q   <=#Tp TxUsedData;
1191
    end
1192 38 mohor
end
1193
 
1194
// Generating delayed signals
1195 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1196 38 mohor
begin
1197 40 mohor
  if(Reset)
1198 38 mohor
    begin
1199 39 mohor
      TxDone_wb_q   <=#Tp 1'b0;
1200
      TxAbort_wb_q  <=#Tp 1'b0;
1201 40 mohor
      TxRetry_wb_q  <=#Tp 1'b0;
1202 105 mohor
      TxDone_wb_q2  <=#Tp 1'b0;
1203
      TxAbort_wb_q2 <=#Tp 1'b0;
1204
      TxRetry_wb_q2 <=#Tp 1'b0;
1205 38 mohor
    end
1206
  else
1207
    begin
1208 39 mohor
      TxDone_wb_q   <=#Tp TxDone_wb;
1209
      TxAbort_wb_q  <=#Tp TxAbort_wb;
1210 40 mohor
      TxRetry_wb_q  <=#Tp TxRetry_wb;
1211 105 mohor
      TxDone_wb_q2  <=#Tp TxDone_wb_q;
1212
      TxAbort_wb_q2 <=#Tp TxAbort_wb_q;
1213
      TxRetry_wb_q2 <=#Tp TxRetry_wb_q;
1214 38 mohor
    end
1215
end
1216
 
1217
 
1218
// Sinchronizing and evaluating tx data
1219 39 mohor
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
1220
assign SetGotData = (TxStartFrm_wb); // igor namesto zgornje
1221 38 mohor
 
1222
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
1223 40 mohor
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1224
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
1225 38 mohor
 
1226
 
1227
// Indication of the last word
1228 40 mohor
always @ (posedge MTxClk or posedge Reset)
1229 38 mohor
begin
1230 40 mohor
  if(Reset)
1231 38 mohor
    LastWord <=#Tp 1'b0;
1232
  else
1233
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
1234
    LastWord <=#Tp 1'b0;
1235
  else
1236
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
1237 39 mohor
    LastWord <=#Tp TxEndFrm_wb;
1238 38 mohor
end
1239
 
1240
 
1241
// Tx end frame generation
1242 40 mohor
always @ (posedge MTxClk or posedge Reset)
1243 38 mohor
begin
1244 40 mohor
  if(Reset)
1245 38 mohor
    TxEndFrm <=#Tp 1'b0;
1246
  else
1247 91 mohor
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)
1248 38 mohor
    TxEndFrm <=#Tp 1'b0;
1249
  else
1250
  if(Flop & LastWord)
1251
    begin
1252 105 mohor
      case (TxValidBytesLatched)  // synopsys parallel_case
1253 38 mohor
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
1254
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
1255
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
1256
 
1257
        default : TxEndFrm <=#Tp 1'b0;
1258
      endcase
1259
    end
1260
end
1261
 
1262
 
1263
// Tx data selection (latching)
1264 40 mohor
always @ (posedge MTxClk or posedge Reset)
1265 38 mohor
begin
1266 40 mohor
  if(Reset)
1267 96 mohor
    TxData <=#Tp 0;
1268 38 mohor
  else
1269 39 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm)
1270 105 mohor
    case(TxPointerLatched)  // synopsys parallel_case
1271 96 mohor
      2'h0 : TxData <=#Tp TxData_wb[31:24];                  // Big Endian Byte Ordering
1272
      2'h1 : TxData <=#Tp TxData_wb[23:16];                  // Big Endian Byte Ordering
1273
      2'h2 : TxData <=#Tp TxData_wb[15:08];                  // Big Endian Byte Ordering
1274
      2'h3 : TxData <=#Tp TxData_wb[07:00];                  // Big Endian Byte Ordering
1275
    endcase
1276 38 mohor
  else
1277 96 mohor
  if(TxStartFrm & TxUsedData & TxPointerLatched==2'h3)
1278
    TxData <=#Tp TxData_wb[31:24];                           // Big Endian Byte Ordering
1279
  else
1280 38 mohor
  if(TxUsedData & Flop)
1281
    begin
1282 105 mohor
      case(TxByteCnt)  // synopsys parallel_case
1283 82 mohor
 
1284
        1 : TxData <=#Tp TxDataLatched[23:16];
1285
        2 : TxData <=#Tp TxDataLatched[15:8];
1286
        3 : TxData <=#Tp TxDataLatched[7:0];
1287 38 mohor
      endcase
1288
    end
1289
end
1290
 
1291
 
1292
// Latching tx data
1293 40 mohor
always @ (posedge MTxClk or posedge Reset)
1294 38 mohor
begin
1295 40 mohor
  if(Reset)
1296 38 mohor
    TxDataLatched[31:0] <=#Tp 32'h0;
1297
  else
1298 96 mohor
 if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1299 39 mohor
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
1300 38 mohor
end
1301
 
1302
 
1303
// Tx under run
1304 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1305 38 mohor
begin
1306 40 mohor
  if(Reset)
1307 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1308 38 mohor
  else
1309 39 mohor
  if(TxAbortPulse)
1310 60 mohor
    TxUnderRun_wb <=#Tp 1'b0;
1311
  else
1312
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
1313
    TxUnderRun_wb <=#Tp 1'b1;
1314
end
1315
 
1316
 
1317
// Tx under run
1318
always @ (posedge MTxClk or posedge Reset)
1319
begin
1320
  if(Reset)
1321 54 billditt
    TxUnderRun <=#Tp 1'b0;
1322 43 mohor
  else
1323 60 mohor
  if(TxUnderRun_wb)
1324 38 mohor
    TxUnderRun <=#Tp 1'b1;
1325 60 mohor
  else
1326
  if(BlockingTxStatusWrite)
1327
    TxUnderRun <=#Tp 1'b0;
1328 38 mohor
end
1329
 
1330
 
1331
// Tx Byte counter
1332 40 mohor
always @ (posedge MTxClk or posedge Reset)
1333 38 mohor
begin
1334 40 mohor
  if(Reset)
1335 38 mohor
    TxByteCnt <=#Tp 2'h0;
1336
  else
1337
  if(TxAbort_q | TxRetry_q)
1338
    TxByteCnt <=#Tp 2'h0;
1339
  else
1340
  if(TxStartFrm & ~TxUsedData)
1341 105 mohor
    case(TxPointerLatched)  // synopsys parallel_case
1342 96 mohor
      2'h0 : TxByteCnt <=#Tp 2'h1;
1343
      2'h1 : TxByteCnt <=#Tp 2'h2;
1344
      2'h2 : TxByteCnt <=#Tp 2'h3;
1345
      2'h3 : TxByteCnt <=#Tp 2'h0;
1346
    endcase
1347 38 mohor
  else
1348
  if(TxUsedData & Flop)
1349 96 mohor
    TxByteCnt <=#Tp TxByteCnt + 1'b1;
1350 38 mohor
end
1351
 
1352
 
1353 39 mohor
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1354
reg ReadTxDataFromFifo_sync1;
1355
reg ReadTxDataFromFifo_sync2;
1356
reg ReadTxDataFromFifo_sync3;
1357
reg ReadTxDataFromFifo_syncb1;
1358
reg ReadTxDataFromFifo_syncb2;
1359
 
1360
 
1361 40 mohor
always @ (posedge MTxClk or posedge Reset)
1362 38 mohor
begin
1363 40 mohor
  if(Reset)
1364 39 mohor
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1365 38 mohor
  else
1366 39 mohor
  if(ReadTxDataFromFifo_syncb2)
1367
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
1368 38 mohor
  else
1369 96 mohor
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
1370 39 mohor
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
1371 38 mohor
end
1372
 
1373 39 mohor
// Synchronizing TxStartFrm_wb to MTxClk
1374 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1375 38 mohor
begin
1376 40 mohor
  if(Reset)
1377 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
1378 38 mohor
  else
1379 39 mohor
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
1380
end
1381 38 mohor
 
1382 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1383 38 mohor
begin
1384 40 mohor
  if(Reset)
1385 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
1386 38 mohor
  else
1387 39 mohor
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
1388 38 mohor
end
1389
 
1390 40 mohor
always @ (posedge MTxClk or posedge Reset)
1391 38 mohor
begin
1392 40 mohor
  if(Reset)
1393 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
1394 38 mohor
  else
1395 39 mohor
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
1396 38 mohor
end
1397
 
1398 40 mohor
always @ (posedge MTxClk or posedge Reset)
1399 38 mohor
begin
1400 40 mohor
  if(Reset)
1401 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
1402 38 mohor
  else
1403 39 mohor
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
1404 38 mohor
end
1405
 
1406 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1407 38 mohor
begin
1408 40 mohor
  if(Reset)
1409 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
1410 38 mohor
  else
1411 39 mohor
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
1412 38 mohor
end
1413
 
1414 39 mohor
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
1415
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
1416 38 mohor
 
1417
 
1418 39 mohor
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
1419 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1420 38 mohor
begin
1421 40 mohor
  if(Reset)
1422 39 mohor
    TxRetrySync1 <=#Tp 1'b0;
1423 38 mohor
  else
1424 39 mohor
    TxRetrySync1 <=#Tp TxRetry;
1425 38 mohor
end
1426
 
1427 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1428 38 mohor
begin
1429 40 mohor
  if(Reset)
1430 39 mohor
    TxRetry_wb <=#Tp 1'b0;
1431 38 mohor
  else
1432 39 mohor
    TxRetry_wb <=#Tp TxRetrySync1;
1433 38 mohor
end
1434
 
1435
 
1436 39 mohor
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
1437 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1438 38 mohor
begin
1439 40 mohor
  if(Reset)
1440 39 mohor
    TxDoneSync1 <=#Tp 1'b0;
1441 38 mohor
  else
1442 39 mohor
    TxDoneSync1 <=#Tp TxDone;
1443 38 mohor
end
1444
 
1445 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1446 38 mohor
begin
1447 40 mohor
  if(Reset)
1448 39 mohor
    TxDone_wb <=#Tp 1'b0;
1449 38 mohor
  else
1450 39 mohor
    TxDone_wb <=#Tp TxDoneSync1;
1451 38 mohor
end
1452
 
1453 39 mohor
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
1454 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1455 38 mohor
begin
1456 40 mohor
  if(Reset)
1457 39 mohor
    TxAbortSync1 <=#Tp 1'b0;
1458 38 mohor
  else
1459 39 mohor
    TxAbortSync1 <=#Tp TxAbort;
1460 38 mohor
end
1461
 
1462 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1463 38 mohor
begin
1464 40 mohor
  if(Reset)
1465 38 mohor
    TxAbort_wb <=#Tp 1'b0;
1466
  else
1467 39 mohor
    TxAbort_wb <=#Tp TxAbortSync1;
1468 38 mohor
end
1469
 
1470
 
1471 90 mohor
assign StartRxBDRead = RxStatusWrite | RxAbortLatched;
1472 39 mohor
 
1473 40 mohor
// Reading the Rx buffer descriptor
1474
always @ (posedge WB_CLK_I or posedge Reset)
1475
begin
1476
  if(Reset)
1477
    RxBDRead <=#Tp 1'b1;
1478
  else
1479 90 mohor
  if(StartRxBDRead & ~RxBDReady)
1480 40 mohor
    RxBDRead <=#Tp 1'b1;
1481
  else
1482
  if(RxBDReady)
1483
    RxBDRead <=#Tp 1'b0;
1484
end
1485 39 mohor
 
1486
 
1487 38 mohor
// Reading of the next receive buffer descriptor starts after reception status is
1488
// written to the previous one.
1489
 
1490
// Latching READY status of the Rx buffer descriptor
1491 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1492 38 mohor
begin
1493 40 mohor
  if(Reset)
1494 38 mohor
    RxBDReady <=#Tp 1'b0;
1495
  else
1496 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1497
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
1498 38 mohor
  else
1499 61 mohor
  if(ShiftEnded | RxAbort)
1500 38 mohor
    RxBDReady <=#Tp 1'b0;
1501
end
1502
 
1503 40 mohor
// Latching Rx buffer descriptor status
1504
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
1505
always @ (posedge WB_CLK_I or posedge Reset)
1506 38 mohor
begin
1507 40 mohor
  if(Reset)
1508 60 mohor
    RxStatus <=#Tp 2'h0;
1509 38 mohor
  else
1510 40 mohor
  if(RxEn & RxEn_q & RxBDRead)
1511 60 mohor
    RxStatus <=#Tp ram_do[14:13];
1512 38 mohor
end
1513
 
1514
 
1515
 
1516
 
1517 40 mohor
// Reading Rx BD pointer
1518
 
1519
 
1520
assign StartRxPointerRead = RxBDRead & RxBDReady;
1521
 
1522
// Reading Tx BD Pointer
1523
always @ (posedge WB_CLK_I or posedge Reset)
1524 38 mohor
begin
1525 40 mohor
  if(Reset)
1526
    RxPointerRead <=#Tp 1'b0;
1527 38 mohor
  else
1528 40 mohor
  if(StartRxPointerRead)
1529
    RxPointerRead <=#Tp 1'b1;
1530 38 mohor
  else
1531 40 mohor
  if(RxEn_q)
1532
    RxPointerRead <=#Tp 1'b0;
1533 38 mohor
end
1534
 
1535 113 mohor
 
1536 40 mohor
//Latching Rx buffer pointer from buffer descriptor;
1537
always @ (posedge WB_CLK_I or posedge Reset)
1538
begin
1539
  if(Reset)
1540
    RxPointer <=#Tp 32'h0;
1541
  else
1542
  if(RxEn & RxEn_q & RxPointerRead)
1543 96 mohor
    RxPointer <=#Tp {ram_do[31:2], 2'h0};
1544 40 mohor
  else
1545 113 mohor
  if(MasterWbRX & m_wb_ack_i)
1546 96 mohor
      RxPointer <=#Tp RxPointer + 3'h4; // Word access  (always word access. m_wb_sel_o are used for selecting bytes)
1547 40 mohor
end
1548 38 mohor
 
1549
 
1550 96 mohor
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
1551 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1552
begin
1553
  if(Reset)
1554 96 mohor
    RxPointerLatched[1:0] <=#Tp 0;
1555
  else
1556
  if(MasterWbRX & m_wb_ack_i)                 // After first write all m_wb_sel_tmp_rx are active
1557
    RxPointerLatched[1:0] <=#Tp 0;
1558
  else
1559
  if(RxEn & RxEn_q & RxPointerRead)
1560
    RxPointerLatched[1:0] <=#Tp ram_do[1:0];
1561
end
1562
 
1563
 
1564
always @ (RxPointerLatched)
1565
begin
1566 105 mohor
  case(RxPointerLatched[1:0])  // synopsys parallel_case
1567 96 mohor
    2'h0 : m_wb_sel_tmp_rx[3:0] = 4'hf;
1568
    2'h1 : m_wb_sel_tmp_rx[3:0] = 4'h7;
1569
    2'h2 : m_wb_sel_tmp_rx[3:0] = 4'h3;
1570
    2'h3 : m_wb_sel_tmp_rx[3:0] = 4'h1;
1571
  endcase
1572
end
1573
 
1574
 
1575
always @ (posedge WB_CLK_I or posedge Reset)
1576
begin
1577
  if(Reset)
1578 40 mohor
    RxEn_needed <=#Tp 1'b0;
1579 38 mohor
  else
1580 40 mohor
  if(~RxBDReady & r_RxEn & WbEn & ~WbEn_q)
1581
    RxEn_needed <=#Tp 1'b1;
1582 38 mohor
  else
1583 40 mohor
  if(RxPointerRead & RxEn & RxEn_q)
1584
    RxEn_needed <=#Tp 1'b0;
1585 38 mohor
end
1586
 
1587
 
1588 40 mohor
// Reception status is written back to the buffer descriptor after the end of frame is detected.
1589
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
1590 38 mohor
 
1591 42 mohor
reg RxStatusWriteLatched;
1592
reg RxStatusWrite_rck;
1593
 
1594
always @ (posedge WB_CLK_I or posedge Reset)
1595
begin
1596
  if(Reset)
1597
    RxStatusWriteLatched <=#Tp 1'b0;
1598
  else
1599 87 mohor
  if(RxStatusWrite & ~RxStatusWrite_rck)
1600 42 mohor
    RxStatusWriteLatched <=#Tp 1'b1;
1601
  else
1602
  if(RxStatusWrite_rck)
1603
    RxStatusWriteLatched <=#Tp 1'b0;
1604
end
1605
 
1606
 
1607
always @ (posedge MRxClk or posedge Reset)
1608
begin
1609
  if(Reset)
1610
    RxStatusWrite_rck <=#Tp 1'b0;
1611
  else
1612 87 mohor
  if(RxStatusWriteLatched)
1613
    RxStatusWrite_rck <=#Tp 1'b1;
1614
  else
1615
    RxStatusWrite_rck <=#Tp 1'b0;
1616 42 mohor
end
1617
 
1618
 
1619 40 mohor
reg RxEnableWindow;
1620 38 mohor
 
1621
// Indicating that last byte is being reveived
1622 40 mohor
always @ (posedge MRxClk or posedge Reset)
1623 38 mohor
begin
1624 40 mohor
  if(Reset)
1625 38 mohor
    LastByteIn <=#Tp 1'b0;
1626
  else
1627 40 mohor
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
1628 38 mohor
    LastByteIn <=#Tp 1'b0;
1629
  else
1630 40 mohor
  if(RxValid & RxBDReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
1631 38 mohor
    LastByteIn <=#Tp 1'b1;
1632
end
1633
 
1634 40 mohor
reg ShiftEnded_tck;
1635
reg ShiftEndedSync1;
1636
reg ShiftEndedSync2;
1637 118 mohor
reg ShiftEndedSync3;
1638
reg ShiftEndedSync_c1;
1639
reg ShiftEndedSync_c2;
1640
 
1641 40 mohor
wire StartShiftWillEnd;
1642 96 mohor
//assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1643
assign StartShiftWillEnd = LastByteIn  | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
1644 38 mohor
 
1645
// Indicating that data reception will end
1646 40 mohor
always @ (posedge MRxClk or posedge Reset)
1647 38 mohor
begin
1648 40 mohor
  if(Reset)
1649 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1650
  else
1651 40 mohor
  if(ShiftEnded_tck | RxAbort)
1652 38 mohor
    ShiftWillEnd <=#Tp 1'b0;
1653
  else
1654 40 mohor
  if(StartShiftWillEnd)
1655 38 mohor
    ShiftWillEnd <=#Tp 1'b1;
1656
end
1657
 
1658
 
1659 40 mohor
 
1660 38 mohor
// Receive byte counter
1661 40 mohor
always @ (posedge MRxClk or posedge Reset)
1662 38 mohor
begin
1663 40 mohor
  if(Reset)
1664 38 mohor
    RxByteCnt <=#Tp 2'h0;
1665
  else
1666 40 mohor
  if(ShiftEnded_tck | RxAbort)
1667 38 mohor
    RxByteCnt <=#Tp 2'h0;
1668 97 lampret
  else
1669 96 mohor
  if(RxValid & RxStartFrm & RxBDReady)
1670 105 mohor
    case(RxPointerLatched)  // synopsys parallel_case
1671 96 mohor
      2'h0 : RxByteCnt <=#Tp 2'h1;
1672
      2'h1 : RxByteCnt <=#Tp 2'h2;
1673
      2'h2 : RxByteCnt <=#Tp 2'h3;
1674
      2'h3 : RxByteCnt <=#Tp 2'h0;
1675
    endcase
1676 38 mohor
  else
1677 96 mohor
  if(RxValid & RxEnableWindow & RxBDReady | LastByteIn)
1678 40 mohor
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
1679 38 mohor
end
1680
 
1681
 
1682
// Indicates how many bytes are valid within the last word
1683 40 mohor
always @ (posedge MRxClk or posedge Reset)
1684 38 mohor
begin
1685 40 mohor
  if(Reset)
1686 38 mohor
    RxValidBytes <=#Tp 2'h1;
1687
  else
1688 96 mohor
  if(RxValid & RxStartFrm)
1689 105 mohor
    case(RxPointerLatched)  // synopsys parallel_case
1690 96 mohor
      2'h0 : RxValidBytes <=#Tp 2'h1;
1691
      2'h1 : RxValidBytes <=#Tp 2'h2;
1692
      2'h2 : RxValidBytes <=#Tp 2'h3;
1693
      2'h3 : RxValidBytes <=#Tp 2'h0;
1694
    endcase
1695 38 mohor
  else
1696 40 mohor
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
1697 38 mohor
    RxValidBytes <=#Tp RxValidBytes + 1;
1698
end
1699
 
1700
 
1701 40 mohor
always @ (posedge MRxClk or posedge Reset)
1702 38 mohor
begin
1703 40 mohor
  if(Reset)
1704
    RxDataLatched1       <=#Tp 24'h0;
1705 38 mohor
  else
1706 96 mohor
  if(RxValid & RxBDReady & ~LastByteIn)
1707
    if(RxStartFrm)
1708 40 mohor
    begin
1709 96 mohor
      case(RxPointerLatched)     // synopsys parallel_case
1710
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1711
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1712
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1713
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1714
      endcase
1715
    end
1716
    else if (RxEnableWindow)
1717
    begin
1718 40 mohor
      case(RxByteCnt)     // synopsys parallel_case
1719 82 mohor
        2'h0:        RxDataLatched1[31:24] <=#Tp RxData;            // Big Endian Byte Ordering
1720
        2'h1:        RxDataLatched1[23:16] <=#Tp RxData;
1721
        2'h2:        RxDataLatched1[15:8]  <=#Tp RxData;
1722 40 mohor
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
1723
      endcase
1724
    end
1725 38 mohor
end
1726
 
1727 40 mohor
wire SetWriteRxDataToFifo;
1728 38 mohor
 
1729 40 mohor
// Assembling data that will be written to the rx_fifo
1730
always @ (posedge MRxClk or posedge Reset)
1731 38 mohor
begin
1732 40 mohor
  if(Reset)
1733
    RxDataLatched2 <=#Tp 32'h0;
1734 38 mohor
  else
1735 40 mohor
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
1736 82 mohor
    RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData};              // Big Endian Byte Ordering
1737 38 mohor
  else
1738 40 mohor
  if(SetWriteRxDataToFifo & ShiftWillEnd)
1739 105 mohor
    case(RxValidBytes)  // synopsys parallel_case
1740 96 mohor
//      0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],  RxData};       // Big Endian Byte Ordering
1741
//      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
1742
//      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
1743
//      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
1744 82 mohor
 
1745
      1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
1746
      2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
1747
      3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8],   8'h0};
1748 40 mohor
    endcase
1749 38 mohor
end
1750
 
1751
 
1752 40 mohor
reg WriteRxDataToFifoSync1;
1753
reg WriteRxDataToFifoSync2;
1754 38 mohor
 
1755
 
1756 40 mohor
// Indicating start of the reception process
1757 96 mohor
//assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
1758
assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (RxValid & RxBDReady & RxStartFrm & (&RxPointerLatched)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
1759 38 mohor
 
1760 40 mohor
always @ (posedge MRxClk or posedge Reset)
1761 38 mohor
begin
1762 40 mohor
  if(Reset)
1763
    WriteRxDataToFifo <=#Tp 1'b0;
1764 38 mohor
  else
1765 40 mohor
  if(SetWriteRxDataToFifo & ~RxAbort)
1766
    WriteRxDataToFifo <=#Tp 1'b1;
1767 38 mohor
  else
1768 40 mohor
  if(WriteRxDataToFifoSync1 | RxAbort)
1769
    WriteRxDataToFifo <=#Tp 1'b0;
1770 38 mohor
end
1771
 
1772
 
1773
 
1774 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1775
begin
1776
  if(Reset)
1777
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
1778
  else
1779
  if(WriteRxDataToFifo)
1780
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
1781
  else
1782
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
1783
end
1784 38 mohor
 
1785 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1786 38 mohor
begin
1787 40 mohor
  if(Reset)
1788
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
1789 38 mohor
  else
1790 40 mohor
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
1791 38 mohor
end
1792
 
1793 40 mohor
wire WriteRxDataToFifo_wb;
1794
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync1 & ~WriteRxDataToFifoSync2;
1795 38 mohor
 
1796 40 mohor
reg RxAbortSync1;
1797
reg RxAbortSync2;
1798
reg RxAbortSyncb1;
1799
reg RxAbortSyncb2;
1800
 
1801 90 mohor
reg LatchedRxStartFrm;
1802
reg SyncRxStartFrm;
1803
reg SyncRxStartFrm_q;
1804
wire RxFifoReset;
1805 40 mohor
 
1806 90 mohor
always @ (posedge MRxClk or posedge Reset)
1807
begin
1808
  if(Reset)
1809
    LatchedRxStartFrm <=#Tp 0;
1810
  else
1811
  if(RxStartFrm & ~SyncRxStartFrm)
1812
    LatchedRxStartFrm <=#Tp 1;
1813
  else
1814
  if(SyncRxStartFrm)
1815
    LatchedRxStartFrm <=#Tp 0;
1816
end
1817
 
1818
 
1819
always @ (posedge WB_CLK_I or posedge Reset)
1820
begin
1821
  if(Reset)
1822
    SyncRxStartFrm <=#Tp 0;
1823
  else
1824
  if(LatchedRxStartFrm)
1825
    SyncRxStartFrm <=#Tp 1;
1826
  else
1827
    SyncRxStartFrm <=#Tp 0;
1828
end
1829
 
1830
 
1831
always @ (posedge WB_CLK_I or posedge Reset)
1832
begin
1833
  if(Reset)
1834
    SyncRxStartFrm_q <=#Tp 0;
1835
  else
1836
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
1837
end
1838
 
1839
 
1840
assign RxFifoReset = SyncRxStartFrm & ~SyncRxStartFrm_q;
1841
 
1842
 
1843 40 mohor
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
1844 88 mohor
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o),
1845
         .clk(WB_CLK_I),                                .reset(Reset),
1846
         .write(WriteRxDataToFifo_wb),                  .read(MasterWbRX & m_wb_ack_i),
1847 90 mohor
         .clear(RxFifoReset),                           .full(RxBufferFull),
1848 118 mohor
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty),
1849 105 mohor
         .empty(RxBufferEmpty),                         .cnt()
1850 88 mohor
        );
1851 40 mohor
 
1852
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
1853
 
1854
 
1855
 
1856
// Generation of the end-of-frame signal
1857
always @ (posedge MRxClk or posedge Reset)
1858 38 mohor
begin
1859 40 mohor
  if(Reset)
1860
    ShiftEnded_tck <=#Tp 1'b0;
1861 38 mohor
  else
1862 118 mohor
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
1863 40 mohor
    ShiftEnded_tck <=#Tp 1'b1;
1864 38 mohor
  else
1865 118 mohor
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
1866 40 mohor
    ShiftEnded_tck <=#Tp 1'b0;
1867 38 mohor
end
1868
 
1869 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1870
begin
1871
  if(Reset)
1872
    ShiftEndedSync1 <=#Tp 1'b0;
1873
  else
1874
    ShiftEndedSync1 <=#Tp ShiftEnded_tck;
1875
end
1876 38 mohor
 
1877 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1878 38 mohor
begin
1879 40 mohor
  if(Reset)
1880
    ShiftEndedSync2 <=#Tp 1'b0;
1881 38 mohor
  else
1882 90 mohor
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
1883 40 mohor
end
1884 38 mohor
 
1885 118 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1886
begin
1887
  if(Reset)
1888
    ShiftEndedSync3 <=#Tp 1'b0;
1889
  else
1890
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
1891
    ShiftEndedSync3 <=#Tp 1'b1;
1892
  else
1893
  if(ShiftEnded)
1894
    ShiftEndedSync3 <=#Tp 1'b0;
1895
end
1896 38 mohor
 
1897 40 mohor
// Generation of the end-of-frame signal
1898
always @ (posedge WB_CLK_I or posedge Reset)
1899 38 mohor
begin
1900 40 mohor
  if(Reset)
1901
    ShiftEnded <=#Tp 1'b0;
1902 38 mohor
  else
1903 118 mohor
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
1904 40 mohor
    ShiftEnded <=#Tp 1'b1;
1905 38 mohor
  else
1906 40 mohor
  if(RxStatusWrite)
1907
    ShiftEnded <=#Tp 1'b0;
1908 38 mohor
end
1909
 
1910 118 mohor
always @ (posedge MRxClk or posedge Reset)
1911
begin
1912
  if(Reset)
1913
    ShiftEndedSync_c1 <=#Tp 1'b0;
1914
  else
1915
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
1916
end
1917 38 mohor
 
1918 118 mohor
always @ (posedge MRxClk or posedge Reset)
1919
begin
1920
  if(Reset)
1921
    ShiftEndedSync_c2 <=#Tp 1'b0;
1922
  else
1923
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
1924
end
1925
 
1926 40 mohor
// Generation of the end-of-frame signal
1927
always @ (posedge MRxClk or posedge Reset)
1928 38 mohor
begin
1929 40 mohor
  if(Reset)
1930
    RxEnableWindow <=#Tp 1'b0;
1931 38 mohor
  else
1932 40 mohor
  if(RxStartFrm)
1933
    RxEnableWindow <=#Tp 1'b1;
1934 38 mohor
  else
1935 40 mohor
  if(RxEndFrm | RxAbort)
1936
    RxEnableWindow <=#Tp 1'b0;
1937 38 mohor
end
1938
 
1939
 
1940 40 mohor
always @ (posedge WB_CLK_I or posedge Reset)
1941 38 mohor
begin
1942 40 mohor
  if(Reset)
1943
    RxAbortSync1 <=#Tp 1'b0;
1944 38 mohor
  else
1945 40 mohor
    RxAbortSync1 <=#Tp RxAbort;
1946
end
1947
 
1948
always @ (posedge WB_CLK_I or posedge Reset)
1949
begin
1950
  if(Reset)
1951
    RxAbortSync2 <=#Tp 1'b0;
1952 38 mohor
  else
1953 40 mohor
    RxAbortSync2 <=#Tp RxAbortSync1;
1954 38 mohor
end
1955
 
1956 40 mohor
always @ (posedge MRxClk or posedge Reset)
1957
begin
1958
  if(Reset)
1959
    RxAbortSyncb1 <=#Tp 1'b0;
1960
  else
1961
    RxAbortSyncb1 <=#Tp RxAbortSync2;
1962
end
1963 38 mohor
 
1964 40 mohor
always @ (posedge MRxClk or posedge Reset)
1965 38 mohor
begin
1966 40 mohor
  if(Reset)
1967
    RxAbortSyncb2 <=#Tp 1'b0;
1968 38 mohor
  else
1969 40 mohor
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
1970 38 mohor
end
1971
 
1972
 
1973 64 mohor
always @ (posedge MRxClk or posedge Reset)
1974
begin
1975
  if(Reset)
1976
    RxAbortLatched <=#Tp 1'b0;
1977
  else
1978
  if(RxAbort)
1979
    RxAbortLatched <=#Tp 1'b1;
1980
  else
1981
  if(RxStartFrm)
1982
    RxAbortLatched <=#Tp 1'b0;
1983
end
1984 40 mohor
 
1985
 
1986 42 mohor
reg LoadStatusBlocked;
1987 64 mohor
 
1988 42 mohor
always @ (posedge MRxClk or posedge Reset)
1989
begin
1990
  if(Reset)
1991
    LoadStatusBlocked <=#Tp 1'b0;
1992
  else
1993 64 mohor
  if(LoadRxStatus & ~RxAbortLatched)
1994 42 mohor
    LoadStatusBlocked <=#Tp 1'b1;
1995
  else
1996 87 mohor
  if(RxStatusWrite_rck | RxStartFrm)
1997 42 mohor
    LoadStatusBlocked <=#Tp 1'b0;
1998
end
1999
 
2000
// LatchedRxLength[15:0]
2001
always @ (posedge MRxClk or posedge Reset)
2002
begin
2003
  if(Reset)
2004
    LatchedRxLength[15:0] <=#Tp 16'h0;
2005
  else
2006 64 mohor
  if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
2007 42 mohor
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
2008
end
2009
 
2010
 
2011 60 mohor
assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
2012 42 mohor
 
2013
always @ (posedge MRxClk or posedge Reset)
2014
begin
2015
  if(Reset)
2016
    RxStatusInLatched <=#Tp 'h0;
2017
  else
2018 64 mohor
  if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
2019 42 mohor
    RxStatusInLatched <=#Tp RxStatusIn;
2020
end
2021
 
2022
 
2023 60 mohor
// Rx overrun
2024
always @ (posedge WB_CLK_I or posedge Reset)
2025
begin
2026
  if(Reset)
2027
    RxOverrun <=#Tp 1'b0;
2028
  else
2029
  if(RxStatusWrite)
2030
    RxOverrun <=#Tp 1'b0;
2031
  else
2032
  if(RxBufferFull & WriteRxDataToFifo_wb)
2033
    RxOverrun <=#Tp 1'b1;
2034
end
2035 48 mohor
 
2036 77 mohor
 
2037
 
2038
wire TxError;
2039
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
2040
 
2041
wire RxError;
2042
assign RxError = |RxStatusInLatched[6:0];
2043
 
2044
// Tx Done Interrupt
2045
always @ (posedge WB_CLK_I or posedge Reset)
2046
begin
2047
  if(Reset)
2048
    TxB_IRQ <=#Tp 1'b0;
2049
  else
2050
  if(TxStatusWrite & TxIRQEn)
2051
    TxB_IRQ <=#Tp ~TxError;
2052
  else
2053
    TxB_IRQ <=#Tp 1'b0;
2054
end
2055
 
2056
 
2057
// Tx Error Interrupt
2058
always @ (posedge WB_CLK_I or posedge Reset)
2059
begin
2060
  if(Reset)
2061
    TxE_IRQ <=#Tp 1'b0;
2062
  else
2063
  if(TxStatusWrite & TxIRQEn)
2064
    TxE_IRQ <=#Tp TxError;
2065
  else
2066
    TxE_IRQ <=#Tp 1'b0;
2067
end
2068
 
2069
 
2070
// Rx Done Interrupt
2071
always @ (posedge WB_CLK_I or posedge Reset)
2072
begin
2073
  if(Reset)
2074
    RxB_IRQ <=#Tp 1'b0;
2075
  else
2076
  if(RxStatusWrite & RxIRQEn)
2077
    RxB_IRQ <=#Tp ReceivedPacketGood;
2078
  else
2079
    RxB_IRQ <=#Tp 1'b0;
2080
end
2081
 
2082
 
2083
// Rx Error Interrupt
2084
always @ (posedge WB_CLK_I or posedge Reset)
2085
begin
2086
  if(Reset)
2087
    RxE_IRQ <=#Tp 1'b0;
2088
  else
2089
  if(RxStatusWrite & RxIRQEn)
2090
    RxE_IRQ <=#Tp RxError;
2091
  else
2092
    RxE_IRQ <=#Tp 1'b0;
2093
end
2094
 
2095
 
2096
assign RxC_IRQ = 1'b0;
2097
assign TxC_IRQ = 1'b0;
2098
assign Busy_IRQ = 1'b0;
2099
 
2100
 
2101
 
2102
 
2103 60 mohor
 
2104
// TX
2105 61 mohor
// bit 15 ready
2106
// bit 14 interrupt
2107
// bit 13 wrap
2108
// bit 12 pad
2109
// bit 11 crc
2110
// bit 10 last
2111
// bit 9  pause request (control frame)
2112
// bit 8  TxUnderRun          
2113
// bit 7-4 RetryCntLatched    
2114
// bit 3  retransmittion limit
2115
// bit 2  LateCollLatched        
2116
// bit 1  DeferLatched        
2117
// bit 0  CarrierSenseLost    
2118 60 mohor
 
2119
 
2120
// RX
2121
// bit 15 od rx je empty
2122 61 mohor
// bit 14 od rx je interrupt
2123 60 mohor
// bit 13 od rx je wrap
2124
// bit 12 od rx je reserved
2125
// bit 11 od rx je reserved
2126
// bit 10 od rx je reserved
2127
// bit 9  od rx je reserved
2128
// bit 8  od rx je reserved
2129 110 mohor
// bit 7  od rx je Miss
2130 60 mohor
// bit 6  od rx je RxOverrun
2131
// bit 5  od rx je InvalidSymbol
2132
// bit 4  od rx je DribbleNibble
2133
// bit 3  od rx je ReceivedPacketTooBig
2134
// bit 2  od rx je ShortFrame
2135
// bit 1  od rx je LatchedCrcError
2136
// bit 0  od rx je RxLateCollision
2137
 
2138 110 mohor
 
2139
 
2140 38 mohor
endmodule
2141
 

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