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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_wishbone.v                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/02/01 12:46:51  mohor
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
// added.
//
// Revision 1.1  2002/01/23 10:47:59  mohor
// Initial version. Equals to eth_wishbonedma.v at this moment.
//
//
//
//
 
// igor !!!
// Napravi, pause frame
 
// Poskusi spremeniti vse signale na wb strani da bodo imeli enake koncnice (npr _wb),
// vsi na MTxClk strani pa _txclk   
// Evaluiraj dato da pre start framom ni prisel abort ali kaj podobnega (kot je bilo v GotData, ki ga zbrisi)
 
// Naj m_wb_err_i vzge status underrun ali uverrun
 
`include "eth_defines.v"
`include "timescale.v"
 
 
module eth_wishbone
   (
 
    // WISHBONE common
    WB_CLK_I, WB_DAT_I, WB_DAT_O,
 
    // WISHBONE slave
                WB_ADR_I, WB_SEL_I, WB_WE_I, WB_ACK_O,
    BDCs,
 
    Reset,
 
    // WISHBONE master
    m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
    m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
    m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
 
    //TX
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, StatusIzTxEthMACModula,
    TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,
    PerPacketPad,
 
    //RX
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
 
    // Register
    r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr,
 
    WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven
 
    // Interrupts
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ
 
                );
 
 
parameter Tp = 1;
 
// WISHBONE common
input           WB_CLK_I;       // WISHBONE clock
input  [31:0]   WB_DAT_I;       // WISHBONE data input
output [31:0]   WB_DAT_O;       // WISHBONE data output
 
// WISHBONE slave
input   [9:2]   WB_ADR_I;       // WISHBONE address input
input   [3:0]   WB_SEL_I;       // WISHBONE byte select input
input           WB_WE_I;        // WISHBONE write enable input
input           BDCs;           // Buffer descriptors are selected
output          WB_ACK_O;       // WISHBONE acknowledge output
 
// WISHBONE master
output  [31:0]  m_wb_adr_o;     // 
output   [3:0]  m_wb_sel_o;     // 
output          m_wb_we_o;      // 
output  [31:0]  m_wb_dat_o;     // 
output          m_wb_cyc_o;     // 
output          m_wb_stb_o;     // 
input   [31:0]  m_wb_dat_i;     // 
input           m_wb_ack_i;     // 
input           m_wb_err_i;     // 
 
input           Reset;       // Reset signal
 
 
 
// DMA
// input   [1:0]   WB_ACK_I;       // DMA acknowledge input
// output  [1:0]   WB_REQ_O;       // DMA request output
// output  [1:0]   WB_ND_O;        // DMA force new descriptor output
// output          WB_RD_O;        // DMA restart descriptor output
 
// Tx
input           MTxClk;         // Transmit clock (from PHY)
input           TxUsedData;     // Transmit packet used data
input  [15:0]   StatusIzTxEthMACModula;
input           TxRetry;        // Transmit packet retry
input           TxAbort;        // Transmit packet abort
input           TxDone;         // Transmission ended
output          TxStartFrm;     // Transmit packet start frame
output          TxEndFrm;       // Transmit packet end frame
output  [7:0]   TxData;         // Transmit packet data byte
output          TxUnderRun;     // Transmit packet under-run
output          PerPacketCrcEn; // Per packet crc enable
output          PerPacketPad;   // Per packet pading
output          TPauseRq;       // Tx PAUSE control frame
output [15:0]   TxPauseTV;      // PAUSE timer value
input           WillSendControlFrame;
input           TxCtrlEndFrm;
 
// Rx
input           MRxClk;         // Receive clock (from PHY)
input   [7:0]   RxData;         // Received data byte (from PHY)
input           RxValid;        // 
input           RxStartFrm;     // 
input           RxEndFrm;       // 
input           RxAbort;        // This signal is set when address doesn't match.
 
//Register
input           r_TxEn;         // Transmit enable
input           r_RxEn;         // Receive enable
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
input           r_DmaEn;        // DMA enable
input           TX_BD_NUM_Wr;   // RxBDNumber written
 
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxF_IRQ;
output Busy_IRQ;
 
reg             TxStartFrm;
reg             TxEndFrm;
reg     [7:0]   TxData;
 
reg             TxUnderRun;
 
reg             TxBDRead;
wire            TxStatusWrite;
 
reg     [1:0]   TxValidBytesLatched;
 
reg    [15:0]   TxLength;
reg    [15:0]   TxStatus;
 
reg    [15:0]   RxStatus;
 
reg             TxStartFrm_wb;
reg             TxRetry_wb;
reg             TxAbort_wb;
reg             TxDone_wb;
 
reg             TxDone_wb_q;
reg             TxAbort_wb_q;
reg             TxRetry_wb_q;
reg             RxBDReady;
reg             TxBDReady;
 
reg             RxBDRead;
wire            RxStatusWrite;
 
reg    [31:0]   TxDataLatched;
reg     [1:0]   TxByteCnt;
reg             LastWord;
reg             ReadTxDataFromFifo_tck;
 
reg             BlockingTxStatusWrite;
reg             BlockingTxBDRead;
 
reg             Flop;
 
reg     [7:0]   TxBDAddress;
reg     [7:0]   RxBDAddress;
 
reg             TxRetrySync1;
reg             TxAbortSync1;
reg             TxDoneSync1;
 
reg             TxAbort_q;
reg             TxRetry_q;
reg             TxUsedData_q;
 
reg    [31:0]   RxDataLatched2;
reg    [23:0]   RxDataLatched1;
reg     [1:0]   RxValidBytes;
reg     [1:0]   RxByteCnt;
reg             LastByteIn;
reg             ShiftWillEnd;
 
reg             WriteRxDataToFifo;
 
reg             ShiftEnded;
 
reg             BDWrite;                    // BD Write Enable for access from WISHBONE side
reg             BDRead;                     // BD Read access from WISHBONE side
wire   [31:0]   RxBDDataIn;                 // Rx BD data in
wire   [31:0]   TxBDDataIn;                 // Tx BD data in
 
reg             TxEndFrm_wb;
 
wire            TxRetryPulse;
wire            TxDonePulse;
wire            TxAbortPulse;
 
wire            StartRxBDRead;
wire            StartRxStatusWrite;
 
wire            StartTxBDRead;
 
wire            TxIRQEn;
wire            WrapTxStatusBit;
 
wire            WrapRxStatusBit;
 
wire    [1:0]   TxValidBytes;
 
wire    [7:0]   TempTxBDAddress;
wire    [7:0]   TempRxBDAddress;
 
reg    [15:0]   RxLength;
wire   [15:0]   NewRxStatus;
 
wire            SetGotData;
wire            GotDataEvaluate;
 
reg             temp_ack;
 
`ifdef ETH_REGISTERED_OUTPUTS
reg             temp_ack2;
reg [31:0]      registered_ram_do;
`endif
 
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
 
wire ram_ce;
wire ram_we;
wire ram_oe;
reg [7:0]   ram_addr;
reg [31:0]  ram_di;
wire [31:0] ram_do;
 
wire StartTxPointerRead;
wire ResetTxPointerRead;
reg  TxPointerRead;
reg TxEn_needed;
reg RxEn_needed;
 
wire StartRxPointerRead;
reg RxPointerRead;
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    begin
      temp_ack <=#Tp 1'b0;
      `ifdef ETH_REGISTERED_OUTPUTS
      temp_ack2 <=#Tp 1'b0;
      registered_ram_do <=#Tp 32'h0;
      `endif
    end
  else
    begin
      temp_ack <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
      `ifdef ETH_REGISTERED_OUTPUTS
      temp_ack2 <=#Tp temp_ack;
      registered_ram_do <=#Tp ram_do;
      `endif
    end
end
 
`ifdef ETH_REGISTERED_OUTPUTS
  assign WB_ACK_O = temp_ack2;
  assign WB_DAT_O = registered_ram_do;
`else
  assign WB_ACK_O = temp_ack;
  assign WB_DAT_O = ram_do;
`endif
 
 
 
 
// Generic synchronous two-port RAM interface
/*
generic_tpram     #(8, 32)  i_generic_tpram
(
  .clk_a(WB_CLK_I),   .rst_a(Reset),         .ce_a(1'b1),        .we_a(BDWrite),
  .oe_a(EnableRAM),   .addr_a(WB_ADR_I[9:2]),   .di_a(WB_DAT_I),    .do_a(WB_BDDataOut),
 
  .clk_b(WB_CLK_I),   .rst_b(Reset),         .ce_b(EnableRAM),   .we_b(BDStatusWrite),
  .oe_b(EnableRAM),   .addr_b(BDAddress[7:0]),  .di_b(BDDataIn),    .do_b(BDDataOut)
);
*/
 
 
 
RAMB4_S16 ram1 (.DO(ram_do[15:0]),  .ADDR(ram_addr), .DI(ram_di[15:0]),  .EN(ram_ce),
                .CLK(WB_CLK_I),     .WE(ram_we),     .RST(Reset));
RAMB4_S16 ram2 (.DO(ram_do[31:16]), .ADDR(ram_addr), .DI(ram_di[31:16]), .EN(ram_ce),
                .CLK(WB_CLK_I),     .WE(ram_we),     .RST(Reset));
 
 
 
/*
generic_spram #(8, 32) ram (
        // Generic synchronous single-port RAM interface
        .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
);
*/
assign ram_ce = 1'b1;
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);     // Tu manjka se read kadar se bere RxBD
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxEn_needed <=#Tp 1'b0;
  else
  if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
    TxEn_needed <=#Tp 1'b1;
  else
  if(TxPointerRead & TxEn & TxEn_q)
    TxEn_needed <=#Tp 1'b0;
end
 
 
reg [3:0] debug;
 
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    begin
      WbEn <=#Tp 1'b1;
      RxEn <=#Tp 1'b0;
      TxEn <=#Tp 1'b0;
      ram_addr <=#Tp 8'h0;
      ram_di <=#Tp 32'h0;
 debug <=#Tp 4'h0;
    end
  else
    begin
      // Switching between three stages depends on enable signals
      casex ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})  // synopsys parallel_case
        5'b100_1x :
          begin
            WbEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b1;  // wb access stage and r_RxEn is enabled
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp RxBDAddress + RxPointerRead;
            ram_di <=#Tp RxBDDataIn;
 debug <=#Tp 4'h1;
          end
        5'b100_01 :
          begin
            WbEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b1;  // wb access stage, r_RxEn is disabled but r_TxEn is enabled
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
            ram_di <=#Tp TxBDDataIn;
 debug <=#Tp 4'h2;
          end
        5'b010_x0 :
          begin
            WbEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is disabled
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDRead <=#Tp BDCs & ~WB_WE_I;
 debug <=#Tp 4'h3;
          end
        5'b010_x1 :
          begin
            WbEn <=#Tp 1'b0;
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b1;  // RxEn access stage and r_TxEn is enabled
            ram_addr <=#Tp TxBDAddress + TxPointerRead;
            ram_di <=#Tp TxBDDataIn;
 debug <=#Tp 4'h4;
          end
        5'b001_xx :
          begin
            WbEn <=#Tp 1'b1;  // TxEn access stage (we always go to wb access stage)
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDRead <=#Tp BDCs & ~WB_WE_I;
 debug <=#Tp 4'h5;
          end
        5'b100_00 :
          begin
            WbEn <=#Tp 1'b0;  // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
 debug <=#Tp 4'h6;
          end
        5'b000_00 :
          begin
            WbEn <=#Tp 1'b1;  // Idle state. We go to WbEn access stage.
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDRead <=#Tp BDCs & ~WB_WE_I;
 debug <=#Tp 4'h7;
          end
        default :
          begin
            WbEn <=#Tp 1'b1;  // We go to wb access stage
            RxEn <=#Tp 1'b0;
            TxEn <=#Tp 1'b0;
            ram_addr <=#Tp WB_ADR_I[9:2];
            ram_di <=#Tp WB_DAT_I;
            BDWrite <=#Tp BDCs & WB_WE_I;
            BDRead <=#Tp BDCs & ~WB_WE_I;
 debug <=#Tp 4'h8;
          end
      endcase
    end
end
 
 
// Delayed stage signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    begin
      WbEn_q <=#Tp 1'b0;
      RxEn_q <=#Tp 1'b0;
      TxEn_q <=#Tp 1'b0;
    end
  else
    begin
      WbEn_q <=#Tp WbEn;
      RxEn_q <=#Tp RxEn;
      TxEn_q <=#Tp TxEn;
    end
end
 
// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    Flop <=#Tp 1'b0;
  else
  if(TxDone | TxAbort | TxRetry_q)
    Flop <=#Tp 1'b0;
  else
  if(TxUsedData)
    Flop <=#Tp ~Flop;
end
 
wire ResetTxBDReady;
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
 
// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxBDReady <=#Tp 1'b0;
  else
  if(TxEn & TxEn_q & TxBDRead)
    TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
  else                                                // Only packets larger then 4 bytes are transmitted.
  if(ResetTxBDReady)
    TxBDReady <=#Tp 1'b0;
end
 
 
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetry_wb | TxStatusWrite) & ~BlockingTxBDRead;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxBDRead <=#Tp 1'b1;
  else
  if(StartTxBDRead)
    TxBDRead <=#Tp 1'b1;
  else
  if(TxBDReady)
    TxBDRead <=#Tp 1'b0;
end
 
 
// Reading Tx BD pointer
assign StartTxPointerRead = TxBDRead & TxBDReady;
 
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxPointerRead <=#Tp 1'b0;
  else
  if(StartTxPointerRead)
    TxPointerRead <=#Tp 1'b1;
  else
  if(TxEn_q)
    TxPointerRead <=#Tp 1'b0;
end
 
 
// Writing status back to the Tx buffer descriptor
assign TxStatusWrite = (TxDone_wb | TxAbort_wb) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
 
 
 
// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockingTxStatusWrite <=#Tp 1'b0;
  else
  if(TxStatusWrite)
    BlockingTxStatusWrite <=#Tp 1'b1;
  else
  if(~TxDone_wb & ~TxAbort_wb)
    BlockingTxStatusWrite <=#Tp 1'b0;
end
 
 
// TxBDRead state is activated only once. 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockingTxBDRead <=#Tp 1'b0;
  else
  if(StartTxBDRead)
    BlockingTxBDRead <=#Tp 1'b1;
  else
  if(TxStartFrm_wb)
    BlockingTxBDRead <=#Tp 1'b0;
end
 
 
// Latching status from the tx buffer descriptor
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxStatus <=#Tp 15'h0;
  else
  if(TxEn & TxEn_q & TxBDRead)
    TxStatus <=#Tp ram_do[15:0];
end
 
reg ReadTxDataFromMemory;
wire WriteRxDataToMemory;
 
reg MasterWbTX;
reg MasterWbRX;
 
reg [31:0] m_wb_adr_o;
reg        m_wb_cyc_o;
reg        m_wb_stb_o;
reg        m_wb_we_o;
 
wire TxLengthEq0;
wire TxLengthLt4;
 
 
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxLength <=#Tp 16'h0;
  else
  if(TxEn & TxEn_q & TxBDRead)
    TxLength <=#Tp ram_do[31:16];
  else
  if(MasterWbTX & m_wb_ack_i)
    begin
      if(TxLengthLt4)
        TxLength <=#Tp 16'h0;
      else
        TxLength <=#Tp TxLength - 3'h4;    // Length is subtracted at the data request
    end
end
 
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
 
 
reg BlockingIncrementTxPointer;
 
reg [31:0] TxPointer;
reg [31:0] RxPointer;
 
//Latching Tx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxPointer <=#Tp 0;
  else
  if(TxEn & TxEn_q & TxPointerRead)
    TxPointer <=#Tp ram_do;
  else
  if(MasterWbTX & ~BlockingIncrementTxPointer)
    TxPointer <=#Tp TxPointer + 4;    // Pointer increment
end
 
wire MasterAccessFinished;
 
 
//Latching Tx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockingIncrementTxPointer <=#Tp 0;
  else
  if(MasterAccessFinished)
    BlockingIncrementTxPointer <=#Tp 0;
  else
  if(MasterWbTX)
    BlockingIncrementTxPointer <=#Tp 1'b1;
end
 
 
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire ResetReadTxDataFromMemory;
wire SetReadTxDataFromMemory;
 
reg BlockReadTxDataFromMemory;
 
assign ResetReadTxDataFromMemory = (TxLengthEq0) | TxAbortPulse | TxRetryPulse;
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromMemory <=#Tp 1'b0;
  else
  if(ResetReadTxDataFromMemory)
    ReadTxDataFromMemory <=#Tp 1'b0;
  else
  if(SetReadTxDataFromMemory)
    ReadTxDataFromMemory <=#Tp 1'b1;
end
 
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockReadTxDataFromMemory <=#Tp 1'b0;
  else
  if(ReadTxDataFromFifo_wb)
    BlockReadTxDataFromMemory <=#Tp 1'b0;
  else
  if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX)
    BlockReadTxDataFromMemory <=#Tp 1'b1;
end
 
 
 
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
 
assign m_wb_sel_o = 4'hf;
 
 
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    begin
      MasterWbTX <=#Tp 1'b0;
      MasterWbRX <=#Tp 1'b0;
      m_wb_adr_o <=#Tp 32'h0;
      m_wb_cyc_o <=#Tp 1'b0;
      m_wb_stb_o <=#Tp 1'b0;
      m_wb_we_o  <=#Tp 1'b0;
    end
  else
    begin
      // Switching between two stages depends on enable signals
      casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished})  // synopsys parallel_case full_case
        5'b00_x1_x :
          begin
            MasterWbTX <=#Tp 1'b0;  // idle and master write is needed (data write to rx buffer)
            MasterWbRX <=#Tp 1'b1;
            m_wb_adr_o <=#Tp RxPointer;
            m_wb_cyc_o <=#Tp 1'b1;
            m_wb_stb_o <=#Tp 1'b1;
            m_wb_we_o  <=#Tp 1'b1;
          end
        5'b00_10_x :
          begin
            MasterWbTX <=#Tp 1'b1;  // idle and master read is needed (data read from tx buffer)
            MasterWbRX <=#Tp 1'b0;
            m_wb_adr_o <=#Tp TxPointer;
            m_wb_cyc_o <=#Tp 1'b1;
            m_wb_stb_o <=#Tp 1'b1;
            m_wb_we_o  <=#Tp 1'b0;
          end
        5'b10_10_1 :
          begin
            MasterWbTX <=#Tp 1'b1;  // master read and master read is needed (data read from tx buffer)
            MasterWbRX <=#Tp 1'b0;
            m_wb_adr_o <=#Tp TxPointer;
            m_wb_cyc_o <=#Tp 1'b1;
            m_wb_stb_o <=#Tp 1'b1;
            m_wb_we_o  <=#Tp 1'b0;
          end
        5'b01_01_1 :
          begin
            MasterWbTX <=#Tp 1'b0;  // master write and master write is needed (data write to rx buffer)
            MasterWbRX <=#Tp 1'b1;
            m_wb_adr_o <=#Tp RxPointer;
            m_wb_we_o  <=#Tp 1'b1;
          end
        5'b10_x1_1 :
          begin
            MasterWbTX <=#Tp 1'b0;  // master read and master write is needed (data write to rx buffer)
            MasterWbRX <=#Tp 1'b1;
            m_wb_adr_o <=#Tp RxPointer;
            m_wb_we_o  <=#Tp 1'b1;
          end
        5'b01_1x_1 :
          begin
            MasterWbTX <=#Tp 1'b1;  // master write and master read is needed (data read from tx buffer)
            MasterWbRX <=#Tp 1'b0;
            m_wb_adr_o <=#Tp TxPointer;
            m_wb_we_o  <=#Tp 1'b0;
          end
        5'bxx_00_1 :
          begin
            MasterWbTX <=#Tp 1'b0;  // whatever and no master read or write is needed (ack or err comes finishing previous access)
            MasterWbRX <=#Tp 1'b0;
            m_wb_cyc_o <=#Tp 1'b0;
            m_wb_stb_o <=#Tp 1'b0;
          end
      endcase
    end
end
 
wire TxFifoClear;
assign TxFifoClear = (TxAbort_wb | TxRetry_wb) & ~TxBDReady;
 
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
tx_fifo (.data_in(m_wb_dat_i),               .data_out(TxData_wb),            .clk(WB_CLK_I),
         .reset(Reset),                   .write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb),
         .clear(TxFifoClear),                .full(TxBufferFull),             .almost_full(TxBufferAlmostFull),
         .almost_empty(TxBufferAlmostEmpty), .empty(TxBufferEmpty));
 
 
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
 
 
 
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxStartFrm_wb <=#Tp 1'b0;
  else
  if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
    TxStartFrm_wb <=#Tp 1'b1;
  else
  if(TxStartFrm_syncb2)
    TxStartFrm_wb <=#Tp 1'b0;
end
 
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    StartOccured <=#Tp 1'b0;
  else
  if(TxStartFrm_wb)
    StartOccured <=#Tp 1'b1;
  else
  if(ResetTxBDReady)
    StartOccured <=#Tp 1'b0;
end
 
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxStartFrm_sync1 <=#Tp 1'b0;
  else
    TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
end
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxStartFrm_sync2 <=#Tp 1'b0;
  else
    TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxStartFrm_syncb1 <=#Tp 1'b0;
  else
    TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxStartFrm_syncb2 <=#Tp 1'b0;
  else
    TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
end
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxStartFrm <=#Tp 1'b0;
  else
  if(TxStartFrm_sync2)
    TxStartFrm <=#Tp 1'b1;      // igor !!! Dodaj se pogoj, da ni vmes prisel kaksen abort ali kaj podobnega
  else
  if(TxUsedData_q)
    TxStartFrm <=#Tp 1'b0;
end
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
 
 
// TxEndFrm_wb: indicator of the end of frame
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxEndFrm_wb <=#Tp 1'b0;
  else
  if(TxLengthLt4 & TxBufferAlmostEmpty & TxUsedData)
    TxEndFrm_wb <=#Tp 1'b1;
  else
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
    TxEndFrm_wb <=#Tp 1'b0;
end
 
 
// Marks which bytes are valid within the word.
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
 
reg LatchValidBytes;
reg LatchValidBytes_q;
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    LatchValidBytes <=#Tp 1'b0;
  else
  if(TxLengthLt4 & TxBDReady)
    LatchValidBytes <=#Tp 1'b1;
  else
    LatchValidBytes <=#Tp 1'b0;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    LatchValidBytes_q <=#Tp 1'b0;
  else
    LatchValidBytes_q <=#Tp LatchValidBytes;
end
 
 
// Latching valid bytes
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxValidBytesLatched <=#Tp 2'h0;
  else
  if(LatchValidBytes & ~LatchValidBytes_q)
    TxValidBytesLatched <=#Tp TxValidBytes;
  else
  if(TxRetryPulse | TxDonePulse | TxAbortPulse)
    TxValidBytesLatched <=#Tp 2'h0;
end
 
 
// Bit 14 is used as a wrap bit. When active it indicates the last buffer descriptor in a row. After
// using this descriptor, first BD will be used again.
 
// TX
// bit 15 od tx je ready
// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
// bit 13 od tx je wrap
// bit 12 od tx je pad
// bit 11 od tx je crc
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9  od tx je pause request (control frame)
    // Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8  od tx je defer indication
// bit 7  od tx je late collision
// bit 6  od tx je retransmittion limit
// bit 5  od tx je underrun
// bit 4  od tx je carrier sense lost
// bit [3:0] od tx je retry count
 
//assign TxBDReady      = TxStatus[15];     // already used
assign TxIRQEn          = TxStatus[14];
assign WrapTxStatusBit  = TxStatus[13];                                                   // ok povezan
assign PerPacketPad     = TxStatus[12];                                                   // ok povezan
assign PerPacketCrcEn   = TxStatus[11] & TxStatus[10];      // When last is also set      // ok povezan
//assign TxPauseRq      = TxStatus[9];      // already used     Ta gre ven, ker bo stvar izvedena preko registrov
 
 
 
// RX
// bit 15 od rx je empty
// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
// bit 13 od rx je wrap
// bit 12 od rx je reserved
// bit 11 od rx je reserved
// bit 10 od rx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9  od rx je pause request (control frame)
    // Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8  od rx je defer indication
// bit 7  od rx je late collision
// bit 6  od rx je retransmittion limit
// bit 5  od rx je underrun
// bit 4  od rx je carrier sense lost
// bit [3:0] od rx je retry count
 
assign WrapRxStatusBit = RxStatus[13];
 
 
// Temporary Tx and Rx buffer descriptor address 
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite     & ~WrapTxStatusBit}} & (TxBDAddress + 2'h2) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum)       | // Using first Rx BD
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 2'h2) ; // Using next Rx BD (incremenrement address)
 
 
// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxBDAddress <=#Tp 8'h0;
  else
  if(TxStatusWrite)
    TxBDAddress <=#Tp TempTxBDAddress;
end
 
 
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxBDAddress <=#Tp 8'h0;
  else
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also igor !!! ta del bi se lahko popravil
    RxBDAddress <=#Tp WB_DAT_I[7:0];
  else
  if(RxStatusWrite)
    RxBDAddress <=#Tp TempRxBDAddress;
end
 
assign NewRxStatus[15:0] = 16'hdead;
 
 
assign RxBDDataIn = {RxLength, NewRxStatus};  // tu dopolni, da se bo vpisoval status
assign TxBDDataIn = {32'h004380ef};   // tu dopolni, da se bo vpisoval status
 
 
// Signals used for various purposes
assign TxRetryPulse   = TxRetry_wb   & ~TxRetry_wb_q;
assign TxDonePulse    = TxDone_wb    & ~TxDone_wb_q;
assign TxAbortPulse   = TxAbort_wb   & ~TxAbort_wb_q;
 
 
// assign ClearTxBDReady = ~TxUsedData & TxUsedData_q;
 
assign TPauseRq = 0; // igor !!! v koncni fazi mora tu biti pause request
assign TxPauseTV[15:0] = TxLength[15:0]; // igor !!! v koncni fazi mora tu biti pause request
 
 
// Generating delayed signals
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    begin
      TxAbort_q      <=#Tp 1'b0;
      TxRetry_q      <=#Tp 1'b0;
      TxUsedData_q   <=#Tp 1'b0;
    end
  else
    begin
      TxAbort_q      <=#Tp TxAbort;
      TxRetry_q      <=#Tp TxRetry;
      TxUsedData_q   <=#Tp TxUsedData;
    end
end
 
// Generating delayed signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    begin
      TxDone_wb_q   <=#Tp 1'b0;
      TxAbort_wb_q  <=#Tp 1'b0;
      TxRetry_wb_q  <=#Tp 1'b0;
    end
  else
    begin
      TxDone_wb_q   <=#Tp TxDone_wb;
      TxAbort_wb_q  <=#Tp TxAbort_wb;
      TxRetry_wb_q  <=#Tp TxRetry_wb;
    end
end
 
 
// Sinchronizing and evaluating tx data
//assign SetGotData = (TxStartFrm_wb | NewTxDataAvaliable_wb & ~TxAbort_wb & ~TxRetry_wb) & ~WB_CLK_I;
assign SetGotData = (TxStartFrm_wb); // igor namesto zgornje
 
// Evaluating data. If abort or retry occured meanwhile than data is ignored.
//assign GotDataEvaluate = GotDataSync3 & ~GotData & (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
assign GotDataEvaluate = (~TxRetry & ~TxAbort | (TxRetry | TxAbort) & (TxStartFrm));
 
 
// Indication of the last word
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    LastWord <=#Tp 1'b0;
  else
  if((TxEndFrm | TxAbort | TxRetry) & Flop)
    LastWord <=#Tp 1'b0;
  else
  if(TxUsedData & Flop & TxByteCnt == 2'h3)
    LastWord <=#Tp TxEndFrm_wb;
end
 
 
// Tx end frame generation
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxEndFrm <=#Tp 1'b0;
  else
  if(Flop & TxEndFrm | TxAbort | TxRetry_q)     // igor !!! zakaj je tu TxRetry_q ?
    TxEndFrm <=#Tp 1'b0;
  else
  if(Flop & LastWord)
    begin
      case (TxValidBytesLatched)
        1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
        2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
        3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
 
        default : TxEndFrm <=#Tp 1'b0;
      endcase
    end
end
 
 
// Tx data selection (latching)
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxData <=#Tp 8'h0;
  else
  if(TxStartFrm_sync2 & ~TxStartFrm)
    TxData <=#Tp TxData_wb[7:0];
  else
  if(TxUsedData & Flop)
    begin
      case(TxByteCnt)
 
        1 : TxData <=#Tp TxDataLatched[15:8];
        2 : TxData <=#Tp TxDataLatched[23:16];
        3 : TxData <=#Tp TxDataLatched[31:24];
      endcase
    end
end
 
 
// Latching tx data
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxDataLatched[31:0] <=#Tp 32'h0;
  else
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3)
    TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
end
 
 
// Tx under run
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxUnderRun <=#Tp 1'b0;
  else
  if(TxAbortPulse)
    TxUnderRun <=#Tp 1'b0;
  else
  if(TxBufferEmpty & ReadTxDataFromFifo_wb)
    TxUnderRun <=#Tp 1'b1;
end
 
 
 
// Tx Byte counter
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    TxByteCnt <=#Tp 2'h0;
  else
  if(TxAbort_q | TxRetry_q)
    TxByteCnt <=#Tp 2'h0;
  else
  if(TxStartFrm & ~TxUsedData)
    TxByteCnt <=#Tp 2'h1;
  else
  if(TxUsedData & Flop)
    TxByteCnt <=#Tp TxByteCnt + 1;
end
 
 
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
reg ReadTxDataFromFifo_sync1;
reg ReadTxDataFromFifo_sync2;
reg ReadTxDataFromFifo_sync3;
reg ReadTxDataFromFifo_syncb1;
reg ReadTxDataFromFifo_syncb2;
 
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
  else
  if(ReadTxDataFromFifo_syncb2)
    ReadTxDataFromFifo_tck <=#Tp 1'b0;
  else
  if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord)
     ReadTxDataFromFifo_tck <=#Tp 1'b1;
end
 
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
end
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
end
 
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
  else
    ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
end
 
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
 
 
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxRetrySync1 <=#Tp 1'b0;
  else
    TxRetrySync1 <=#Tp TxRetry;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxRetry_wb <=#Tp 1'b0;
  else
    TxRetry_wb <=#Tp TxRetrySync1;
end
 
 
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxDoneSync1 <=#Tp 1'b0;
  else
    TxDoneSync1 <=#Tp TxDone;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxDone_wb <=#Tp 1'b0;
  else
    TxDone_wb <=#Tp TxDoneSync1;
end
 
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxAbortSync1 <=#Tp 1'b0;
  else
    TxAbortSync1 <=#Tp TxAbort;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxAbort_wb <=#Tp 1'b0;
  else
    TxAbort_wb <=#Tp TxAbortSync1;
end
 
 
assign StartRxBDRead = RxStatusWrite | RxAbort;
 
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxBDRead <=#Tp 1'b1;
  else
  if(StartRxBDRead)
    RxBDRead <=#Tp 1'b1;
  else
  if(RxBDReady)
    RxBDRead <=#Tp 1'b0;
end
 
 
// Reading of the next receive buffer descriptor starts after reception status is
// written to the previous one.
 
// Latching READY status of the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxBDReady <=#Tp 1'b0;
  else
  if(RxEn & RxEn_q & RxBDRead)
    RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
  else
  if(ShiftEnded | RxAbort)   // igor !!! tx del ima tu ResetTxBDReady
    RxBDReady <=#Tp 1'b0;
end
 
// Latching Rx buffer descriptor status
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxStatus <=#Tp 16'h0;
  else
  if(RxEn & RxEn_q & RxBDRead)
    RxStatus <=#Tp ram_do[15:0];
end
 
 
 
 
// Reading Rx BD pointer
 
 
assign StartRxPointerRead = RxBDRead & RxBDReady;
 
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxPointerRead <=#Tp 1'b0;
  else
  if(StartRxPointerRead)
    RxPointerRead <=#Tp 1'b1;
  else
  if(RxEn_q)
    RxPointerRead <=#Tp 1'b0;
end
 
reg BlockingIncrementRxPointer;
//Latching Rx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxPointer <=#Tp 32'h0;
  else
  if(RxEn & RxEn_q & RxPointerRead)
    RxPointer <=#Tp ram_do;
  else
  if(MasterWbRX & ~BlockingIncrementRxPointer)
    RxPointer <=#Tp RxPointer + 4;    // Pointer increment
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    BlockingIncrementRxPointer <=#Tp 0;
  else
  if(MasterAccessFinished)
    BlockingIncrementRxPointer <=#Tp 0;
  else
  if(MasterWbRX)
    BlockingIncrementRxPointer <=#Tp 1'b1;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxEn_needed <=#Tp 1'b0;
  else
  if(~RxBDReady & r_RxEn & WbEn & ~WbEn_q)
    RxEn_needed <=#Tp 1'b1;
  else
  if(RxPointerRead & RxEn & RxEn_q)
    RxEn_needed <=#Tp 1'b0;
end
 
 
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
 
reg RxEnableWindow;
 
// Indicating that last byte is being reveived
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LastByteIn <=#Tp 1'b0;
  else
  if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
    LastByteIn <=#Tp 1'b0;
  else
  if(RxValid & RxBDReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
    LastByteIn <=#Tp 1'b1;
end
 
reg ShiftEnded_tck;
reg ShiftEndedSync1;
reg ShiftEndedSync2;
wire StartShiftWillEnd;
assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
 
// Indicating that data reception will end
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShiftWillEnd <=#Tp 1'b0;
  else
  if(ShiftEnded_tck | RxAbort)
    ShiftWillEnd <=#Tp 1'b0;
  else
  if(StartShiftWillEnd)
    ShiftWillEnd <=#Tp 1'b1;
end
 
 
 
// Receive byte counter
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxByteCnt <=#Tp 2'h0;
  else
  if(ShiftEnded_tck | RxAbort)
    RxByteCnt <=#Tp 2'h0;
  else
  if(RxValid & (RxStartFrm | RxEnableWindow) & RxBDReady | LastByteIn)
    RxByteCnt <=#Tp RxByteCnt + 1'b1;
end
 
 
// Indicates how many bytes are valid within the last word
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxValidBytes <=#Tp 2'h1;
  else
  if(ShiftEnded_tck | RxAbort)
    RxValidBytes <=#Tp 2'h1;
  else
  if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
    RxValidBytes <=#Tp RxValidBytes + 1;
end
 
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxDataLatched1       <=#Tp 24'h0;
  else
  if(RxValid & RxBDReady & ~LastByteIn & (RxStartFrm | RxEnableWindow))
    begin
      case(RxByteCnt)     // synopsys parallel_case
        2'h0:        RxDataLatched1[7:0]   <=#Tp RxData;
        2'h1:        RxDataLatched1[15:8]  <=#Tp RxData;
        2'h2:        RxDataLatched1[23:16] <=#Tp RxData;
        2'h3:        RxDataLatched1        <=#Tp RxDataLatched1;
      endcase
    end
end
 
wire SetWriteRxDataToFifo;
 
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxDataLatched2 <=#Tp 32'h0;
  else
  if(SetWriteRxDataToFifo & ~ShiftWillEnd)
    RxDataLatched2 <=#Tp {RxData, RxDataLatched1[23:0]};
  else
  if(SetWriteRxDataToFifo & ShiftWillEnd)
    case(RxValidBytes)
 
      1 : RxDataLatched2 <=#Tp { 24'h0, RxDataLatched1[7:0]};
      2 : RxDataLatched2 <=#Tp { 16'h0, RxDataLatched1[15:0]};
      3 : RxDataLatched2 <=#Tp {  8'h0, RxDataLatched1[23:0]};
    endcase
end
 
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxLength <=#Tp 16'h0;
  else
  if(RxStartFrm)
    RxLength <=#Tp 16'h1;
  else
  if(RxValid & (RxStartFrm | RxEnableWindow))
    RxLength <=#Tp RxLength + 1'b1;
end
 
 
reg WriteRxDataToFifoSync1;
reg WriteRxDataToFifoSync2;
 
 
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifo <=#Tp 1'b0;
  else
  if(SetWriteRxDataToFifo & ~RxAbort)
    WriteRxDataToFifo <=#Tp 1'b1;
  else
  if(WriteRxDataToFifoSync1 | RxAbort)
    WriteRxDataToFifo <=#Tp 1'b0;
end
 
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
  else
  if(WriteRxDataToFifo)
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
  else
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
  else
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
end
 
wire WriteRxDataToFifo_wb;
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync1 & ~WriteRxDataToFifoSync2;
 
reg RxAbortLatched;
reg RxAbortSync1;
reg RxAbortSync2;
reg RxAbortSyncb1;
reg RxAbortSyncb2;
 
 
eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
rx_fifo (.data_in(RxDataLatched2),        .data_out(m_wb_dat_o),        .clk(WB_CLK_I),
         .reset(Reset),                   .write(WriteRxDataToFifo_wb), .read(MasterWbRX & m_wb_ack_i),
         .clear(RxAbortSync2),            .full(RxBufferFull),          .almost_full(RxBufferAlmostFull),
         .almost_empty(RxBufferAlmostEmpty), .empty(RxBufferEmpty));
 
assign WriteRxDataToMemory = ~RxBufferEmpty & (~MasterWbRX | ~RxBufferAlmostEmpty);
 
 
 
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShiftEnded_tck <=#Tp 1'b0;
  else
  if(SetWriteRxDataToFifo & StartShiftWillEnd & ~RxAbort)
    ShiftEnded_tck <=#Tp 1'b1;
  else
  if(ShiftEndedSync2 | RxAbort)
    ShiftEnded_tck <=#Tp 1'b0;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync1 <=#Tp 1'b0;
  else
    ShiftEndedSync1 <=#Tp ShiftEnded_tck;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync2 <=#Tp 1'b0;
  else
  if(ShiftEndedSync1)
    ShiftEndedSync2 <=#Tp 1'b1;
  else
  if(ShiftEnded)
    ShiftEndedSync2 <=#Tp 1'b0;
end
 
 
// Generation of the end-of-frame signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEnded <=#Tp 1'b0;
  else
  if(ShiftEndedSync2 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty)
    ShiftEnded <=#Tp 1'b1;
  else
  if(RxStatusWrite)
    ShiftEnded <=#Tp 1'b0;
end
 
 
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxEnableWindow <=#Tp 1'b0;
  else
  if(RxStartFrm)
    RxEnableWindow <=#Tp 1'b1;
  else
  if(RxEndFrm | RxAbort)
    RxEnableWindow <=#Tp 1'b0;
end
 
 
 
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxAbortLatched <=#Tp 1'b0;
  else
  if(RxAbort)
    RxAbortLatched <=#Tp 1'b1;
  else
  if(RxAbortSyncb2 | RxStartFrm)
    RxAbortLatched <=#Tp 1'b0;
end
 
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync1 <=#Tp 1'b0;
  else
    RxAbortSync1 <=#Tp RxAbort;
end
 
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync2 <=#Tp 1'b0;
  else
    RxAbortSync2 <=#Tp RxAbortSync1;
end
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxAbortSyncb1 <=#Tp 1'b0;
  else
    RxAbortSyncb1 <=#Tp RxAbortSync2;
end
 
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxAbortSyncb2 <=#Tp 1'b0;
  else
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
end
 
 
 
 
 
 
// Interrupts
assign TxB_IRQ = 1'b0;
assign TxE_IRQ = 1'b0;
assign RxB_IRQ = 1'b0;
assign RxF_IRQ = 1'b0;
assign Busy_IRQ = 1'b0;
 
 
endmodule
 

Line No.	Rev	Author	Line
1	38	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_wishbone.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	40	mohor	`// Revision 1.2 2002/02/01 12:46:51 mohor`
45			`// Tx part finished. TxStatus needs to be fixed. Pause request needs to be`
46			`// added.`
47			`//`
48	39	mohor	`// Revision 1.1 2002/01/23 10:47:59 mohor`
49			`// Initial version. Equals to eth_wishbonedma.v at this moment.`
50	38	mohor	`//`
51			`//`
52			`//`
53	39	mohor	`//`
54	38	mohor
55	40	mohor	`// igor !!!`
56			`// Napravi, pause frame`
57	38	mohor
58	40	mohor	`// Poskusi spremeniti vse signale na wb strani da bodo imeli enake koncnice (npr _wb),`
59			`// vsi na MTxClk strani pa _txclk`
60			`// Evaluiraj dato da pre start framom ni prisel abort ali kaj podobnega (kot je bilo v GotData, ki ga zbrisi)`
61
62			`// Naj m_wb_err_i vzge status underrun ali uverrun`
63
64	38	mohor	`include "eth_defines.v"
65			`include "timescale.v"
66
67
68			`module eth_wishbone`
69			`(`
70
71			`// WISHBONE common`
72	40	mohor	`WB_CLK_I, WB_DAT_I, WB_DAT_O,`
73	38	mohor
74			`// WISHBONE slave`
75			`WB_ADR_I, WB_SEL_I, WB_WE_I, WB_ACK_O,`
76	40	mohor	`BDCs,`
77	38	mohor
78	40	mohor	`Reset,`
79
80	39	mohor	`// WISHBONE master`
81			`m_wb_adr_o, m_wb_sel_o, m_wb_we_o,`
82			`m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,`
83			`m_wb_stb_o, m_wb_ack_i, m_wb_err_i,`
84
85	38	mohor	`//TX`
86			`MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, StatusIzTxEthMACModula,`
87			`TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn,`
88			`PerPacketPad,`
89
90			`//RX`
91	40	mohor	`MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,`
92	38	mohor
93			`// Register`
94			`r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr,`
95
96	39	mohor	`WillSendControlFrame, TxCtrlEndFrm, // igor !!! WillSendControlFrame gre najbrz ven`
97	38	mohor
98			`// Interrupts`
99			`TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ`
100
101			`);`
102
103
104			`parameter Tp = 1;`
105
106			`// WISHBONE common`
107			`input WB_CLK_I; // WISHBONE clock`
108			`input [31:0] WB_DAT_I; // WISHBONE data input`
109			`output [31:0] WB_DAT_O; // WISHBONE data output`
110
111			`// WISHBONE slave`
112			`input [9:2] WB_ADR_I; // WISHBONE address input`
113			`input [3:0] WB_SEL_I; // WISHBONE byte select input`
114			`input WB_WE_I; // WISHBONE write enable input`
115			`input BDCs; // Buffer descriptors are selected`
116			`output WB_ACK_O; // WISHBONE acknowledge output`
117
118	39	mohor	`// WISHBONE master`
119			`output [31:0] m_wb_adr_o; //`
120			`output [3:0] m_wb_sel_o; //`
121			`output m_wb_we_o; //`
122			`output [31:0] m_wb_dat_o; //`
123			`output m_wb_cyc_o; //`
124			`output m_wb_stb_o; //`
125			`input [31:0] m_wb_dat_i; //`
126			`input m_wb_ack_i; //`
127			`input m_wb_err_i; //`
128
129	40	mohor	`input Reset; // Reset signal`
130	39	mohor
131
132
133	38	mohor	`// DMA`
134	40	mohor	`// input [1:0] WB_ACK_I; // DMA acknowledge input`
135			`// output [1:0] WB_REQ_O; // DMA request output`
136			`// output [1:0] WB_ND_O; // DMA force new descriptor output`
137			`// output WB_RD_O; // DMA restart descriptor output`
138	38	mohor
139			`// Tx`
140			`input MTxClk; // Transmit clock (from PHY)`
141			`input TxUsedData; // Transmit packet used data`
142			`input [15:0] StatusIzTxEthMACModula;`
143			`input TxRetry; // Transmit packet retry`
144			`input TxAbort; // Transmit packet abort`
145			`input TxDone; // Transmission ended`
146			`output TxStartFrm; // Transmit packet start frame`
147			`output TxEndFrm; // Transmit packet end frame`
148			`output [7:0] TxData; // Transmit packet data byte`
149			`output TxUnderRun; // Transmit packet under-run`
150			`output PerPacketCrcEn; // Per packet crc enable`
151			`output PerPacketPad; // Per packet pading`
152			`output TPauseRq; // Tx PAUSE control frame`
153			`output [15:0] TxPauseTV; // PAUSE timer value`
154			`input WillSendControlFrame;`
155			`input TxCtrlEndFrm;`
156
157			`// Rx`
158			`input MRxClk; // Receive clock (from PHY)`
159			`input [7:0] RxData; // Received data byte (from PHY)`
160			`input RxValid; //`
161			`input RxStartFrm; //`
162			`input RxEndFrm; //`
163	40	mohor	`input RxAbort; // This signal is set when address doesn't match.`
164	38	mohor
165			`//Register`
166			`input r_TxEn; // Transmit enable`
167			`input r_RxEn; // Receive enable`
168			`input [7:0] r_TxBDNum; // Receive buffer descriptor number`
169			`input r_DmaEn; // DMA enable`
170			`input TX_BD_NUM_Wr; // RxBDNumber written`
171
172			`// Interrupts`
173			`output TxB_IRQ;`
174			`output TxE_IRQ;`
175			`output RxB_IRQ;`
176			`output RxF_IRQ;`
177			`output Busy_IRQ;`
178
179			`reg TxStartFrm;`
180			`reg TxEndFrm;`
181			`reg [7:0] TxData;`
182
183			`reg TxUnderRun;`
184
185			`reg TxBDRead;`
186	39	mohor	`wire TxStatusWrite;`
187	38	mohor
188			`reg [1:0] TxValidBytesLatched;`
189
190			`reg [15:0] TxLength;`
191	39	mohor	`reg [15:0] TxStatus;`
192	38	mohor
193			`reg [15:0] RxStatus;`
194
195			`reg TxStartFrm_wb;`
196			`reg TxRetry_wb;`
197	39	mohor	`reg TxAbort_wb;`
198	38	mohor	`reg TxDone_wb;`
199
200			`reg TxDone_wb_q;`
201			`reg TxAbort_wb_q;`
202	39	mohor	`reg TxRetry_wb_q;`
203	38	mohor	`reg RxBDReady;`
204			`reg TxBDReady;`
205
206			`reg RxBDRead;`
207	40	mohor	`wire RxStatusWrite;`
208	38	mohor
209			`reg [31:0] TxDataLatched;`
210			`reg [1:0] TxByteCnt;`
211			`reg LastWord;`
212	39	mohor	`reg ReadTxDataFromFifo_tck;`
213	38	mohor
214			`reg BlockingTxStatusWrite;`
215			`reg BlockingTxBDRead;`
216
217	40	mohor	`reg Flop;`
218	38	mohor
219			`reg [7:0] TxBDAddress;`
220			`reg [7:0] RxBDAddress;`
221
222			`reg TxRetrySync1;`
223			`reg TxAbortSync1;`
224	39	mohor	`reg TxDoneSync1;`
225	38	mohor
226			`reg TxAbort_q;`
227			`reg TxRetry_q;`
228			`reg TxUsedData_q;`
229
230			`reg [31:0] RxDataLatched2;`
231	40	mohor	`reg [23:0] RxDataLatched1;`
232	38	mohor	`reg [1:0] RxValidBytes;`
233			`reg [1:0] RxByteCnt;`
234			`reg LastByteIn;`
235			`reg ShiftWillEnd;`
236
237	40	mohor	`reg WriteRxDataToFifo;`
238	38	mohor
239	40	mohor	`reg ShiftEnded;`
240	38	mohor
241	40	mohor	`reg BDWrite; // BD Write Enable for access from WISHBONE side`
242			`reg BDRead; // BD Read access from WISHBONE side`
243	39	mohor	`wire [31:0] RxBDDataIn; // Rx BD data in`
244			`wire [31:0] TxBDDataIn; // Tx BD data in`
245	38	mohor
246	39	mohor	`reg TxEndFrm_wb;`
247	38	mohor
248	39	mohor	`wire TxRetryPulse;`
249	38	mohor	`wire TxDonePulse;`
250			`wire TxAbortPulse;`
251
252			`wire StartRxBDRead;`
253			`wire StartRxStatusWrite;`
254
255			`wire StartTxBDRead;`
256
257			`wire TxIRQEn;`
258			`wire WrapTxStatusBit;`
259
260			`wire WrapRxStatusBit;`
261
262			`wire [1:0] TxValidBytes;`
263
264			`wire [7:0] TempTxBDAddress;`
265			`wire [7:0] TempRxBDAddress;`
266
267	40	mohor	`reg [15:0] RxLength;`
268	38	mohor	`wire [15:0] NewRxStatus;`
269
270			`wire SetGotData;`
271			`wire GotDataEvaluate;`
272
273	39	mohor	`reg temp_ack;`
274	38	mohor
275	39	mohor	`ifdef ETH_REGISTERED_OUTPUTS
276			`reg temp_ack2;`
277			`reg [31:0] registered_ram_do;`
278			`endif
279	38	mohor
280	39	mohor	`reg WbEn, WbEn_q;`
281			`reg RxEn, RxEn_q;`
282			`reg TxEn, TxEn_q;`
283	38	mohor
284	39	mohor	`wire ram_ce;`
285			`wire ram_we;`
286			`wire ram_oe;`
287			`reg [7:0] ram_addr;`
288			`reg [31:0] ram_di;`
289			`wire [31:0] ram_do;`
290	38	mohor
291	39	mohor	`wire StartTxPointerRead;`
292			`wire ResetTxPointerRead;`
293			`reg TxPointerRead;`
294			`reg TxEn_needed;`
295	40	mohor	`reg RxEn_needed;`
296	38	mohor
297	40	mohor	`wire StartRxPointerRead;`
298			`reg RxPointerRead;`
299	38	mohor
300	39	mohor
301	40	mohor	`always @ (posedge WB_CLK_I or posedge Reset)`
302			`begin`
303			`if(Reset)`
304			`begin`
305			`temp_ack <=#Tp 1'b0;`
306			`ifdef ETH_REGISTERED_OUTPUTS
307			`temp_ack2 <=#Tp 1'b0;`
308			`registered_ram_do <=#Tp 32'h0;`
309			`endif
310			`end`
311			`else`
312			`begin`
313			`temp_ack <=#Tp BDWrite & WbEn & WbEn_q \| BDRead & WbEn & ~WbEn_q;`
314			`ifdef ETH_REGISTERED_OUTPUTS
315			`temp_ack2 <=#Tp temp_ack;`
316			`registered_ram_do <=#Tp ram_do;`
317			`endif
318			`end`
319			`end`
320	39	mohor
321			`ifdef ETH_REGISTERED_OUTPUTS
322			`assign WB_ACK_O = temp_ack2;`
323			`assign WB_DAT_O = registered_ram_do;`
324			`else
325			`assign WB_ACK_O = temp_ack;`
326			`assign WB_DAT_O = ram_do;`
327			`endif
328
329
330
331
332	38	mohor	`// Generic synchronous two-port RAM interface`
333	39	mohor	`/*`
334	38	mohor	`generic_tpram #(8, 32) i_generic_tpram`
335			`(`
336	40	mohor	`.clk_a(WB_CLK_I), .rst_a(Reset), .ce_a(1'b1), .we_a(BDWrite),`
337	38	mohor	`.oe_a(EnableRAM), .addr_a(WB_ADR_I[9:2]), .di_a(WB_DAT_I), .do_a(WB_BDDataOut),`
338
339	40	mohor	`.clk_b(WB_CLK_I), .rst_b(Reset), .ce_b(EnableRAM), .we_b(BDStatusWrite),`
340	38	mohor	`.oe_b(EnableRAM), .addr_b(BDAddress[7:0]), .di_b(BDDataIn), .do_b(BDDataOut)`
341			`);`
342	39	mohor	`*/`
343	38	mohor
344
345	39	mohor
346			`RAMB4_S16 ram1 (.DO(ram_do[15:0]), .ADDR(ram_addr), .DI(ram_di[15:0]), .EN(ram_ce),`
347	40	mohor	`.CLK(WB_CLK_I), .WE(ram_we), .RST(Reset));`
348	39	mohor	`RAMB4_S16 ram2 (.DO(ram_do[31:16]), .ADDR(ram_addr), .DI(ram_di[31:16]), .EN(ram_ce),`
349	40	mohor	`.CLK(WB_CLK_I), .WE(ram_we), .RST(Reset));`
350	39	mohor
351
352
353			`/*`
354			`generic_spram #(8, 32) ram (`
355			`// Generic synchronous single-port RAM interface`
356	40	mohor	`.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)`
357	39	mohor	`);`
358			`*/`
359			`assign ram_ce = 1'b1;`
360	40	mohor	`assign ram_we = BDWrite & WbEn & WbEn_q \| TxStatusWrite \| RxStatusWrite;`
361			`assign ram_oe = BDRead & WbEn & WbEn_q \| TxEn & TxEn_q & (TxBDRead \| TxPointerRead) \| RxEn & RxEn_q & (RxBDRead \| RxPointerRead); // Tu manjka se read kadar se bere RxBD`
362	39	mohor
363
364	40	mohor	`always @ (posedge WB_CLK_I or posedge Reset)`
365	38	mohor	`begin`
366	40	mohor	`if(Reset)`
367	39	mohor	`TxEn_needed <=#Tp 1'b0;`
368	38	mohor	`else`
369	40	mohor	`if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)`
370	39	mohor	`TxEn_needed <=#Tp 1'b1;`
371			`else`
372			`if(TxPointerRead & TxEn & TxEn_q)`
373			`TxEn_needed <=#Tp 1'b0;`
374	38	mohor	`end`
375
376
377	40	mohor	`reg [3:0] debug;`
378	38	mohor
379	39	mohor	`// Enabling access to the RAM for three devices.`
380	40	mohor	`always @ (posedge WB_CLK_I or posedge Reset)`
381	39	mohor	`begin`
382	40	mohor	`if(Reset)`
383	39	mohor	`begin`
384			`WbEn <=#Tp 1'b1;`
385			`RxEn <=#Tp 1'b0;`
386			`TxEn <=#Tp 1'b0;`
387			`ram_addr <=#Tp 8'h0;`
388			`ram_di <=#Tp 32'h0;`
389	40	mohor	`debug <=#Tp 4'h0;`
390	39	mohor	`end`
391			`else`
392			`begin`
393			`// Switching between three stages depends on enable signals`
394	40	mohor	`casex ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case`
395	39	mohor	`5'b100_1x :`
396			`begin`
397			`WbEn <=#Tp 1'b0;`
398			`RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled`
399			`TxEn <=#Tp 1'b0;`
400	40	mohor	`ram_addr <=#Tp RxBDAddress + RxPointerRead;`
401	39	mohor	`ram_di <=#Tp RxBDDataIn;`
402	40	mohor	`debug <=#Tp 4'h1;`
403	39	mohor	`end`
404			`5'b100_01 :`
405			`begin`
406			`WbEn <=#Tp 1'b0;`
407			`RxEn <=#Tp 1'b0;`
408			`TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled`
409			`ram_addr <=#Tp TxBDAddress + TxPointerRead;`
410			`ram_di <=#Tp TxBDDataIn;`
411	40	mohor	`debug <=#Tp 4'h2;`
412	39	mohor	`end`
413			`5'b010_x0 :`
414			`begin`
415			`WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled`
416			`RxEn <=#Tp 1'b0;`
417			`TxEn <=#Tp 1'b0;`
418			`ram_addr <=#Tp WB_ADR_I[9:2];`
419			`ram_di <=#Tp WB_DAT_I;`
420	40	mohor	`BDWrite <=#Tp BDCs & WB_WE_I;`
421			`BDRead <=#Tp BDCs & ~WB_WE_I;`
422			`debug <=#Tp 4'h3;`
423	39	mohor	`end`
424			`5'b010_x1 :`
425			`begin`
426			`WbEn <=#Tp 1'b0;`
427			`RxEn <=#Tp 1'b0;`
428			`TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled`
429			`ram_addr <=#Tp TxBDAddress + TxPointerRead;`
430			`ram_di <=#Tp TxBDDataIn;`
431	40	mohor	`debug <=#Tp 4'h4;`
432	39	mohor	`end`
433			`5'b001_xx :`
434			`begin`
435			`WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)`
436			`RxEn <=#Tp 1'b0;`
437			`TxEn <=#Tp 1'b0;`
438			`ram_addr <=#Tp WB_ADR_I[9:2];`
439			`ram_di <=#Tp WB_DAT_I;`
440	40	mohor	`BDWrite <=#Tp BDCs & WB_WE_I;`
441			`BDRead <=#Tp BDCs & ~WB_WE_I;`
442			`debug <=#Tp 4'h5;`
443	39	mohor	`end`
444			`5'b100_00 :`
445			`begin`
446			`WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit`
447	40	mohor	`debug <=#Tp 4'h6;`
448	39	mohor	`end`
449			`5'b000_00 :`
450			`begin`
451			`WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.`
452			`RxEn <=#Tp 1'b0;`
453			`TxEn <=#Tp 1'b0;`
454			`ram_addr <=#Tp WB_ADR_I[9:2];`
455			`ram_di <=#Tp WB_DAT_I;`
456	40	mohor	`BDWrite <=#Tp BDCs & WB_WE_I;`
457			`BDRead <=#Tp BDCs & ~WB_WE_I;`
458			`debug <=#Tp 4'h7;`
459	39	mohor	`end`
460			`default :`
461			`begin`
462			`WbEn <=#Tp 1'b1; // We go to wb access stage`
463			`RxEn <=#Tp 1'b0;`
464			`TxEn <=#Tp 1'b0;`
465			`ram_addr <=#Tp WB_ADR_I[9:2];`
466			`ram_di <=#Tp WB_DAT_I;`
467	40	mohor	`BDWrite <=#Tp BDCs & WB_WE_I;`
468			`BDRead <=#Tp BDCs & ~WB_WE_I;`
469			`debug <=#Tp 4'h8;`
470	39	mohor	`end`
471			`endcase`
472			`end`
473			`end`
474
475
476			`// Delayed stage signals`
477	40	mohor	`always @ (posedge WB_CLK_I or posedge Reset)`
478	39	mohor	`begin`
479	40	mohor	`if(Reset)`
480	39	mohor	`begin`
481			`WbEn_q <=#Tp 1'b0;`
482			`RxEn_q <=#Tp 1'b0;`
483			`TxEn_q <=#Tp 1'b0;`
484			`end`
485			`else`
486			`begin`
487			`WbEn_q <=#Tp WbEn;`
488			`RxEn_q <=#Tp RxEn;`
489			`TxEn_q <=#Tp TxEn;`
490			`end`
491			`end`
492
493	38	mohor	`// Changes for tx occur every second clock. Flop is used for this manner.`
494	40	mohor	`always @ (posedge MTxClk or posedge Reset)`
495	38	mohor	`begin`
496	40	mohor	`if(Reset)`
497	38	mohor	`Flop <=#Tp 1'b0;`
498			`else`
499			`if(TxDone \| TxAbort \| TxRetry_q)`
500			`Flop <=#Tp 1'b0;`

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