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[/] [ethmac/] [trunk/] [sim/] [rtl_sim/] [ncsim_sim/] [log/] [tb_eth_display.log] - Blame information for rev 348

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Line No. Rev Author Line
1 319 tadejm 
ncsim: 04.10-b001: (c) Copyright 1995-2002 Cadence Design Systems, Inc.
2 
Loading snapshot worklib.ethernet:fun .................... Done
3 
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
4 
ncsim> run
5 
 
6 
ACCESS TO MAC REGISTERS TEST
7 
  Time: 62387000
8 
  TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
9 
  Time: 68509000
10 
  TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
11 
    ->registers tested with 0, 1, 2, 3 and 4 bus delay cycles
12 
  Time: 302749000
13 
  TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
14 
    ->buffer descriptors tested with 0 bus delay
15 
    ->buffer descriptors tested with 1 bus delay cycle
16 
    ->buffer descriptors tested with 2 bus delay cycles
17 
    ->buffer descriptors tested with 3 bus delay cycles
18 
  Time: 5383309000
19 
  TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC
20 
  Time: 5399539000
21 
  TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC
22 
 
23 
MIIM MODULE TEST
24 
  Time: 5645717000
25 
  TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES
26 
  Time: 7595117000
27 
  TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS
28 
  Time: 7622149000
29 
  TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS )
30 
  Time: 7655119000
31 
  TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE
32 
  Time: 7673959000
33 
  TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE )
34 
  Time: 7749859000
35 
  TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE )
36 
  Time: 7825759000
37 
  TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE )
38 
  Time: 8067259000
39 
  TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA )
40 
  => Two error lines will be displayed from WB Bus Monitor, because correct HIGH Z data was read
41 
Time:           8071935000
42 
tb_ethernet.wb_eth_slave_bus_mon.message_out, Slave provided invalid data during read and qualified it with ACK_I
43 
Byte select value: SEL_O = 1111, Data bus value: DAT_I =  0000zzzz
44 
  Time: 8071969000
45 
  TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE
46 
  Time: 8081389000
47 
  TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE )
48 
  Time: 8976619000
49 
  TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE )
50 
  Time: 9882439000
51 
  TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE )
52 
  Time: 10098649000
53 
  TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE )
54 
  Time: 10315609000
55 
  TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE )
56 
  Time: 10532569000
57 
  TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
58 
  Time: 10676539000
59 
  TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE )
60 
  Time: 12186559000
61 
  TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE )
62 
  Time: 13113619000
63 
  TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE )
64 
 
65 
===========================================================================
66 
PHY generates ideal Carrier sense and Collision signals for following tests
67 
===========================================================================
68 
 
69 
MAC FULL DUPLEX TRANSMIT TEST
70 
  Time: 14603687000
71 
  TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )
72 
  Time: 15302239000
73 
  TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )
74 
  Time: 15936679000
75 
  TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
76 
    pads appending to packets is NOT selected
77 
    ->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte)
78 
    pads appending to packets is selected
79 
    ->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes)
80 
    pads appending to packets is NOT selected
81 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
82 
  Time: 49727119000
83 
  TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
84 
    pads appending to packets is NOT selected
85 
    ->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte)
86 
    pads appending to packets is selected
87 
    ->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes)
88 
    pads appending to packets is NOT selected
89 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
90 
  Time: 53442319000
91 
  TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )
92 
    pads appending to packets is NOT selected
93 
    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)
94 
    ->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte)
95 
    ->all packets were send from TX BD 0
96 
    pads appending to packets is NOT selected
97 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
98 
    ->packets with lengths from 72 to 192 are checked (length increasing by 1 byte)
99 
    ->packets were send from TX BD 0 to TX BD 120 respectively
100 
    pads appending to packets is selected
101 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
102 
    ->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes)
103 
    ->packets were send from TX BD 121 to TX BD 127 and from TX BD 0 to TX BD 2 respectively
104 
    pads appending to packets is NOT selected
105 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
106 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
107 
    ->packets were send from TX BD 3 to TX BD 18 respectively
108 
  Time: 95351355000
109 
  TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )
110 
    pads appending to packets is NOT selected
111 
    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)
112 
    ->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte)
113 
    ->all packets were send from TX BD 0
114 
    pads appending to packets is NOT selected
115 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
116 
    ->packets with lengths from 72 to 192 are checked (length increasing by 1 byte)
117 
    ->packets were send from TX BD 0 to TX BD 120 respectively
118 
    pads appending to packets is selected
119 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
120 
    ->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes)
121 
    ->packets were send from TX BD 121 to TX BD 127 and from TX BD 0 to TX BD 2 respectively
122 
    pads appending to packets is NOT selected
123 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
124 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
125 
    ->packets were send from TX BD 3 to TX BD 18 respectively
126 
  Time: 99968955000
127 
  TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
128 
    pads appending to packets is selected
129 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
130 
    ->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte)
131 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
132 
    ->packet with length 4 is not transmitted (length increasing by 1 byte)
133 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
134 
    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)
135 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
136 
    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)
137 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
138 
    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)
139 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
140 
    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)
141 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
142 
    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)
143 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
144 
  Time: 104360595000
145 
  TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
146 
    pads appending to packets is selected
147 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
148 
    ->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte)
149 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
150 
    ->packet with length 4 is not transmitted (length increasing by 1 byte)
151 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
152 
    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)
153 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
154 
    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)
155 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
156 
    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)
157 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
158 
    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)
159 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
160 
    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)
161 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
162 
  Time: 104966115000
163 
  TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
164 
    pads appending to packets is not selected (except for 0x23)
165 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
166 
    ->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte)
167 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
168 
    ->packet with length 4 is not transmitted (length increasing by 1 byte)
169 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
170 
    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)
171 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
172 
    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)
173 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
174 
    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)
175 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
176 
    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)
177 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
178 
    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)
179 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
180 
  Time: 108053235000
181 
  TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
182 
    pads appending to packets is not selected (except for 0x23)
183 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
184 
    ->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte)
185 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
186 
    ->packet with length 4 is not transmitted (length increasing by 1 byte)
187 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
188 
    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)
189 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
190 
    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)
191 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
192 
    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)
193 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
194 
    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)
195 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
196 
    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)
197 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
198 
  Time: 108528075000
199 
  TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )
200 
    ->packet with length 1535 sent
201 
    ->packet with length 1536 sent
202 
    ->packet with length 1537 sent
203 
    ->packet with length 104 sent
204 
  Time: 112357635000
205 
  TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )
206 
    ->packet with length 1535 sent
207 
    ->packet with length 1536 sent
208 
    ->packet with length 1537 sent
209 
    ->packet with length 104 sent
210 
  Time: 112755195000
211 
  TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )
212 
    ->packet with length 116 sent
213 
    ->packet with length 117 sent
214 
    ->packet with length 118 sent
215 
  Time: 113082915000
216 
  TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )
217 
    ->packet with length 116 sent
218 
    ->packet with length 117 sent
219 
    ->packet with length 118 sent
220 
  Time: 113125035000
221 
  TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )
222 
    ->packet with length 1358 sent
223 
    ->packet with length 1359 sent
224 
    ->packet with length 1360 sent
225 
  Time: 116433315000
226 
  TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )
227 
    ->packet with length 1358 sent
228 
    ->packet with length 1359 sent
229 
    ->packet with length 1360 sent
230 
  Time: 116773995000
231 
  TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )
232 
   i_length = 1531
233 
   eth_phy length = 1535
234 
    ->packet with length 1535 sent
235 
   i_length = 1532
236 
   eth_phy length = 1536
237 
    ->packet with length 1536 sent
238 
   i_length = 1533
239 
   eth_phy length = 1537
240 
    ->packet with length 1537 sent
241 
   i_length = 65530
242 
   eth_phy length = 65534
243 
    ->packet with length 65534 sent
244 
   i_length = 65531
245 
   eth_phy length = 65535
246 
    ->packet with length 65535 sent
247 
  Time: 225419715000
248 
  TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )
249 
   i_length = 1531
250 
   eth_phy length = 1535
251 
    ->packet with length 1535 sent
252 
   i_length = 1532
253 
   eth_phy length = 1536
254 
    ->packet with length 1536 sent
255 
   i_length = 1533
256 
   eth_phy length = 1537
257 
    ->packet with length 1537 sent
258 
   i_length = 65530
259 
   eth_phy length = 65534
260 
    ->packet with length 65534 sent
261 
   i_length = 65531
262 
   eth_phy length = 65535
263 
    ->packet with length 65535 sent
264 
  Time: 236329395000
265 
  TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )
266 
    ->IPG with 8 mtx_clk periods (min 3) between packets with lengths 64 and 65 checked
267 
    ->IPG with 8 mtx_clk periods (min 4) between packets with lengths 66 and 67 checked
268 
    ->IPG with 8 mtx_clk periods (min 5) between packets with lengths 68 and 69 checked
269 
    ->IPG with 8 mtx_clk periods (min 6) between packets with lengths 70 and 71 checked
270 
    ->IPG with 7 mtx_clk periods (min 7) between packets with lengths 72 and 73 checked
271 
    ->IPG with 8 mtx_clk periods (min 8) between packets with lengths 74 and 75 checked
272 
    ->IPG with 9 mtx_clk periods (min 9) between packets with lengths 76 and 77 checked
273 
    ->IPG with 10 mtx_clk periods (min 10) between packets with lengths 78 and 79 checked
274 
    ->IPG with 17 mtx_clk periods (min 17) between packets with lengths 80 and 81 checked
275 
    ->IPG with 24 mtx_clk periods (min 24) between packets with lengths 82 and 83 checked
276 
    ->IPG with 38 mtx_clk periods (min 38) between packets with lengths 84 and 85 checked
277 
    ->IPG with 72 mtx_clk periods (min 72) between packets with lengths 86 and 87 checked
278 
    ->IPG with 130 mtx_clk periods (min 130) between packets with lengths 88 and 89 checked
279 
  Time: 238386915000
280 
  TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )
281 
    ->IPG with 47 mtx_clk periods (min 3) between packets with lengths 64 and 65 checked
282 
    ->IPG with 47 mtx_clk periods (min 4) between packets with lengths 66 and 67 checked
283 
    ->IPG with 44 mtx_clk periods (min 5) between packets with lengths 68 and 69 checked
284 
    ->IPG with 45 mtx_clk periods (min 6) between packets with lengths 70 and 71 checked
285 
    ->IPG with 44 mtx_clk periods (min 7) between packets with lengths 72 and 73 checked
286 
    ->IPG with 43 mtx_clk periods (min 8) between packets with lengths 74 and 75 checked
287 
    ->IPG with 45 mtx_clk periods (min 9) between packets with lengths 76 and 77 checked
288 
    ->IPG with 44 mtx_clk periods (min 10) between packets with lengths 78 and 79 checked
289 
    ->IPG with 43 mtx_clk periods (min 17) between packets with lengths 80 and 81 checked
290 
    ->IPG with 45 mtx_clk periods (min 24) between packets with lengths 82 and 83 checked
291 
    ->IPG with 44 mtx_clk periods (min 38) between packets with lengths 84 and 85 checked
292 
    ->IPG with 72 mtx_clk periods (min 72) between packets with lengths 86 and 87 checked
293 
    ->IPG with 130 mtx_clk periods (min 130) between packets with lengths 88 and 89 checked
294 
  Time: 238653435000
295 
  TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )
296 
    ->under-run on 61. byte
297 
    ->under-run on 62. byte
298 
    ->under-run on 63. byte
299 
    ->under-run on 64. byte
300 
    ->under-run on 65. byte
301 
    ->under-run on 66. byte
302 
    ->under-run on 67. byte
303 
    ->under-run on 68. byte
304 
    ->under-run on 69. byte
305 
    ->under-run on 70. byte
306 
    ->under-run on 71. byte
307 
    ->under-run on 72. byte
308 
    ->under-run on 73. byte
309 
    ->under-run on 74. byte
310 
    ->under-run on 75. byte
311 
    ->under-run on 76. byte
312 
    ->under-run on 77. byte
313 
    ->under-run on 78. byte
314 
    ->under-run on 79. byte
315 
    ->no under-run on 80. byte, since length of frame (without CRC) is only 80 bytes
316 
    ->no under-run on 81. byte, since length of frame (without CRC) is only 80 bytes
317 
    ->no under-run on 82. byte, since length of frame (without CRC) is only 80 bytes
318 
    ->no under-run on 83. byte, since length of frame (without CRC) is only 80 bytes
319 
    ->no under-run on 84. byte, since length of frame (without CRC) is only 80 bytes
320 
  Time: 242447355000
321 
  TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )
322 
    ->under-run on 61. byte
323 
    ->under-run on 62. byte
324 
    ->under-run on 63. byte
325 
    ->under-run on 64. byte
326 
    ->under-run on 65. byte
327 
    ->under-run on 66. byte
328 
    ->under-run on 67. byte
329 
    ->under-run on 68. byte
330 
    ->under-run on 69. byte
331 
    ->under-run on 70. byte
332 
    ->under-run on 71. byte
333 
    ->under-run on 72. byte
334 
    ->under-run on 73. byte
335 
    ->under-run on 74. byte
336 
    ->under-run on 75. byte
337 
    ->under-run on 76. byte
338 
    ->under-run on 77. byte
339 
    ->under-run on 78. byte
340 
    ->under-run on 79. byte
341 
    ->no under-run on 80. byte, since length of frame (without CRC) is only 80 bytes
342 
    ->no under-run on 81. byte, since length of frame (without CRC) is only 80 bytes
343 
    ->no under-run on 82. byte, since length of frame (without CRC) is only 80 bytes
344 
    ->no under-run on 83. byte, since length of frame (without CRC) is only 80 bytes
345 
    ->no under-run on 84. byte, since length of frame (without CRC) is only 80 bytes
346 
 
347 
MAC FULL DUPLEX RECEIVE TEST
348 
  Time: 242923367000
349 
  TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
350 
  Time: 252557359000
351 
  TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
352 
  Time: 254085799000
353 
  TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
354 
    8 packets (without this one) are checked - packets are received by two in a set
355 
    From this moment:
356 
    first one of two packets (including this one) is not accepted due to late RX enable
357 
    ->RX enable set 3 WB clks after RX_DV
358 
  Time: 294264649000
359 
  TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
360 
 
361 
    From this moment:
362 
    first one of two packets (including this one) is not accepted due to late RX enable
363 
    ->RX enable set 2 WB clks after RX_DV
364 
  Time: 299591329000
365 
  TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )
366 
    receive small packets is NOT selected
367 
    ->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte)
368 
    receive small packets is selected
369 
    ->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes)
370 
    receive small packets is NOT selected
371 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
372 
  Time: 333243169000
373 
  TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
374 
    receive small packets is NOT selected
375 
    ->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte)
376 
    receive small packets is selected
377 
    ->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes)
378 
    receive small packets is NOT selected
379 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
380 
  Time: 336818689000
381 
  TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
382 
    receive small packets is NOT selected
383 
    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)
384 
    ->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte)
385 
    ->all packets were received on RX BD 0
386 
    receive small packets is NOT selected
387 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
388 
    ->packets with lengths from 72 to 192 are checked (length increasing by 1 byte)
389 
    ->packets were received on RX BD 0 to RX BD 120 respectively
390 
    receive small packets is selected
391 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
392 
    ->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes)
393 
    ->packets were received from RX BD 121 to RX BD 127 and from RX BD 0 to RX BD 2 respectively
394 
    receive small packets is NOT selected
395 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
396 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
397 
    ->packets were received from RX BD 3 to RX BD 18 respectively
398 
  Time: 378320475000
399 
  TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )
400 
    receive small packets is NOT selected
401 
    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)
402 
    ->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte)
403 
    ->all packets were received on RX BD 0
404 
    receive small packets is NOT selected
405 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
406 
    ->packets with lengths from 72 to 192 are checked (length increasing by 1 byte)
407 
    ->packets were received on RX BD 0 to RX BD 120 respectively
408 
    receive small packets is selected
409 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
410 
    ->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes)
411 
    ->packets were received from RX BD 121 to RX BD 127 and from RX BD 0 to RX BD 2 respectively
412 
    receive small packets is NOT selected
413 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
414 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
415 
    ->packets were received from RX BD 3 to RX BD 18 respectively
416 
  Time: 382758795000
417 
  TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )
418 
    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)
419 
    ->packets with lengths from 0 to 3 are not received (length increasing by 1 byte)
420 
    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)
421 
    ->packet with length 4 is not received (length increasing by 1 byte)
422 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
423 
    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)
424 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
425 
    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)
426 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
427 
    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)
428 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
429 
    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)
430 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
431 
    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)
432 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
433 
    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)
434 
    ->packets with lengths from 70 to 77 are checked (length increasing by 1 byte)
435 
  Time: 386187495000
436 
  TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )
437 
    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)
438 
    ->packets with lengths from 0 to 3 are not received (length increasing by 1 byte)
439 
    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)
440 
    ->packet with length 4 is not received (length increasing by 1 byte)
441 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
442 
    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)
443 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
444 
    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)
445 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
446 
    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)
447 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
448 
    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)
449 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
450 
    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)
451 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
452 
    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)
453 
    ->packets with lengths from 70 to 77 are checked (length increasing by 1 byte)
454 
  Time: 386657745000
455 
  TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )
456 
    Unicast packet is going to be received with PRO bit (wrap at 1st BD)
457 
    ->packet received
458 
    Unicast packet is going to be received without PRO bit (wrap at 1st BD)
459 
    ->packet received
460 
    non Unicast packet is going to be received with PRO bit (wrap at 1st BD)
461 
    ->packet received
462 
    non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD)
463 
    ->packet NOT received
464 
    Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)
465 
    ->packet received
466 
    Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD)
467 
    ->packet received
468 
    Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)
469 
    ->packet received
470 
    Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD)
471 
    ->packet NOT received
472 
  Time: 387208159000
473 
  TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )
474 
    Unicast packet is going to be received with PRO bit (wrap at 1st BD)
475 
    ->packet received
476 
    Unicast packet is going to be received without PRO bit (wrap at 1st BD)
477 
    ->packet received
478 
    non Unicast packet is going to be received with PRO bit (wrap at 1st BD)
479 
    ->packet received
480 
    non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD)
481 
    ->packet NOT received
482 
    Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)
483 
    ->packet received
484 
    Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD)
485 
    ->packet received
486 
    Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)
487 
    ->packet received
488 
    Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD)
489 
    ->packet NOT received
490 
  Time: 387288679000
491 
  TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )
492 
    packet shoud be successfuly received
493 
    ->packet received
494 
  Time: 387359689000
495 
*E RX buffer descriptor status is not correct: 6000 instead of 4000
496 
    packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun
497 
    ->packet NOT received
498 
  Time: 387423768000
499 
*E WB INT signal should not be set
500 
  Time: 387424129000
501 
*E Any of interrupts was set, interrupt reg: 10, len: 0
502 
    packet should NOT be received - RX FIFO overrun
503 
    ->packet NOT received
504 
  Time: 387487968000
505 
*E WB INT signal should not be set
506 
  Time: 387488329000
507 
*E Any of interrupts was set, interrupt reg: 10, len: 0
508 
    ->previous packet written into MEM
509 
  Time: 387492409000
510 
*E RX buffer descriptor status is not correct: c000 instead of 4000
511 
  Time: 387492529000
512 
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10
513 
  Time: 387492529000
514 
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10
515 
    packet shoud be successfuly received
516 
    ->packet NOT received
517 
  Time: 387562849000
518 
*E RX buffer descriptor status is not correct: c000 instead of 4000
519 
  Time: 387562849000
520 
*E Wrong length of the packet out from PHY (0 instead of 72)
521 
  Time: 387562867000
522 
*E Wrong data of the received packet
523 
  Time: 387562969000
524 
*E Interrupt Receive Buffer was not set, interrupt reg: 10
525 
  Time: 387562969000
526 
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10
527 
    packet should NOT be received - RX FIFO overrun
528 
    ->packet NOT received
529 
  Time: 387633408000
530 
*E WB INT signal should not be set
531 
  Time: 387633769000
532 
*E Any of interrupts was set, interrupt reg: 10, len: 0
533 
  Time: 387637849000
534 
*E RX buffer descriptor status is not correct: c000 instead of 4040
535 
  Time: 387637969000
536 
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10
537 
  Time: 387637969000
538 
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10
539 
    packet shoud be successfuly received
540 
    ->packet NOT received
541 
  Time: 387708409000
542 
*E RX buffer descriptor status is not correct: c000 instead of 4000
543 
  Time: 387708409000
544 
*E Wrong length of the packet out from PHY (0 instead of 72)
545 
  Time: 387708427000
546 
*E Wrong data of the received packet
547 
  Time: 387708529000
548 
*E Interrupt Receive Buffer was not set, interrupt reg: 10
549 
  Time: 387708529000
550 
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10
551 
    packet should NOT be received - RX FIFO overrun
552 
    ->packet NOT received
553 
  Time: 387788208000
554 
*E WB INT signal should not be set
555 
  Time: 387788569000
556 
*E Any of interrupts was set, interrupt reg: 10, len: 0
557 
  Time: 387792649000
558 
*E RX buffer descriptor status is not correct: c000 instead of 4040
559 
  Time: 387792769000
560 
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10
561 
  Time: 387792769000
562 
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10
563 
    packet shoud be successfuly received
564 
    ->packet NOT received
565 
  Time: 387872809000
566 
*E RX buffer descriptor status is not correct: c000 instead of 4000
567 
  Time: 387872809000
568 
*E Wrong length of the packet out from PHY (0 instead of 84)
569 
  Time: 387872830000
570 
*E Wrong data of the received packet
571 
  Time: 387872929000
572 
*E Interrupt Receive Buffer was not set, interrupt reg: 10
573 
  Time: 387872929000
574 
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10
575 
    packet shoud be successfuly received
576 
    ->packet NOT received
577 
  Time: 387952849000
578 
*E RX buffer descriptor status is not correct: e000 instead of 6000
579 
  Time: 387952849000
580 
*E Wrong length of the packet out from PHY (0 instead of 84)
581 
  Time: 387952870000
582 
*E Wrong data of the received packet
583 
  Time: 387952969000
584 
*E Interrupt Receive Buffer was not set, interrupt reg: 10
585 
  Time: 387952969000
586 
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10
587 
    packet should NOT be received - RX FIFO overrun due to lack of RX BDs
588 
    ->packet NOT received
589 
    packet shoud be successfuly received
590 
    ->packet received
591 
  Time: 388115689000
592 
*E RX buffer descriptor status is not correct: 6000 instead of 4000
593 
  Time: 388116049000
594 
  TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )
595 
    packet shoud be successfuly received
596 
    ->packet received
597 
    packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun
598 
    ->packet NOT received
599 
    packet should NOT be received - RX FIFO overrun
600 
    ->packet NOT received
601 
    ->previous packet written into MEM
602 
    packet shoud be successfuly received
603 
    ->packet received
604 
    packet should NOT be received - RX FIFO overrun
605 
    ->packet NOT received
606 
    packet shoud be successfuly received
607 
    ->packet received
608 
    packet should NOT be received - RX FIFO overrun
609 
    ->packet NOT received
610 
    packet shoud be successfuly received
611 
    ->packet received
612 
    packet shoud be successfuly received
613 
    ->packet received
614 
    packet should NOT be received - RX FIFO overrun due to lack of RX BDs
615 
    ->packet NOT received
616 
    packet shoud be successfuly received
617 
    ->packet received
618 
 
619 
MAC FULL DUPLEX FLOW CONTROL TEST
620 
  Time: 388235057000
621 
  TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )
622 
  Time: 397626071000
623 
  TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )
624 
  Time: 398657171000
625 
  TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )
626 
  Time: 399868939000
627 
  TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )
628 
  Time: 400018579000
629 
  TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )
630 
   ->8 frames transmitted
631 
   ->8 frames received
632 
   ->8 frames transmitted
633 
   ->8 frames received
634 
   ->8 frames transmitted
635 
   ->8 frames transmitted
636 
   ->8 frames received
637 
   ->8 frames transmitted
638 
   ->8 frames received
639 
   ->8 frames transmitted
640 
   ->8 frames transmitted
641 
   ->8 frames received
642 
   ->8 frames transmitted
643 
   ->8 frames received
644 
   ->8 frames transmitted
645 
   ->8 frames received
646 
   ->8 frames transmitted
647 
   ->8 frames transmitted
648 
   ->8 frames received
649 
   ->8 frames transmitted
650 
   ->8 frames received
651 
   ->8 frames transmitted
652 
   ->8 frames transmitted
653 
   ->8 frames received
654 
   ->8 frames transmitted
655 
   ->8 frames received
656 
   ->8 frames transmitted
657 
   ->8 frames received
658 
   ->8 frames transmitted
659 
   ->8 frames transmitted
660 
   ->8 frames received
661 
   ->8 frames transmitted
662 
   ->8 frames received
663 
   ->8 frames transmitted
664 
   ->8 frames transmitted
665 
   ->8 frames received
666 
   ->8 frames transmitted
667 
   ->8 frames received
668 
   ->8 frames transmitted
669 
   ->8 frames received
670 
   ->8 frames transmitted
671 
   ->8 frames transmitted
672 
   ->8 frames received
673 
   ->8 frames transmitted
674 
   ->8 frames received
675 
   ->8 frames transmitted
676 
   ->8 frames transmitted
677 
   ->8 frames received
678 
   ->8 frames transmitted
679 
   ->8 frames received
680 
   ->8 frames transmitted
681 
   ->8 frames received
682 
   ->8 frames transmitted
683 
   ->8 frames transmitted
684 
   ->8 frames received
685 
   ->8 frames transmitted
686 
   ->8 frames received
687 
   ->8 frames transmitted
688 
   ->8 frames transmitted
689 
   ->8 frames received
690 
   ->8 frames transmitted
691 
   ->8 frames received
692 
   ->8 frames transmitted
693 
   ->8 frames received
694 
   ->8 frames transmitted
695 
   ->8 frames transmitted
696 
   ->8 frames received
697 
   ->8 frames transmitted
698 
   ->8 frames received
699 
   ->8 frames transmitted
700 
   ->8 frames transmitted
701 
   ->8 frames received
702 
   ->8 frames transmitted
703 
   ->8 frames received
704 
   ->8 frames transmitted
705 
   ->8 frames received
706 
   ->8 frames transmitted
707 
   ->8 frames transmitted
708 
   ->8 frames received
709 
   ->8 frames transmitted
710 
   ->8 frames received
711 
   ->8 frames transmitted
712 
   ->8 frames transmitted
713 
   ->8 frames received
714 
   ->8 frames transmitted
715 
   ->8 frames received
716 
   ->8 frames received
717 
   ->8 frames received
718 
   ->8 frames received
719 
   ->8 frames received
720 
   ->8 frames received
721 
   ->8 frames received
722 
   ->8 frames received
723 
   ->8 frames received
724 
   ->8 frames received
725 
   ->8 frames received
726 
   ->8 frames received
727 
   ->8 frames received
728 
   ->8 frames received
729 
   ->8 frames received
730 
  Time: 438761899000
731 
  TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps )
732 
   ->8 frames transmitted
733 
   ->8 frames received
734 
   ->8 frames transmitted
735 
   ->8 frames received
736 
   ->8 frames transmitted
737 
   ->8 frames received
738 
   ->8 frames transmitted
739 
   ->8 frames received
740 
   ->8 frames transmitted
741 
   ->8 frames received
742 
   ->8 frames transmitted
743 
   ->8 frames transmitted
744 
   ->8 frames received
745 
   ->8 frames transmitted
746 
   ->8 frames received
747 
   ->8 frames transmitted
748 
   ->8 frames received
749 
   ->8 frames transmitted
750 
   ->8 frames received
751 
   ->8 frames transmitted
752 
   ->8 frames received
753 
   ->8 frames transmitted
754 
   ->8 frames received
755 
   ->8 frames transmitted
756 
   ->8 frames transmitted
757 
   ->8 frames received
758 
   ->8 frames transmitted
759 
   ->8 frames received
760 
   ->8 frames transmitted
761 
   ->8 frames received
762 
   ->8 frames transmitted
763 
   ->8 frames received
764 
   ->8 frames transmitted
765 
   ->8 frames received
766 
   ->8 frames transmitted
767 
   ->8 frames received
768 
   ->8 frames transmitted
769 
   ->8 frames transmitted
770 
   ->8 frames received
771 
   ->8 frames transmitted
772 
   ->8 frames received
773 
   ->8 frames transmitted
774 
   ->8 frames received
775 
   ->8 frames transmitted
776 
   ->8 frames received
777 
   ->8 frames transmitted
778 
   ->8 frames received
779 
   ->8 frames transmitted
780 
   ->8 frames received
781 
   ->8 frames transmitted
782 
   ->8 frames transmitted
783 
   ->8 frames received
784 
   ->8 frames transmitted
785 
   ->8 frames received
786 
   ->8 frames transmitted
787 
   ->8 frames received
788 
   ->8 frames transmitted
789 
   ->8 frames received
790 
   ->8 frames transmitted
791 
   ->8 frames received
792 
   ->8 frames transmitted
793 
   ->8 frames received
794 
   ->8 frames transmitted
795 
   ->8 frames transmitted
796 
   ->8 frames received
797 
   ->8 frames transmitted
798 
   ->8 frames received
799 
   ->8 frames transmitted
800 
   ->8 frames received
801 
   ->8 frames transmitted
802 
   ->8 frames received
803 
   ->8 frames transmitted
804 
   ->8 frames received
805 
   ->8 frames transmitted
806 
   ->8 frames received
807 
   ->8 frames transmitted
808 
   ->8 frames transmitted
809 
   ->8 frames received
810 
   ->8 frames transmitted
811 
   ->8 frames received
812 
   ->8 frames transmitted
813 
   ->8 frames received
814 
   ->8 frames transmitted
815 
   ->8 frames received
816 
   ->8 frames transmitted
817 
   ->8 frames received
818 
   ->8 frames transmitted
819 
   ->8 frames received
820 
   ->8 frames transmitted
821 
   ->8 frames transmitted
822 
   ->8 frames received
823 
   ->8 frames transmitted
824 
   ->8 frames received
825 
   ->8 frames received
826 
   ->8 frames received
827 
   ->8 frames received
828 
   ->8 frames received
829 
   ->8 frames received
830 
   ->8 frames received
831 
   ->8 frames received
832 
 
833 
MAC HALF DUPLEX FLOW TEST
834 
  Time: 443751047000
835 
  TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )
836 
    ->TX Defer occured
837 
    ->IPGR2 timing checking
838 
  Time: 443899119000
839 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
840 
    ->TX Defer occured
841 
    ->IPGR2 timing checking
842 
  Time: 444057159000
843 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
844 
    ->TX Defer occured
845 
    ->IPGR2 timing checking
846 
  Time: 444222399000
847 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
848 
    ->TX Defer occured
849 
    ->IPGR2 timing checking
850 
  Time: 444387999000
851 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
852 
    ->TX Defer occured
853 
    ->IPGR2 timing checking
854 
  Time: 444564339000
855 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
856 
    ->TX Defer occured
857 
    ->IPGR2 timing checking
858 
  Time: 444730779000
859 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
860 
    ->TX Defer occured
861 
    ->IPGR2 timing checking
862 
  Time: 444897579000
863 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
864 
    ->TX Defer occured
865 
    ->IPGR2 timing checking
866 
  Time: 445064679000
867 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
868 
    ->TX Defer occured
869 
  Time: 445100407000
870 
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
871 
    ->IPGR2 timing checking
872 
  Time: 445293579000
873 
*E Wrong data of the transmitted packet
874 
    ->TX Defer occured
875 
  Time: 445319207000
876 
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
877 
    ->IPGR2 timing checking
878 
  Time: 445461579000
879 
*E Wrong data of the transmitted packet
880 
    ->Collision occured due to registered inputs
881 
    ->IPGR2 timing checking
882 
  Time: 445680339000
883 
*E Wrong data of the transmitted packet
884 
    ->Collision occured - last checking
885 
    ->IPGR2 timing checking
886 
  Time: 445899039000
887 
*E Wrong data of the transmitted packet
888 
  Time: 445919355000
889 
  TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )
890 
    ->TX Defer occured
891 
    ->IPGR2 timing checking
892 
  Time: 445941549000
893 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
894 
    ->TX Defer occured
895 
    ->IPGR2 timing checking
896 
  Time: 445958709000
897 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
898 
    ->TX Defer occured
899 
    ->IPGR2 timing checking
900 
  Time: 445976589000
901 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
902 
    ->TX Defer occured
903 
    ->IPGR2 timing checking
904 
  Time: 445994469000
905 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
906 
    ->TX Defer occured
907 
    ->IPGR2 timing checking
908 
  Time: 446019369000
909 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
910 
    ->TX Defer occured
911 
    ->IPGR2 timing checking
912 
  Time: 446037369000
913 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
914 
    ->TX Defer occured
915 
    ->IPGR2 timing checking
916 
  Time: 446055369000
917 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
918 
    ->TX Defer occured
919 
    ->IPGR2 timing checking
920 
  Time: 446073369000
921 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
922 
    ->TX Defer occured
923 
    ->IPGR2 timing checking
924 
  Time: 446098269000
925 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
926 
    ->TX Defer occured
927 
    ->IPGR2 timing checking
928 
  Time: 446116269000
929 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
930 
    ->TX Defer occured
931 
    ->IPGR2 timing checking
932 
  Time: 446134389000
933 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
934 
    ->TX Defer occured
935 
    ->IPGR2 timing checking
936 
  Time: 446152629000
937 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
938 
    ->TX Defer occured
939 
    ->IPGR2 timing checking
940 
  Time: 446177769000
941 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
942 
    ->TX Defer occured
943 
    ->IPGR2 timing checking
944 
  Time: 446196129000
945 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
946 
    ->TX Defer occured
947 
    ->IPGR2 timing checking
948 
  Time: 446214489000
949 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
950 
    ->TX Defer occured
951 
    ->IPGR2 timing checking
952 
  Time: 446232849000
953 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
954 
    ->TX Defer occured
955 
    ->IPGR2 timing checking
956 
  Time: 446257989000
957 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
958 
    ->TX Defer occured
959 
    ->IPGR2 timing checking
960 
  Time: 446276349000
961 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
962 
    ->TX Defer occured
963 
    ->IPGR2 timing checking
964 
  Time: 446294709000
965 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
966 
    ->TX Defer occured
967 
    ->IPGR2 timing checking
968 
  Time: 446313189000
969 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
970 
    ->TX Defer occured
971 
    ->IPGR2 timing checking
972 
  Time: 446338689000
973 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
974 
    ->TX Defer occured
975 
    ->IPGR2 timing checking
976 
  Time: 446357289000
977 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
978 
    ->TX Defer occured
979 
    ->IPGR2 timing checking
980 
  Time: 446376009000
981 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
982 
    ->TX Defer occured
983 
    ->IPGR2 timing checking
984 
  Time: 446394549000
985 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
986 
    ->TX Defer occured
987 
    ->IPGR2 timing checking
988 
  Time: 446420169000
989 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
990 
    ->TX Defer occured
991 
    ->IPGR2 timing checking
992 
  Time: 446439009000
993 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
994 
    ->TX Defer occured
995 
    ->IPGR2 timing checking
996 
  Time: 446457849000
997 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
998 
    ->TX Defer occured
999 
    ->IPGR2 timing checking
1000 
  Time: 446476689000
1001 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1002 
    ->TX Defer occured
1003 
    ->IPGR2 timing checking
1004 
  Time: 446502309000
1005 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1006 
    ->TX Defer occured
1007 
    ->IPGR2 timing checking
1008 
  Time: 446521149000
1009 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1010 
    ->TX Defer occured
1011 
    ->IPGR2 timing checking
1012 
  Time: 446539989000
1013 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1014 
    ->TX Defer occured
1015 
    ->IPGR2 timing checking
1016 
  Time: 446558949000
1017 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1018 
    ->TX Defer occured
1019 
    ->IPGR2 timing checking
1020 
  Time: 446584929000
1021 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1022 
    ->TX Defer occured
1023 
    ->IPGR2 timing checking
1024 
  Time: 446604009000
1025 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1026 
    ->TX Defer occured
1027 
    ->IPGR2 timing checking
1028 
  Time: 446623209000
1029 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1030 
    ->TX Defer occured
1031 
    ->IPGR2 timing checking
1032 
  Time: 446642229000
1033 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1034 
    ->TX Defer occured
1035 
    ->IPGR2 timing checking
1036 
  Time: 446668329000
1037 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1038 
    ->TX Defer occured
1039 
    ->IPGR2 timing checking
1040 
  Time: 446687649000
1041 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1042 
    ->TX Defer occured
1043 
    ->IPGR2 timing checking
1044 
  Time: 446706969000
1045 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1046 
    ->TX Defer occured
1047 
    ->IPGR2 timing checking
1048 
  Time: 446726289000
1049 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1050 
    ->TX Defer occured
1051 
    ->IPGR2 timing checking
1052 
  Time: 446752389000
1053 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1054 
    ->TX Defer occured
1055 
    ->IPGR2 timing checking
1056 
  Time: 446771709000
1057 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1058 
    ->TX Defer occured
1059 
    ->IPGR2 timing checking
1060 
  Time: 446791029000
1061 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1062 
    ->TX Defer occured
1063 
    ->IPGR2 timing checking
1064 
  Time: 446810469000
1065 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1066 
    ->TX Defer occured
1067 
    ->IPGR2 timing checking
1068 
  Time: 446836929000
1069 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1070 
    ->TX Defer occured
1071 
    ->IPGR2 timing checking
1072 
  Time: 446856489000
1073 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1074 
    ->TX Defer occured
1075 
    ->IPGR2 timing checking
1076 
  Time: 446876169000
1077 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1078 
    ->TX Defer occured
1079 
  Time: 446880487000
1080 
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
1081 
    ->IPGR2 timing checking
1082 
  Time: 446895669000
1083 
*E Wrong data of the transmitted packet
1084 
    ->TX Defer occured
1085 
  Time: 446906887000
1086 
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
1087 
    ->IPGR2 timing checking
1088 
  Time: 446922249000
1089 
*E Wrong data of the transmitted packet
1090 
    ->Collision occured due to registered inputs
1091 
    ->IPGR2 timing checking
1092 
  Time: 446947089000
1093 
*E Wrong data of the transmitted packet
1094 
    ->Collision occured - last checking
1095 
    ->IPGR2 timing checking
1096 
  Time: 446966889000
1097 
*E Wrong data of the transmitted packet
1098 
 
1099 
===========================================================================
1100 
PHY generates 'real delayed' Carrier sense and Collision signals for following tests
1101 
===========================================================================
1102 
 
1103 
MAC FULL DUPLEX TRANSMIT TEST
1104 
  Time: 446969327000
1105 
  TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps )
1106 
  Time: 447667519000
1107 
  TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps )
1108 
  Time: 448301959000
1109 
  TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps )
1110 
    pads appending to packets is NOT selected
1111 
    ->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte)
1112 
    pads appending to packets is selected
1113 
    ->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes)
1114 
    pads appending to packets is NOT selected
1115 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
1116 
  Time: 482092399000
1117 
  TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps )
1118 
    pads appending to packets is NOT selected
1119 
    ->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte)
1120 
    pads appending to packets is selected
1121 
    ->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes)
1122 
    pads appending to packets is NOT selected
1123 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
1124 
  Time: 485807599000
1125 
  TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps )
1126 
    pads appending to packets is NOT selected
1127 
    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)
1128 
    ->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte)
1129 
    ->all packets were send from TX BD 0
1130 
    pads appending to packets is NOT selected
1131 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
1132 
    ->packets with lengths from 72 to 192 are checked (length increasing by 1 byte)
1133 
    ->packets were send from TX BD 0 to TX BD 120 respectively
1134 
    pads appending to packets is selected
1135 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
1136 
    ->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes)
1137 
    ->packets were send from TX BD 121 to TX BD 127 and from TX BD 0 to TX BD 2 respectively
1138 
    pads appending to packets is NOT selected
1139 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
1140 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
1141 
    ->packets were send from TX BD 3 to TX BD 18 respectively
1142 
  Time: 527716635000
1143 
  TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps )
1144 
    pads appending to packets is NOT selected
1145 
    using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0)
1146 
    ->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte)
1147 
    ->all packets were send from TX BD 0
1148 
    pads appending to packets is NOT selected
1149 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
1150 
    ->packets with lengths from 72 to 192 are checked (length increasing by 1 byte)
1151 
    ->packets were send from TX BD 0 to TX BD 120 respectively
1152 
    pads appending to packets is selected
1153 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
1154 
    ->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes)
1155 
    ->packets were send from TX BD 121 to TX BD 127 and from TX BD 0 to TX BD 2 respectively
1156 
    pads appending to packets is NOT selected
1157 
    using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127)
1158 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
1159 
    ->packets were send from TX BD 3 to TX BD 18 respectively
1160 
  Time: 532334235000
1161 
  TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
1162 
    pads appending to packets is selected
1163 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
1164 
    ->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte)
1165 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
1166 
    ->packet with length 4 is not transmitted (length increasing by 1 byte)
1167 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
1168 
    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)
1169 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
1170 
    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)
1171 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
1172 
    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)
1173 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
1174 
    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)
1175 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
1176 
    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)
1177 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
1178 
  Time: 536725875000
1179 
  TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
1180 
    pads appending to packets is selected
1181 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
1182 
    ->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte)
1183 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
1184 
    ->packet with length 4 is not transmitted (length increasing by 1 byte)
1185 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
1186 
    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)
1187 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
1188 
    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)
1189 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
1190 
    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)
1191 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
1192 
    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)
1193 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
1194 
    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)
1195 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
1196 
  Time: 537331395000
1197 
  TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps )
1198 
    pads appending to packets is not selected (except for 0x23)
1199 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
1200 
    ->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte)
1201 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
1202 
    ->packet with length 4 is not transmitted (length increasing by 1 byte)
1203 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
1204 
    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)
1205 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
1206 
    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)
1207 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
1208 
    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)
1209 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
1210 
    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)
1211 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
1212 
    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)
1213 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
1214 
  Time: 540418515000
1215 
  TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps )
1216 
    pads appending to packets is not selected (except for 0x23)
1217 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
1218 
    ->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte)
1219 
    using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0)
1220 
    ->packet with length 4 is not transmitted (length increasing by 1 byte)
1221 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
1222 
    using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3)
1223 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
1224 
    using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4)
1225 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
1226 
    using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5)
1227 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
1228 
    using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6)
1229 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
1230 
    using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7)
1231 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
1232 
  Time: 540893355000
1233 
  TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps )
1234 
    ->packet with length 1535 sent
1235 
    ->packet with length 1536 sent
1236 
    ->packet with length 1537 sent
1237 
    ->packet with length 104 sent
1238 
  Time: 544722915000
1239 
  TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps )
1240 
    ->packet with length 1535 sent
1241 
    ->packet with length 1536 sent
1242 
    ->packet with length 1537 sent
1243 
    ->packet with length 104 sent
1244 
  Time: 545120475000
1245 
  TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps )
1246 
    ->packet with length 116 sent
1247 
    ->packet with length 117 sent
1248 
    ->packet with length 118 sent
1249 
  Time: 545448195000
1250 
  TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps )
1251 
    ->packet with length 116 sent
1252 
    ->packet with length 117 sent
1253 
    ->packet with length 118 sent
1254 
  Time: 545490315000
1255 
  TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps )
1256 
    ->packet with length 1358 sent
1257 
    ->packet with length 1359 sent
1258 
    ->packet with length 1360 sent
1259 
  Time: 548798595000
1260 
  TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps )
1261 
    ->packet with length 1358 sent
1262 
    ->packet with length 1359 sent
1263 
    ->packet with length 1360 sent
1264 
  Time: 549139275000
1265 
  TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps )
1266 
   i_length = 1531
1267 
   eth_phy length = 1535
1268 
    ->packet with length 1535 sent
1269 
   i_length = 1532
1270 
   eth_phy length = 1536
1271 
    ->packet with length 1536 sent
1272 
   i_length = 1533
1273 
   eth_phy length = 1537
1274 
    ->packet with length 1537 sent
1275 
   i_length = 65530
1276 
   eth_phy length = 65534
1277 
    ->packet with length 65534 sent
1278 
   i_length = 65531
1279 
   eth_phy length = 65535
1280 
    ->packet with length 65535 sent
1281 
  Time: 657784995000
1282 
  TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps )
1283 
   i_length = 1531
1284 
   eth_phy length = 1535
1285 
    ->packet with length 1535 sent
1286 
   i_length = 1532
1287 
   eth_phy length = 1536
1288 
    ->packet with length 1536 sent
1289 
   i_length = 1533
1290 
   eth_phy length = 1537
1291 
    ->packet with length 1537 sent
1292 
   i_length = 65530
1293 
   eth_phy length = 65534
1294 
    ->packet with length 65534 sent
1295 
   i_length = 65531
1296 
   eth_phy length = 65535
1297 
    ->packet with length 65535 sent
1298 
  Time: 668694675000
1299 
  TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps )
1300 
    ->IPG with 8 mtx_clk periods (min 3) between packets with lengths 64 and 65 checked
1301 
    ->IPG with 8 mtx_clk periods (min 4) between packets with lengths 66 and 67 checked
1302 
    ->IPG with 8 mtx_clk periods (min 5) between packets with lengths 68 and 69 checked
1303 
    ->IPG with 8 mtx_clk periods (min 6) between packets with lengths 70 and 71 checked
1304 
    ->IPG with 7 mtx_clk periods (min 7) between packets with lengths 72 and 73 checked
1305 
    ->IPG with 8 mtx_clk periods (min 8) between packets with lengths 74 and 75 checked
1306 
    ->IPG with 9 mtx_clk periods (min 9) between packets with lengths 76 and 77 checked
1307 
    ->IPG with 10 mtx_clk periods (min 10) between packets with lengths 78 and 79 checked
1308 
    ->IPG with 17 mtx_clk periods (min 17) between packets with lengths 80 and 81 checked
1309 
    ->IPG with 24 mtx_clk periods (min 24) between packets with lengths 82 and 83 checked
1310 
    ->IPG with 38 mtx_clk periods (min 38) between packets with lengths 84 and 85 checked
1311 
    ->IPG with 72 mtx_clk periods (min 72) between packets with lengths 86 and 87 checked
1312 
    ->IPG with 130 mtx_clk periods (min 130) between packets with lengths 88 and 89 checked
1313 
  Time: 670752195000
1314 
  TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps )
1315 
    ->IPG with 47 mtx_clk periods (min 3) between packets with lengths 64 and 65 checked
1316 
    ->IPG with 47 mtx_clk periods (min 4) between packets with lengths 66 and 67 checked
1317 
    ->IPG with 44 mtx_clk periods (min 5) between packets with lengths 68 and 69 checked
1318 
    ->IPG with 45 mtx_clk periods (min 6) between packets with lengths 70 and 71 checked
1319 
    ->IPG with 44 mtx_clk periods (min 7) between packets with lengths 72 and 73 checked
1320 
    ->IPG with 43 mtx_clk periods (min 8) between packets with lengths 74 and 75 checked
1321 
    ->IPG with 45 mtx_clk periods (min 9) between packets with lengths 76 and 77 checked
1322 
    ->IPG with 44 mtx_clk periods (min 10) between packets with lengths 78 and 79 checked
1323 
    ->IPG with 43 mtx_clk periods (min 17) between packets with lengths 80 and 81 checked
1324 
    ->IPG with 45 mtx_clk periods (min 24) between packets with lengths 82 and 83 checked
1325 
    ->IPG with 44 mtx_clk periods (min 38) between packets with lengths 84 and 85 checked
1326 
    ->IPG with 72 mtx_clk periods (min 72) between packets with lengths 86 and 87 checked
1327 
    ->IPG with 130 mtx_clk periods (min 130) between packets with lengths 88 and 89 checked
1328 
  Time: 671018715000
1329 
  TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps )
1330 
    ->under-run on 61. byte
1331 
    ->under-run on 62. byte
1332 
    ->under-run on 63. byte
1333 
    ->under-run on 64. byte
1334 
    ->under-run on 65. byte
1335 
    ->under-run on 66. byte
1336 
    ->under-run on 67. byte
1337 
    ->under-run on 68. byte
1338 
    ->under-run on 69. byte
1339 
    ->under-run on 70. byte
1340 
    ->under-run on 71. byte
1341 
    ->under-run on 72. byte
1342 
    ->under-run on 73. byte
1343 
    ->under-run on 74. byte
1344 
    ->under-run on 75. byte
1345 
    ->under-run on 76. byte
1346 
    ->under-run on 77. byte
1347 
    ->under-run on 78. byte
1348 
    ->under-run on 79. byte
1349 
    ->no under-run on 80. byte, since length of frame (without CRC) is only 80 bytes
1350 
    ->no under-run on 81. byte, since length of frame (without CRC) is only 80 bytes
1351 
    ->no under-run on 82. byte, since length of frame (without CRC) is only 80 bytes
1352 
    ->no under-run on 83. byte, since length of frame (without CRC) is only 80 bytes
1353 
    ->no under-run on 84. byte, since length of frame (without CRC) is only 80 bytes
1354 
  Time: 674812635000
1355 
  TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps )
1356 
    ->under-run on 61. byte
1357 
    ->under-run on 62. byte
1358 
    ->under-run on 63. byte
1359 
    ->under-run on 64. byte
1360 
    ->under-run on 65. byte
1361 
    ->under-run on 66. byte
1362 
    ->under-run on 67. byte
1363 
    ->under-run on 68. byte
1364 
    ->under-run on 69. byte
1365 
    ->under-run on 70. byte
1366 
    ->under-run on 71. byte
1367 
    ->under-run on 72. byte
1368 
    ->under-run on 73. byte
1369 
    ->under-run on 74. byte
1370 
    ->under-run on 75. byte
1371 
    ->under-run on 76. byte
1372 
    ->under-run on 77. byte
1373 
    ->under-run on 78. byte
1374 
    ->under-run on 79. byte
1375 
    ->no under-run on 80. byte, since length of frame (without CRC) is only 80 bytes
1376 
    ->no under-run on 81. byte, since length of frame (without CRC) is only 80 bytes
1377 
    ->no under-run on 82. byte, since length of frame (without CRC) is only 80 bytes
1378 
    ->no under-run on 83. byte, since length of frame (without CRC) is only 80 bytes
1379 
    ->no under-run on 84. byte, since length of frame (without CRC) is only 80 bytes
1380 
 
1381 
MAC FULL DUPLEX RECEIVE TEST
1382 
  Time: 675288647000
1383 
  TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps )
1384 
  Time: 684922639000
1385 
  TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps )
1386 
  Time: 686451079000
1387 
  TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps )
1388 
    8 packets (without this one) are checked - packets are received by two in a set
1389 
    From this moment:
1390 
    first one of two packets (including this one) is not accepted due to late RX enable
1391 
    ->RX enable set 3 WB clks after RX_DV
1392 
  Time: 726629929000
1393 
  TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps )
1394 
 
1395 
    From this moment:
1396 
    first one of two packets (including this one) is not accepted due to late RX enable
1397 
    ->RX enable set 2 WB clks after RX_DV
1398 
  Time: 731956609000
1399 
  TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps )
1400 
    receive small packets is NOT selected
1401 
    ->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte)
1402 
    receive small packets is selected
1403 
    ->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes)
1404 
    receive small packets is NOT selected
1405 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
1406 
  Time: 765608449000
1407 
  TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps )
1408 
    receive small packets is NOT selected
1409 
    ->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte)
1410 
    receive small packets is selected
1411 
    ->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes)
1412 
    receive small packets is NOT selected
1413 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
1414 
  Time: 769183969000
1415 
  TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps )
1416 
    receive small packets is NOT selected
1417 
    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)
1418 
    ->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte)
1419 
    ->all packets were received on RX BD 0
1420 
    receive small packets is NOT selected
1421 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
1422 
    ->packets with lengths from 72 to 192 are checked (length increasing by 1 byte)
1423 
    ->packets were received on RX BD 0 to RX BD 120 respectively
1424 
    receive small packets is selected
1425 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
1426 
    ->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes)
1427 
    ->packets were received from RX BD 121 to RX BD 127 and from RX BD 0 to RX BD 2 respectively
1428 
    receive small packets is NOT selected
1429 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
1430 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
1431 
    ->packets were received from RX BD 3 to RX BD 18 respectively
1432 
  Time: 810685755000
1433 
  TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps )
1434 
    receive small packets is NOT selected
1435 
    using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0)
1436 
    ->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte)
1437 
    ->all packets were received on RX BD 0
1438 
    receive small packets is NOT selected
1439 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
1440 
    ->packets with lengths from 72 to 192 are checked (length increasing by 1 byte)
1441 
    ->packets were received on RX BD 0 to RX BD 120 respectively
1442 
    receive small packets is selected
1443 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
1444 
    ->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes)
1445 
    ->packets were received from RX BD 121 to RX BD 127 and from RX BD 0 to RX BD 2 respectively
1446 
    receive small packets is NOT selected
1447 
    using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127)
1448 
    ->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte)
1449 
    ->packets were received from RX BD 3 to RX BD 18 respectively
1450 
  Time: 815124075000
1451 
  TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps )
1452 
    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)
1453 
    ->packets with lengths from 0 to 3 are not received (length increasing by 1 byte)
1454 
    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)
1455 
    ->packet with length 4 is not received (length increasing by 1 byte)
1456 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
1457 
    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)
1458 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
1459 
    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)
1460 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
1461 
    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)
1462 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
1463 
    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)
1464 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
1465 
    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)
1466 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
1467 
    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)
1468 
    ->packets with lengths from 70 to 77 are checked (length increasing by 1 byte)
1469 
  Time: 818552775000
1470 
  TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps )
1471 
    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)
1472 
    ->packets with lengths from 0 to 3 are not received (length increasing by 1 byte)
1473 
    using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120)
1474 
    ->packet with length 4 is not received (length increasing by 1 byte)
1475 
    ->packets with lengths from 5 to 9 are checked (length increasing by 1 byte)
1476 
    using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123)
1477 
    ->packets with lengths from 10 to 17 are checked (length increasing by 1 byte)
1478 
    using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124)
1479 
    ->packets with lengths from 18 to 27 are checked (length increasing by 1 byte)
1480 
    using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125)
1481 
    ->packets with lengths from 28 to 40 are checked (length increasing by 1 byte)
1482 
    using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126)
1483 
    ->packets with lengths from 41 to 54 are checked (length increasing by 1 byte)
1484 
    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)
1485 
    ->packets with lengths from 55 to 69 are checked (length increasing by 1 byte)
1486 
    using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127)
1487 
    ->packets with lengths from 70 to 77 are checked (length increasing by 1 byte)
1488 
  Time: 819023025000
1489 
  TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps )
1490 
    Unicast packet is going to be received with PRO bit (wrap at 1st BD)
1491 
    ->packet received
1492 
    Unicast packet is going to be received without PRO bit (wrap at 1st BD)
1493 
    ->packet received
1494 
    non Unicast packet is going to be received with PRO bit (wrap at 1st BD)
1495 
    ->packet received
1496 
    non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD)
1497 
    ->packet NOT received
1498 
    Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)
1499 
    ->packet received
1500 
    Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD)
1501 
    ->packet received
1502 
    Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)
1503 
    ->packet received
1504 
    Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD)
1505 
    ->packet NOT received
1506 
  Time: 819573439000
1507 
  TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps )
1508 
    Unicast packet is going to be received with PRO bit (wrap at 1st BD)
1509 
    ->packet received
1510 
    Unicast packet is going to be received without PRO bit (wrap at 1st BD)
1511 
    ->packet received
1512 
    non Unicast packet is going to be received with PRO bit (wrap at 1st BD)
1513 
    ->packet received
1514 
    non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD)
1515 
    ->packet NOT received
1516 
    Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD)
1517 
    ->packet received
1518 
    Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD)
1519 
    ->packet received
1520 
    Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD)
1521 
    ->packet received
1522 
    Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD)
1523 
    ->packet NOT received
1524 
  Time: 819653959000
1525 
  TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps )
1526 
    packet shoud be successfuly received
1527 
    ->packet received
1528 
  Time: 819724969000
1529 
*E RX buffer descriptor status is not correct: 6000 instead of 4000
1530 
    packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun
1531 
    ->packet NOT received
1532 
  Time: 819789048000
1533 
*E WB INT signal should not be set
1534 
  Time: 819789409000
1535 
*E Any of interrupts was set, interrupt reg: 10, len: 0
1536 
    packet should NOT be received - RX FIFO overrun
1537 
    ->packet NOT received
1538 
  Time: 819853248000
1539 
*E WB INT signal should not be set
1540 
  Time: 819853609000
1541 
*E Any of interrupts was set, interrupt reg: 10, len: 0
1542 
    ->previous packet written into MEM
1543 
  Time: 819857689000
1544 
*E RX buffer descriptor status is not correct: c000 instead of 4000
1545 
  Time: 819857809000
1546 
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10
1547 
  Time: 819857809000
1548 
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10
1549 
    packet shoud be successfuly received
1550 
    ->packet NOT received
1551 
  Time: 819928129000
1552 
*E RX buffer descriptor status is not correct: c000 instead of 4000
1553 
  Time: 819928129000
1554 
*E Wrong length of the packet out from PHY (0 instead of 72)
1555 
  Time: 819928147000
1556 
*E Wrong data of the received packet
1557 
  Time: 819928249000
1558 
*E Interrupt Receive Buffer was not set, interrupt reg: 10
1559 
  Time: 819928249000
1560 
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10
1561 
    packet should NOT be received - RX FIFO overrun
1562 
    ->packet NOT received
1563 
  Time: 819998688000
1564 
*E WB INT signal should not be set
1565 
  Time: 819999049000
1566 
*E Any of interrupts was set, interrupt reg: 10, len: 0
1567 
  Time: 820003129000
1568 
*E RX buffer descriptor status is not correct: c000 instead of 4040
1569 
  Time: 820003249000
1570 
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10
1571 
  Time: 820003249000
1572 
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10
1573 
    packet shoud be successfuly received
1574 
    ->packet NOT received
1575 
  Time: 820073689000
1576 
*E RX buffer descriptor status is not correct: c000 instead of 4000
1577 
  Time: 820073689000
1578 
*E Wrong length of the packet out from PHY (0 instead of 72)
1579 
  Time: 820073707000
1580 
*E Wrong data of the received packet
1581 
  Time: 820073809000
1582 
*E Interrupt Receive Buffer was not set, interrupt reg: 10
1583 
  Time: 820073809000
1584 
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10
1585 
    packet should NOT be received - RX FIFO overrun
1586 
    ->packet NOT received
1587 
  Time: 820153488000
1588 
*E WB INT signal should not be set
1589 
  Time: 820153849000
1590 
*E Any of interrupts was set, interrupt reg: 10, len: 0
1591 
  Time: 820157929000
1592 
*E RX buffer descriptor status is not correct: c000 instead of 4040
1593 
  Time: 820158049000
1594 
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10
1595 
  Time: 820158049000
1596 
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10
1597 
    packet shoud be successfuly received
1598 
    ->packet NOT received
1599 
  Time: 820238089000
1600 
*E RX buffer descriptor status is not correct: c000 instead of 4000
1601 
  Time: 820238089000
1602 
*E Wrong length of the packet out from PHY (0 instead of 84)
1603 
  Time: 820238110000
1604 
*E Wrong data of the received packet
1605 
  Time: 820238209000
1606 
*E Interrupt Receive Buffer was not set, interrupt reg: 10
1607 
  Time: 820238209000
1608 
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10
1609 
    packet shoud be successfuly received
1610 
    ->packet NOT received
1611 
  Time: 820318129000
1612 
*E RX buffer descriptor status is not correct: e000 instead of 6000
1613 
  Time: 820318129000
1614 
*E Wrong length of the packet out from PHY (0 instead of 84)
1615 
  Time: 820318150000
1616 
*E Wrong data of the received packet
1617 
  Time: 820318249000
1618 
*E Interrupt Receive Buffer was not set, interrupt reg: 10
1619 
  Time: 820318249000
1620 
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10
1621 
    packet should NOT be received - RX FIFO overrun due to lack of RX BDs
1622 
    ->packet NOT received
1623 
    packet shoud be successfuly received
1624 
    ->packet received
1625 
  Time: 820480969000
1626 
*E RX buffer descriptor status is not correct: 6000 instead of 4000
1627 
  Time: 820481329000
1628 
  TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps )
1629 
    packet shoud be successfuly received
1630 
    ->packet received
1631 
    packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun
1632 
    ->packet NOT received
1633 
    packet should NOT be received - RX FIFO overrun
1634 
    ->packet NOT received
1635 
    ->previous packet written into MEM
1636 
    packet shoud be successfuly received
1637 
    ->packet received
1638 
    packet should NOT be received - RX FIFO overrun
1639 
    ->packet NOT received
1640 
    packet shoud be successfuly received
1641 
    ->packet received
1642 
    packet should NOT be received - RX FIFO overrun
1643 
    ->packet NOT received
1644 
    packet shoud be successfuly received
1645 
    ->packet received
1646 
    packet shoud be successfuly received
1647 
    ->packet received
1648 
    packet should NOT be received - RX FIFO overrun due to lack of RX BDs
1649 
    ->packet NOT received
1650 
    packet shoud be successfuly received
1651 
    ->packet received
1652 
 
1653 
MAC FULL DUPLEX FLOW CONTROL TEST
1654 
  Time: 820600337000
1655 
  TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps )
1656 
  Time: 829991351000
1657 
  TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps )
1658 
  Time: 831022451000
1659 
  TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps )
1660 
  Time: 832234219000
1661 
  TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps )
1662 
  Time: 832383859000
1663 
  TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps )
1664 
   ->8 frames transmitted
1665 
   ->8 frames received
1666 
   ->8 frames transmitted
1667 
   ->8 frames received
1668 
   ->8 frames transmitted
1669 
   ->8 frames transmitted
1670 
   ->8 frames received
1671 
   ->8 frames transmitted
1672 
   ->8 frames received
1673 
   ->8 frames transmitted
1674 
   ->8 frames transmitted
1675 
   ->8 frames received
1676 
   ->8 frames transmitted
1677 
   ->8 frames received
1678 
   ->8 frames transmitted
1679 
   ->8 frames received
1680 
   ->8 frames transmitted
1681 
   ->8 frames transmitted
1682 
   ->8 frames received
1683 
   ->8 frames transmitted
1684 
   ->8 frames received
1685 
   ->8 frames transmitted
1686 
   ->8 frames transmitted
1687 
   ->8 frames received
1688 
   ->8 frames transmitted
1689 
   ->8 frames received
1690 
   ->8 frames transmitted
1691 
   ->8 frames received
1692 
   ->8 frames transmitted
1693 
   ->8 frames transmitted
1694 
   ->8 frames received
1695 
   ->8 frames transmitted
1696 
   ->8 frames received
1697 
   ->8 frames transmitted
1698 
   ->8 frames transmitted
1699 
   ->8 frames received
1700 
   ->8 frames transmitted
1701 
   ->8 frames received
1702 
   ->8 frames transmitted
1703 
   ->8 frames received
1704 
   ->8 frames transmitted
1705 
   ->8 frames transmitted
1706 
   ->8 frames received
1707 
   ->8 frames transmitted
1708 
   ->8 frames received
1709 
   ->8 frames transmitted
1710 
   ->8 frames transmitted
1711 
   ->8 frames received
1712 
   ->8 frames transmitted
1713 
   ->8 frames received
1714 
   ->8 frames transmitted
1715 
   ->8 frames received
1716 
   ->8 frames transmitted
1717 
   ->8 frames transmitted
1718 
   ->8 frames received
1719 
   ->8 frames transmitted
1720 
   ->8 frames received
1721 
   ->8 frames transmitted
1722 
   ->8 frames transmitted
1723 
   ->8 frames received
1724 
   ->8 frames transmitted
1725 
   ->8 frames received
1726 
   ->8 frames transmitted
1727 
   ->8 frames received
1728 
   ->8 frames transmitted
1729 
   ->8 frames transmitted
1730 
   ->8 frames received
1731 
   ->8 frames transmitted
1732 
   ->8 frames received
1733 
   ->8 frames transmitted
1734 
   ->8 frames transmitted
1735 
   ->8 frames received
1736 
   ->8 frames transmitted
1737 
   ->8 frames received
1738 
   ->8 frames transmitted
1739 
   ->8 frames received
1740 
   ->8 frames transmitted
1741 
   ->8 frames transmitted
1742 
   ->8 frames received
1743 
   ->8 frames transmitted
1744 
   ->8 frames received
1745 
   ->8 frames transmitted
1746 
   ->8 frames transmitted
1747 
   ->8 frames received
1748 
   ->8 frames transmitted
1749 
   ->8 frames received
1750 
   ->8 frames received
1751 
   ->8 frames received
1752 
   ->8 frames received
1753 
   ->8 frames received
1754 
   ->8 frames received
1755 
   ->8 frames received
1756 
   ->8 frames received
1757 
   ->8 frames received
1758 
   ->8 frames received
1759 
   ->8 frames received
1760 
   ->8 frames received
1761 
   ->8 frames received
1762 
   ->8 frames received
1763 
   ->8 frames received
1764 
  Time: 871127179000
1765 
  TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps )
1766 
   ->8 frames transmitted
1767 
   ->8 frames received
1768 
   ->8 frames transmitted
1769 
   ->8 frames received
1770 
   ->8 frames transmitted
1771 
   ->8 frames received
1772 
   ->8 frames transmitted
1773 
   ->8 frames received
1774 
   ->8 frames transmitted
1775 
   ->8 frames received
1776 
   ->8 frames transmitted
1777 
   ->8 frames transmitted
1778 
   ->8 frames received
1779 
   ->8 frames transmitted
1780 
   ->8 frames received
1781 
   ->8 frames transmitted
1782 
   ->8 frames received
1783 
   ->8 frames transmitted
1784 
   ->8 frames received
1785 
   ->8 frames transmitted
1786 
   ->8 frames received
1787 
   ->8 frames transmitted
1788 
   ->8 frames received
1789 
   ->8 frames transmitted
1790 
   ->8 frames transmitted
1791 
   ->8 frames received
1792 
   ->8 frames transmitted
1793 
   ->8 frames received
1794 
   ->8 frames transmitted
1795 
   ->8 frames received
1796 
   ->8 frames transmitted
1797 
   ->8 frames received
1798 
   ->8 frames transmitted
1799 
   ->8 frames received
1800 
   ->8 frames transmitted
1801 
   ->8 frames received
1802 
   ->8 frames transmitted
1803 
   ->8 frames transmitted
1804 
   ->8 frames received
1805 
   ->8 frames transmitted
1806 
   ->8 frames received
1807 
   ->8 frames transmitted
1808 
   ->8 frames received
1809 
   ->8 frames transmitted
1810 
   ->8 frames received
1811 
   ->8 frames transmitted
1812 
   ->8 frames received
1813 
   ->8 frames transmitted
1814 
   ->8 frames received
1815 
   ->8 frames transmitted
1816 
   ->8 frames transmitted
1817 
   ->8 frames received
1818 
   ->8 frames transmitted
1819 
   ->8 frames received
1820 
   ->8 frames transmitted
1821 
   ->8 frames received
1822 
   ->8 frames transmitted
1823 
   ->8 frames received
1824 
   ->8 frames transmitted
1825 
   ->8 frames received
1826 
   ->8 frames transmitted
1827 
   ->8 frames received
1828 
   ->8 frames transmitted
1829 
   ->8 frames transmitted
1830 
   ->8 frames received
1831 
   ->8 frames transmitted
1832 
   ->8 frames received
1833 
   ->8 frames transmitted
1834 
   ->8 frames received
1835 
   ->8 frames transmitted
1836 
   ->8 frames received
1837 
   ->8 frames transmitted
1838 
   ->8 frames received
1839 
   ->8 frames transmitted
1840 
   ->8 frames received
1841 
   ->8 frames transmitted
1842 
   ->8 frames transmitted
1843 
   ->8 frames received
1844 
   ->8 frames transmitted
1845 
   ->8 frames received
1846 
   ->8 frames transmitted
1847 
   ->8 frames received
1848 
   ->8 frames transmitted
1849 
   ->8 frames received
1850 
   ->8 frames transmitted
1851 
   ->8 frames received
1852 
   ->8 frames transmitted
1853 
   ->8 frames received
1854 
   ->8 frames transmitted
1855 
   ->8 frames transmitted
1856 
   ->8 frames received
1857 
   ->8 frames transmitted
1858 
   ->8 frames received
1859 
   ->8 frames received
1860 
   ->8 frames received
1861 
   ->8 frames received
1862 
   ->8 frames received
1863 
   ->8 frames received
1864 
   ->8 frames received
1865 
   ->8 frames received
1866 
 
1867 
MAC HALF DUPLEX FLOW TEST
1868 
  Time: 876116327000
1869 
  TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps )
1870 
    ->TX Defer occured
1871 
    ->IPGR2 timing checking
1872 
  Time: 876264399000
1873 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1874 
    ->TX Defer occured
1875 
    ->IPGR2 timing checking
1876 
  Time: 876422439000
1877 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1878 
    ->TX Defer occured
1879 
    ->IPGR2 timing checking
1880 
  Time: 876587679000
1881 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1882 
    ->TX Defer occured
1883 
    ->IPGR2 timing checking
1884 
  Time: 876753279000
1885 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1886 
    ->TX Defer occured
1887 
    ->IPGR2 timing checking
1888 
  Time: 876929619000
1889 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1890 
    ->TX Defer occured
1891 
    ->IPGR2 timing checking
1892 
  Time: 877096059000
1893 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1894 
    ->TX Defer occured
1895 
    ->IPGR2 timing checking
1896 
  Time: 877262859000
1897 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1898 
    ->TX Defer occured
1899 
    ->IPGR2 timing checking
1900 
  Time: 877429959000
1901 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1902 
    ->TX Defer occured
1903 
    ->IPGR2 timing checking
1904 
  Time: 877607619000
1905 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1906 
    ->TX Defer occured
1907 
  Time: 877635687000
1908 
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
1909 
    ->IPGR2 timing checking
1910 
  Time: 877826379000
1911 
*E Wrong data of the transmitted packet
1912 
    ->TX Defer occured
1913 
  Time: 877854487000
1914 
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
1915 
    ->IPGR2 timing checking
1916 
  Time: 877994859000
1917 
*E Wrong data of the transmitted packet
1918 
    ->Collision occured due to registered inputs
1919 
    ->IPGR2 timing checking
1920 
  Time: 878163519000
1921 
*E Wrong data of the transmitted packet
1922 
    ->Collision occured - last checking
1923 
  Time: 878264599000
1924 
*E Receive packet should be accepted
1925 
    ->IPGR2 timing checking
1926 
  Time: 878342599000
1927 
*E Wrong length of the packet out from PHY (0 instead of 68)
1928 
  Time: 878342616000
1929 
*E Wrong data of the received packet
1930 
  Time: 878342616000
1931 
*E RX buffer descriptor status is not correct: c000 instead of 6081
1932 
  Time: 878342859000
1933 
*E Wrong data of the transmitted packet
1934 
  Time: 878342959000
1935 
*E Interrupt Receive Error was not set, interrupt reg: 1
1936 
  Time: 878363025000
1937 
  TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps )
1938 
    ->TX Defer occured
1939 
    ->IPGR2 timing checking
1940 
  Time: 878385939000
1941 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1942 
    ->TX Defer occured
1943 
    ->IPGR2 timing checking
1944 
  Time: 878403099000
1945 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1946 
    ->TX Defer occured
1947 
    ->IPGR2 timing checking
1948 
  Time: 878420979000
1949 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1950 
    ->TX Defer occured
1951 
    ->IPGR2 timing checking
1952 
  Time: 878438859000
1953 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1954 
    ->TX Defer occured
1955 
    ->IPGR2 timing checking
1956 
  Time: 878463639000
1957 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1958 
    ->TX Defer occured
1959 
    ->IPGR2 timing checking
1960 
  Time: 878481519000
1961 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1962 
    ->TX Defer occured
1963 
    ->IPGR2 timing checking
1964 
  Time: 878499399000
1965 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1966 
    ->TX Defer occured
1967 
    ->IPGR2 timing checking
1968 
  Time: 878517399000
1969 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1970 
    ->TX Defer occured
1971 
    ->IPGR2 timing checking
1972 
  Time: 878542299000
1973 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1974 
    ->TX Defer occured
1975 
    ->IPGR2 timing checking
1976 
  Time: 878560299000
1977 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1978 
    ->TX Defer occured
1979 
    ->IPGR2 timing checking
1980 
  Time: 878578419000
1981 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1982 
    ->TX Defer occured
1983 
    ->IPGR2 timing checking
1984 
  Time: 878596539000
1985 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
1986 
    ->TX Defer occured
1987 
    ->IPGR2 timing checking
1988 
  Time: 878621559000
1989 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1990 
    ->TX Defer occured
1991 
    ->IPGR2 timing checking
1992 
  Time: 878639799000
1993 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1994 
    ->TX Defer occured
1995 
    ->IPGR2 timing checking
1996 
  Time: 878658039000
1997 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
1998 
    ->TX Defer occured
1999 
    ->IPGR2 timing checking
2000 
  Time: 878676399000
2001 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
2002 
    ->TX Defer occured
2003 
    ->IPGR2 timing checking
2004 
  Time: 878701539000
2005 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2006 
    ->TX Defer occured
2007 
    ->IPGR2 timing checking
2008 
  Time: 878719899000
2009 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2010 
    ->TX Defer occured
2011 
    ->IPGR2 timing checking
2012 
  Time: 878738259000
2013 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2014 
    ->TX Defer occured
2015 
    ->IPGR2 timing checking
2016 
  Time: 878756739000
2017 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
2018 
    ->TX Defer occured
2019 
    ->IPGR2 timing checking
2020 
  Time: 878782119000
2021 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2022 
    ->TX Defer occured
2023 
    ->IPGR2 timing checking
2024 
  Time: 878800599000
2025 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2026 
    ->TX Defer occured
2027 
    ->IPGR2 timing checking
2028 
  Time: 878819199000
2029 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2030 
    ->TX Defer occured
2031 
    ->IPGR2 timing checking
2032 
  Time: 878837919000
2033 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
2034 
    ->TX Defer occured
2035 
    ->IPGR2 timing checking
2036 
  Time: 878863419000
2037 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2038 
    ->TX Defer occured
2039 
    ->IPGR2 timing checking
2040 
  Time: 878882139000
2041 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2042 
    ->TX Defer occured
2043 
    ->IPGR2 timing checking
2044 
  Time: 878900859000
2045 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2046 
    ->TX Defer occured
2047 
    ->IPGR2 timing checking
2048 
  Time: 878919699000
2049 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
2050 
    ->TX Defer occured
2051 
    ->IPGR2 timing checking
2052 
  Time: 878945439000
2053 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2054 
    ->TX Defer occured
2055 
    ->IPGR2 timing checking
2056 
  Time: 878964279000
2057 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2058 
    ->TX Defer occured
2059 
    ->IPGR2 timing checking
2060 
  Time: 878983119000
2061 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2062 
    ->TX Defer occured
2063 
    ->IPGR2 timing checking
2064 
  Time: 879002079000
2065 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
2066 
    ->TX Defer occured
2067 
    ->IPGR2 timing checking
2068 
  Time: 879027939000
2069 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2070 
    ->TX Defer occured
2071 
    ->IPGR2 timing checking
2072 
  Time: 879046899000
2073 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2074 
    ->TX Defer occured
2075 
    ->IPGR2 timing checking
2076 
  Time: 879065979000
2077 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2078 
    ->TX Defer occured
2079 
    ->IPGR2 timing checking
2080 
  Time: 879085059000
2081 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
2082 
    ->TX Defer occured
2083 
    ->IPGR2 timing checking
2084 
  Time: 879111039000
2085 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2086 
    ->TX Defer occured
2087 
    ->IPGR2 timing checking
2088 
  Time: 879130239000
2089 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2090 
    ->TX Defer occured
2091 
    ->IPGR2 timing checking
2092 
  Time: 879149439000
2093 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2094 
    ->TX Defer occured
2095 
    ->IPGR2 timing checking
2096 
  Time: 879168759000
2097 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
2098 
    ->TX Defer occured
2099 
    ->IPGR2 timing checking
2100 
  Time: 879194859000
2101 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2102 
    ->TX Defer occured
2103 
    ->IPGR2 timing checking
2104 
  Time: 879214179000
2105 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2106 
    ->TX Defer occured
2107 
    ->IPGR2 timing checking
2108 
  Time: 879233499000
2109 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2110 
    ->TX Defer occured
2111 
    ->IPGR2 timing checking
2112 
  Time: 879252939000
2113 
*E TX buffer descriptor status is not correct: 7800 instead of 7802
2114 
    ->TX Defer occured
2115 
    ->IPGR2 timing checking
2116 
  Time: 879279279000
2117 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2118 
    ->TX Defer occured
2119 
    ->IPGR2 timing checking
2120 
  Time: 879298719000
2121 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2122 
    ->TX Defer occured
2123 
    ->IPGR2 timing checking
2124 
  Time: 879318279000
2125 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2126 
    ->TX Defer occured
2127 
  Time: 879322807000
2128 
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
2129 
    ->IPGR2 timing checking
2130 
  Time: 879342999000
2131 
*E Wrong data of the transmitted packet
2132 
    ->TX Defer occured
2133 
    ->IPGR2 timing checking
2134 
  Time: 879369459000
2135 
*E TX buffer descriptor status is not correct: 5800 instead of 5802
2136 
    ->TX Defer occured
2137 
  Time: 879374007000
2138 
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision
2139 
    ->IPGR2 timing checking
2140 
  Time: 879389139000
2141 
*E Wrong data of the transmitted packet
2142 
    ->Collision occured due to registered inputs
2143 
    ->IPGR2 timing checking
2144 
  Time: 879408819000
2145 
*E Wrong data of the transmitted packet
2146 
    ->Collision occured - last checking
2147 
  Time: 879420079000
2148 
*E Receive packet should be accepted
2149 
    ->IPGR2 timing checking
2150 
  Time: 879428239000
2151 
*E Wrong length of the packet out from PHY (0 instead of 68)
2152 
  Time: 879428256000
2153 
*E Wrong data of the received packet
2154 
  Time: 879428256000
2155 
*E RX buffer descriptor status is not correct: e000 instead of 6081
2156 
  Time: 879428499000
2157 
*E Wrong data of the transmitted packet
2158 
  Time: 879428599000
2159 
*E Interrupt Receive Error was not set, interrupt reg: 1
2160 
 
2161 
 
2162 
 END of SIMULATION
2163 
Simulation stopped via $stop(1) at time 879430815 NS + 0
2164 
/projects/ethernet/tadejm/ethernet/bench/verilog/tb_ethernet.v:530   $stop;
2165 
ncsim> quit

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