OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [sim/] [rtl_sim/] [run/] [run_eth_sim_regr.scr] - Blame information for rev 343

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 291 tadejm
#!/bin/csh -f
2
 
3
set arg_num = $#argv; # number of arguments
4
 
5
# current iterration
6
set iter = 1;
7
# number of tests with DEFINES + test with user defined constants!
8
set all_iterations = 3;
9
# ATS (Automatic Test System) parameter, which causes displaying 'OK'
10
# if all testcases finish OK.
11
set ok = 1;
12
 
13
# Process argument
14
set arg_waves = 0;
15
set arg_regression = 0;
16
 
17
if ($arg_num == 0) then
18
            echo "    Verification without any parameter !"
19
else
20
  if ($arg_num == 1) then
21
    if (("$1" == "waves") | ("$1" == "-w")) then
22
            @ arg_waves = 1;
23
            echo "    Verification with parameter : waves !"
24
    else
25
      if (("$1" == "regression") | ("$1" == "-r")) then
26
            @ arg_regression = 1;
27
            echo "    Verification with parameter : regression !"
28
      else
29
            echo "    Not correct parameter ( $1 )"
30
            echo "    Correct parameters are:"
31
            echo "      'waves' or '-w'"
32
            echo "      'regression' or '-r'"
33
            exit
34
      endif
35
    endif
36
  else
37
    if ($arg_num == 2) then
38
      if (("$1" == "waves") | ("$1" == "-w")) then
39
            @ arg_waves = 1;
40
        if (("$2" == "regression") | ("$2" == "-r")) then
41
            @ arg_regression = 1;
42
            echo "    Verification with parameter : waves, regression !"
43
        else
44
            echo "    Not correct parameter ( $2 )"
45
            echo "    Correct 2. parameter is:"
46
            echo "      'regression' or '-r'"
47
            exit
48
        endif
49
      else
50
        if (("$1" == "regression") | ("$1" == "-r")) then
51
            @ arg_regression = 1;
52
          if (("$2" == "waves") | ("$2" == "-w")) then
53
            @ arg_waves = 1;
54
            echo "    Verification with parameter : waves, regression !"
55
          else
56
            echo "    Not correct parameter ( $2 )"
57
            echo "    Correct 2. parameter is:"
58
            echo "      'waves' or '-w'"
59
            exit
60
          endif
61
        else
62
            echo "    Not correct parameter ( $1 )"
63
            echo "    Correct parameters are:"
64
            echo "      'waves' or '-w'"
65
            echo "      'regression' or '-r'"
66
            exit
67
        endif
68
      endif
69
    else
70
            echo "    Too many parameters ( $arg_num )"
71
            echo "    Maximum number of parameters is 2:"
72
            echo "      'waves' or '-w'"
73
            echo "      'regression' or '-r'"
74
            exit
75
    endif
76
  endif
77
endif
78
 
79
echo ""
80
echo "<<<"
81
echo "<<< Ethernet MAC VERIFICATION "
82
echo "<<<"
83
 
84
# ITERATION LOOP
85
iteration:
86
 
87
echo ""
88
echo "<<<"
89
echo "<<< Iteration ${iter}"
90
echo "<<<"
91
 
92
if ($arg_regression == 1) then
93
  if ($iter <= $all_iterations) then
94
    if ($iter == 1) then
95
        echo "<<< Defines:"
96
        echo "\tEthernet with GENERIC RAM"
97
        echo "-DEFINE REGR" > ../run/defines.args
98
    endif
99
    if ($iter == 2) then
100
        echo "<<< Defines:"
101
        echo "\tEthernet with XILINX DISTRIBUTED RAM"
102
        echo "-DEFINE REGR -DEFINE ETH_FIFO_XILINX" > ../run/defines.args
103
    endif
104
    if ($iter == 3) then
105
        echo "<<< Defines:"
106
        echo "\tEthernet with XILINX BLOCK RAM"
107
        echo "-DEFINE REGR -DEFINE XILINX_RAMB4" > ../run/defines.args
108
    endif
109
  endif
110
endif
111
 
112
# Run NC-Verilog compiler
113
echo ""
114
echo "\t@@@"
115
echo "\t@@@ Compiling sources"
116
echo "\t@@@"
117
 
118
# creating .args file for ncvlog and adding main parameters
119
echo "-cdslib ../bin/cds.lib" > ../run/ncvlog.args
120
echo "-hdlvar ../bin/hdl.var" >> ../run/ncvlog.args
121
echo "-logfile ../log/ncvlog.log" >> ../run/ncvlog.args
122
echo "-update" >> ../run/ncvlog.args
123
echo "-messages" >> ../run/ncvlog.args
124 292 tadejm
echo "-INCDIR ../../../bench/verilog" >> ../run/ncvlog.args
125
echo "-INCDIR ../../../rtl/verilog" >> ../run/ncvlog.args
126 291 tadejm
echo "-DEFINE SIM" >> ../run/ncvlog.args
127
# adding defines to .args file
128
if ($arg_regression == 1) then
129 292 tadejm
    cat ../run/defines.args >> ../run/ncvlog.args
130 291 tadejm
endif
131
# adding RTL and Sim files to .args file
132
cat ../bin/rtl_file_list.lst >> ../run/ncvlog.args
133
cat ../bin/sim_file_list.lst >> ../run/ncvlog.args
134
# adding device dependent files to .args file
135
cat ../bin/xilinx_file_list.lst >> ../run/ncvlog.args
136
 
137
ncvlog -file ../run/ncvlog.args# > /dev/null;
138
echo ""
139
 
140
 
141
# Run the NC-Verilog elaborator (build the design hierarchy)
142
echo ""
143
echo "\t@@@"
144
echo "\t@@@ Building design hierarchy (elaboration)"
145
echo "\t@@@"
146
ncelab -file ../bin/ncelab_xilinx.args# > /dev/null;
147
echo ""
148
 
149
 
150
# Run the NC-Verilog simulator (simulate the design)
151
echo ""
152
echo "\t###"
153
echo "\t### Running tests (this takes a long time!)"
154
echo "\t###"
155
 
156
# creating ncsim.args file for ncsim and adding main parameters
157
echo "-cdslib ../bin/cds.lib" > ../run/ncsim.args
158
echo "-hdlvar ../bin/hdl.var" >> ../run/ncsim.args
159
echo "-logfile ../log/ncsim.log" >> ../run/ncsim.args
160
echo "-messages" >> ../run/ncsim.args
161
if ($arg_waves == 1) then
162
  echo "-input ../bin/ncsim_waves.rc" >> ../run/ncsim.args
163
else
164
  echo "-input ../bin/ncsim.rc" >> ../run/ncsim.args
165
endif
166
echo "worklib.ethernet:fun" >> ../run/ncsim.args
167
 
168
ncsim -file ../run/ncsim.args# > /dev/null
169
if ($status != 0) then
170
  echo ""
171
  echo "TESTS couldn't start due to Errors!"
172
  echo ""
173
  exit
174
else
175
  if ($arg_regression == 1) then
176
    if ($arg_waves == 1) then
177
      mv ../out/waves.shm ../out/i${iter}_waves.shm
178
    endif
179
    # For ATS - counting all 'FAILED' words
180
    set FAIL_COUNT = `grep -c "FAILED" ../log/eth_tb.log`
181
    if ($FAIL_COUNT != 0) then
182
        # Test didn't pass!!!
183
        @ ok = 0;
184
    endif
185
    # Move 'log' files
186
    mv ../log/eth_tb.log ../log/i${iter}_eth_tb.log
187
    mv ../log/eth_tb_phy.log ../log/i${iter}_eth_tb_phy.log
188
    mv ../log/eth_tb_memory.log ../log/i${iter}_eth_tb_memory.log
189
    mv ../log/eth_tb_host.log ../log/i${iter}_eth_tb_host.log
190
    mv ../log/eth_tb_wb_s_mon.log ../log/i${iter}_eth_tb_wb_s_mon.log
191
    mv ../log/eth_tb_wb_m_mon.log ../log/i${iter}_eth_tb_wb_m_mon.log
192
  endif
193
endif
194
echo ""
195
 
196
@ iter += 1;
197
 
198
if (($arg_regression == 1) && ($iter <= $all_iterations)) then
199
    goto iteration
200
else
201
#   rm ./defines.args
202
    echo ""
203
    echo "<<<"
204
    echo "<<< End of VERIFICATION"
205
    echo "<<<"
206
    echo "<<<"
207
    echo "<<< -------------------------------------------------"
208
    echo "<<<"
209
    # For ATS - displaying 'OK' when tests pass successfuly
210
    echo " "
211
    echo "Simulation finished:"
212
    if ($ok == 1) then
213
        echo "OK"
214
    else
215
        echo "FAILED"
216
    endif
217
endif
218
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.