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[/] [ethmac10g/] [tags/] [V10/] [M2_1E.v] - Blame information for rev 72

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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date:    11:54:49 12/27/05
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// Design Name:
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// Module Name:    M2_1E
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// Project Name:
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module M2_1E(E, S0, D0, D1, O);
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    input E;
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    input S0;
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    input D0;
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    input D1;
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    output O;
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         wire M0,M1;
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         assign M0 = D0 & ~S0 & E;
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         assign M1 = D1 & S0 & E;
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         assign O = M0 | M1;
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endmodule

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