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////////////////////////////////////////////////////////////////////////////////

// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

////////////////////////////////////////////////////////////////////////////////

//   ____  ____ 

//  /   /\/   / 

// /___/  \  /    Vendor: Xilinx 

// \   \   \/     Version : 8.1.03i

//  \   \         Application : xaw2verilog

//  /   /         Filename : dcm0.v

// /___/   /\     Timestamp : 05/30/2006 09:16:54

// \   \  /  \ 

//  \___\/\___\ 

//

//Command: xaw2verilog -intstyle F:/10G/rx_engine_v2/dcm0.xaw -st dcm0.v

//Design Name: dcm0

//Device: xc2vp20-6fg676

//

// Module dcm0

// Generated by Xilinx Architecture Wizard

// Written for synthesis tool: XST

`timescale 1ns / 1ps

module dcm0(CLKIN_IN,

            RST_IN,

            CLKIN_IBUFG_OUT,

            CLK0_OUT,

            CLK180_OUT,

            LOCKED_OUT);

    input CLKIN_IN;

    input RST_IN;

   output CLKIN_IBUFG_OUT;

   output CLK0_OUT;

   output CLK180_OUT;

   output LOCKED_OUT;

   wire CLKFB_IN;

   wire CLKIN_IBUFG;

   wire CLK0_BUF;

   wire CLK180_BUF;

   wire GND1;

   assign GND1 = 0;

   assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;

   assign CLK0_OUT = CLKFB_IN;

   IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),

                           .O(CLKIN_IBUFG));

   BUFG CLK0_BUFG_INST (.I(CLK0_BUF),

                        .O(CLKFB_IN));

   BUFG CLK180_BUFG_INST (.I(CLK180_BUF),

                          .O(CLK180_OUT));

   DCM DCM_INST (.CLKFB(CLKFB_IN),

                 .CLKIN(CLKIN_IBUFG),

                 .DSSEN(GND1),

                 .PSCLK(GND1),

                 .PSEN(GND1),

                 .PSINCDEC(GND1),

                 .RST(RST_IN),

                 .CLKDV(),

                 .CLKFX(),

                 .CLKFX180(),

                 .CLK0(CLK0_BUF),

                 .CLK2X(),

                 .CLK2X180(),

                 .CLK90(),

                 .CLK180(CLK180_BUF),

                 .CLK270(),

                 .LOCKED(LOCKED_OUT),

                 .PSDONE(),

                 .STATUS());

   defparam DCM_INST.CLK_FEEDBACK = "1X";

   defparam DCM_INST.CLKDV_DIVIDE = 2.000000;

   defparam DCM_INST.CLKFX_DIVIDE = 1;

   defparam DCM_INST.CLKFX_MULTIPLY = 4;

   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";

   defparam DCM_INST.CLKIN_PERIOD = 6.400000;

   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "FIXED";

   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";

   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";

   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";

   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";

   defparam DCM_INST.FACTORY_JF = 16'hC080;

   defparam DCM_INST.PHASE_SHIFT = 0;

   defparam DCM_INST.STARTUP_WAIT = "FALSE";

endmodule